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? semiconductor components industries, llc, 2015 november, 2015 ? rev. 1 1 publication order number: ncv78713/d ncv78713 high efficiency buck single led driver with integrated current sensing for automotive front lighting the ncv78713 is a single-chip and high ef ficient buck single led driver designed for automotive front lighting applications like high beam, low beam, drl (daytime running light), turn indicator, fog light, static cornering, etc. the ncv78713 is in particular designed for high current leds and provides a complete solution to drive 1 led string of up-to 60 v. it includes 1 current regulator for the led string and required diagnostic features for automotive front lighting with a minimum of external components ? the chip doesn?t need any external sense resistor for the buck current regulation. the available output current and voltage can be customized for the led string. when more than 1 led channel is required on 1 module, the ncv78713 can be combined with ncv78723 devices, incorporating buck dual led driver. thanks to the spi programmability, one single hardware configuration can support various application platforms. features ? single chip ? buck topology ? 1 led string up-to 60 v ? high current capability up to 1.6 a dc ? high overall efficiency ? minimum of external components ? integrated high accuracy current sensing ? integrated switched mode buck current regulator ? average current regulation through the leds ? high operating frequencies to reduce inductor sizes ? low emc emission for led switching and dimming ? spi interface for dynamic control of system parameters ? fail safe operating (fso) mode, stand-alone mode typical applications ? high beam ? low beam ? drl ? position or park light ? turn indicator ? fog ? static cornering www.onsemi.com qfn24 case 485cs marking diagram see detailed ordering and shipping information on page 30 o f this data sheet. ordering information (note: microdot may be in either location) 24 1 n78713?0 awlyyww 1 n78713 = specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb?free package
ncv78713 www.onsemi.com 2 typical application schematic figure 1. typical application schematic vboost c csb v cc of mcu r_sdo external vdd supply c_dd sdo sdi sclk ledctrl rstb vdd test test1 test2 gnd exposed pad vinbck lbcksw vled vboost vboostm3v led-string l_bck d r_led lbcksw c_led c_bck on semiconductor led driver 1-channel buck ncv78713 c_m3v table 1. pin description component function typical value unit l_bck buck regulator coil (see buck regulator chapter for details) 47 h c_bck buck regulator output capacitor (see buck regulator chapter for details) 220 nf c_m3v capacitor for m3v regulator (see table 6 ? vboostm3v) nf c_dd v dd decoupling capacitor 470 nf c_led optional vled pin filter capacitor (note 2) 1 nf r_led vled pin serial resistor (notes 2 and 3) min. 1 k r_sdo spi pull-up resistor 1 k d buck regulator free-wheeling diode e.g. mbrs2h100t3g 1. pin test has to be connected to ground. test1 and test2 pins can be connected to ground or left floating. 2. c_led is optional. if used, time constant of the c_led and r_led filter has to be lower than minimal ledctrl on time in pwm dimming for proper vled measurement. 3. r_led is necessary to ensure absolute maximum ratings of ivled current (see table 3).
ncv78713 www.onsemi.com 3 block diagram figure 2. block diagram vboostm3v vdd bandgap vref por bias osc 5 v input ledctrl 5 v input/ od output sdo lv ios test digital control gnd buck vboostm3v regulator vinbck temp dividers mux vboost, vdd, vled lbcksw vboost predriver current sense cmp ctrl vled adc sclk csb sdi test1 test2 otp rstb exposed pad
ncv78713 www.onsemi.com 4 esd schematic figure 3. esd schematic 5 1 4 3 vboostm3v test test2 vboost 14 18 24 15 nc vinbck sdo csb 23 13 rstb nc vdd 22 nc 21 nc 20 nc 19 nc 6 gnd 2 7 8 9 10 11 12 17 sdi 16 sclk test1 vled nc lbcksw nc ledctrl self prot pdmos
ncv78713 www.onsemi.com 5 package and pin description figure 4. pin connections test test1 vboostm3v gnd vboost test2 2 3 4 1 6 5 nc 22 23 24 19 20 21 sdi sclk csb sdo rstb vdd 15 16 17 18 13 14 vled gnd/nc vinbck lbcksw ledctrl gnd/nc 7 8 9 11 12 10 ncv78713 nc nc nc nc nc table 2. pin description pin no. pin name description i/o type 1 test test pin lv in 2 test1 test pin lv in/out hv tolerant 3 vboostm3v vboostm3v regulator output pin hv out (supply) 4 vboost booster input voltage pin hv supply 5 test2 test pin lv in/out hv tolerant 6 gnd ground ground 7 vled led string forward voltage sense input hv in 8 lbcksw buck switch output hv out 9, 11 gnd/nc gnd/nc connection in application nc 10 vinbck buck high voltage supply hv supply 12 ledctrl led string enable mv in 13 rstb external reset signal mv in 14 sdo spi data output mv open-drain 15 csb spi chip select (chip select bar) mv in 16 sclk spi clock mv in 17 sdi spi data input mv in 18 vdd 3 v logic supply lv supply 19, 20, 21, 22, 23, 24 nc gnd/nc connection in the application nc
ncv78713 www.onsemi.com 6 table 3. absolute maximum ratings characteristic symbol minimum maximum unit vboost supply voltage v boost ?0.3 +68 v vinbck supply voltage (note 4) vinbck max of vboostm3v ? 0.3, ?0.3 min of v boost + 0.3, 68 v vboostm3v supply voltage (note 5) vboostm3v max of v boost ? 3.6, ?0.3 min of v boost + 0.3, 68 v vled sense voltage vled ?0.3 min of v boost + 0.3, 68 v logic supply voltage (note 6) v dd ?0.3 3.6 v medium voltage io pins (note 7) iomv ?0.3 7.0 v test pins (note 8) testx ?0.3 min of v boost + 0.3, 68 v buck switch low side (note 4) lbcksw ?2.0 vinbck + 0.3 v vled sink/source current ivled ?30 30 ma storage temperature (note 9) t strg ?50 150 c the exposed pad (note 10) expad gnd ? 0.3 gnd + 0.3 v electrostatic discharge on component level (note 11) human body model charge device model v esd_hbm v esd_cdm ?2 ?500 +2 +500 kv v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 4. v(vinbck ? lbcksw) < 70 v, the driver in off state. 5. the vboostm3v regulator in off state. 6. absolute maximum rating for pins: vdd, test. also valid for relative difference v boost ? vboostm3v. 7. absolute maximum rating for pins: sclk, csb, sdi, sdo, ledctrl, rstb. the c interface pins (the iomv pins) accept 5 v while the device is in the power-off mode (v dd = 0 v). 8. absolute maximum rating for pins: test1, test2. 9. for limited time up to 100 hours. otherwise the max storage temperature is 85 c. 10. the exposed pad must be hard wired to gnd pin in an application to ensure both electrical and thermal connection. 11. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec q100 002 (eia/jesd22 a114) esd charge device model tested per eia/jesd22 c101 latch-up current maximum rating: 100 ma per jedec standard: jesd78 operating ranges define the limits for functional operation and parametric characteristics of the device. a mission profile (note 12) is a substantial part of the operation conditions; hence the customer must contact on semiconductor in order to mutually agree in writing on the allowed missions profile(s) in the application. table 4. recommended operating ranges characteristic symbol min typ max unit boost supply voltage v boost +8 +67 v vinbck supply voltage (note 13) vinbck v boost ? 0.1 v boost v boost + 0.1 v low voltage supply v dd 3.05 3.3 3.6 v buck switch output current i_lbcksw 1.9 a functional operating junction temperature range (note 14) t jf ?40 155 c parametric operating junction temperature range (note 15) t jp ?40 150 c the exposed pad connection (note 16) exposed_pad gnd ? 0.1 gnd gnd + 0.1 v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 12. a mission profile describes the application specific conditions such as, but not limited to, the cumulative operating condit ions over life time, the system power dissipation, the system?s environmental conditions, the thermal design of the customer?s system, the modes, in which the device is operated by the customer, etc. no more than 100 cumulated hours in life time above t tw . 13. hard connection of vinbck to vboost on pcb. 14. the circuit functionality is not guaranteed outside the functional operating junction temperature range. also please note th at the device is verified on bench for operation up to 170 c but that the production test guarantees 155 c only. 15. the parametric characteristics of the circuit are not guaranteed outside the parametric operating junction temperature range . 16. the exposed pad must be hard wired to gnd pin in an application to ensure both electrical and thermal connection.
ncv78713 www.onsemi.com 7 table 5. thermal resistance characteristic package symbol min typ max unit thermal resistance junction to exposed pad (note 17) qfn24 5x5 r thjp ? 5 ? c/w 17. includes also typical solder thickness under the exposed pad (ep). table 6. electrical characteristics (all min and max parameters are guaranteed over full junction temperature (t jp ) range (?40 c; 150 c), unless otherwise specified) characteristic symbol condition min typ max unit vdd: 3 v low voltage analog and digital supply the vdd current consumption i_vdd ? ? 6 ma por toggle level on vdd rising por 3v_h 2.7 ? 3.05 v por toggle level on vdd falling por 3v_l 2.45 ? 2.8 v por hysteresis por 3v_hyst 0.01 0.2 0.75 v otp uv toggle level on vboost otp_uv 13 ? 15 v otp uv toggle level hysteresis otp_uv_hyst 0.01 0.2 0.75 v vboostm3v: high side auxiliary supply vbstm3 regulator output voltage v bstm3 referenced to vboost ?3.6 ?3.3 ?3.0 v dc output current consumption m3v_iout ? 5 28 (note 18) ma output current limitation m3v_ilim ? ? 200 ma vbstm3 external decoupling cap. c vbstm3v referenced to vboost 0.3 ? 2.2 f vbstm3 ext. decoupling cap. esr c vbstm3v _esr referenced to vboost ? ? 200 m osc10m: system oscillator clock system oscillator frequency fosc10m 8 10 12 mhz adc for measuring v boost , v dd , v led , temp adc resolution adc_res ? 8 ? bits nonlinearity integral (inl) differential (dnl) adc_inl adc_dnl best fitting straight line method ?1.5 ?2.0 ? ? +1.5 +2.0 lsb full path gain error for measurements of v dd , v led , v boost adc_gainer ?3.25 ? 3.25 % offset at output of adc adc_offset ?2 ? 2 lsb time for 1 sar conversion adc_conv full conversion of 8 bits 6.67 8 10 s adc full scale for v dd measurement adcfs_vdd 3.87 4 4.13 v adc full scale for v led measurement adcfs_vled00 adcfs_vled01 adcfs_vled10 adcfs_vled11 the v led range code is ?00? the v led range code is ?01? the v led range code is ?10? the v led range code is ?11? 67.725 48.375 38.700 29.025 70 50 40 30 72.275 51.625 41.300 30.975 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 18. v boost = 68 v, v led = 34 v, f buck = 2 mhz, maximum total gate charge for activated buck channel q gate = 14 nc.
ncv78713 www.onsemi.com 8 table 6. electrical characteristics (continued) (all min and max parameters are guaranteed over full junction temperature (t jp ) range (?40 c; 150 c), unless otherwise specified) characteristic unit max typ min condition symbol adc for measuring v boost , v dd , v led , temp adc full scale for v boost measurement adcfs_vbst 67.725 70 72.275 v adc full scale for temp. measurement adcfs_temp 193.5 200 206.5 c tsd threshold level adc_tsd adc measurement of junction temperature 163 169 175 c v led input impedance vled_res 210 ? 650 k buck regulator ? switch on resistance, range 1 rdson1 at room-temperature, i(vinbck) = 0.18 a, v(boost ? vinbck) 0.2 v ? ? 5.2 on resistance at hot, range 1 rdson1_hot at tj = 150 c, i(vinbck) = 0.18 a, v(boost ? vinbck) 0.2 v ? ? 7.2 on resistance, range 2 rdson2 at room-temperature, i(vinbck) = 0.375 a, v(boost ? vinbck) 0.2 v ? ? 2.6 on resistance at hot, range 2 rdson2_hot at tj = 150 c, i(vinbck) = 0.375 a, v(boost ? vinbck) 0.2 v ? ? 3.6 on resistance, range 3 rdson3 at room-temperature, i(vinbck) = 0.75 a, v(boost ? vinbck) 0.2 v ? ? 1.3 on resistance at hot, range 3 rdson3_hot at tj = 150 c, i(vinbck) = 0.75 a, v(boost ? vinbck) 0.2 v ? ? 1.8 on resistance, range 4 rdson4 at room-temperature, i(vinbck) = 1.5 a, v(boost ? vinbck) 0.2 v ? ? 0.65 on resistance at hot, range 4 rdson4_hot at tj = 150 c, i(vinbck) = 1.5 a, v(boost ? vinbck) 0.2 v ? ? 0.9 switching slope ? on phase t rise ? 3 ? v/ns switching slope ? off phase (note 19) t fall ? 3 ? v/ns buck regulator ? current regulation current sense threshold level, range 1, min value ithr1_000 [buck_vthr = 00000000] end of the buck on-phase 23.905 28.125 32.344 ma current sense threshold level, range 1, spec. value ithr1_110 [buck_vthr = 01101110] end of the buck on-phase. min. value for specified precision ? 112.5 ? ma current sense threshold level, range 1, max value ithr1_255 [buck_vthr = 1 1111111] end of the buck on-phase ? 224.15 ? ma current sense threshold level, range 2, min value ithr2_000 [buck_vthr = 00000000] end of the buck on-phase 47.813 56.25 64.688 ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 19. falling switching slope depends on used current (range, current sense threshold level) and free-wheeling diode capacitance.
ncv78713 www.onsemi.com 9 table 6. electrical characteristics (continued) (all min and max parameters are guaranteed over full junction temperature (t jp ) range (?40 c; 150 c), unless otherwise specified) characteristic unit max typ min condition symbol buck regulator ? current regulation current sense threshold level, range 2, spec. value ithr2_110 [buck_vthr = 01101110] end of the buck on-phase. min. value for specified precision ? 225 ? ma current sense threshold level, range 2, max value ithr2_255 [buck_vthr = 1 1111111] end of the buck on-phase ? 448.3 ? ma current sense threshold level, range 3, min value ithr3_000 [buck_vthr = 00000000] end of the buck on-phase 95.625 112.5 129.375 ma current sense threshold level, range 3, spec. value ithr3_110 [buck_vthr = 01101110] end of the buck on-phase. min. value for specified precision ? 450 ? ma current sense threshold level, range 3, max value ithr3_255 [buck_vthr = 1 1111111] end of the buck on-phase ? 896.6 ? ma current sense threshold level, range 4, min value ithr4_000 [buck_vthr = 00000000] end of the buck on-phase 191.25 225 258.75 ma current sense threshold level, range 4, spec. value ithr4_110 [buck_vthr = 01101110] end of the buck on-phase. min. value for specified precision ? 900 ? ma current sense threshold level, range 4, max value ithr4_255 [buck_vthr = 1 1111111] end of the buck on-phase ? 1791.75 ? ma current sense threshold increase per code, range 1 ithr1 8 bit, linear increase ? 0.77 ? ma current sense threshold increase per code, range 2 ithr2 8 bit, linear increase ? 1.54 ? ma current sense threshold increase per code, range 3 ithr3 8 bit, linear increase ? 3.08 ? ma current sense threshold increase per code, range 4 ithr4 8 bit, linear increase ? 6.15 ? ma current threshold accuracy only with trimming constant for the highest range (note 20) ithr_err_dd specified for buck_vthr 01101110, without the delta of the trimming code and without temp. compensation ?8 ? +8 % current threshold accuracy without temperature compensation (note 20) ithr_err_d specified for buck_vthr 01101110, with the delta of the trimming code and without temp. compensation ?6 ? +6 % current threshold accuracy (note 20) ithr_err specified for buck_vthr 01101110, the delta of the trimming code and temp. compensation ?3 ? +3 % over-current detection level, range 1 ocdr1 typ. 1.5 ithr1_255 286 ? 388 ma over-current detection level, range 2 ocdr2 typ. 1.5 ithr2_255 573 ? 776 ma over-current detection level, range 3 ocdr3 typ. 1.5 ithr3_255 1148 ? 1553 ma over-current detection level, range 4 ocdr4 typ. 1.5 ithr4_255 2295 ? 3105 ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 20. measured as comparator dc threshold value, without comparator delay and switch falling slope.
ncv78713 www.onsemi.com 10 table 6. electrical characteristics (continued) (all min and max parameters are guaranteed over full junction temperature (t jp ) range (?40 c; 150 c), unless otherwise specified) characteristic unit max typ min condition symbol buck regulator ? current regulation time constant for longest off time tc_00 [buck_toff = 00000] ? 50 ? sv time constant for shortest off time tc_31 [buck_toff = 1 1111] ? 5 ? sv t off time relative error toff_err tc = t off v led @ vled > 2 v, t off > 350 ns ?10 ? +10 % t off time absolute error toff_err_abs tc = t off v led @ vled > 2 v, t off 350 ns ?35 ? +35 ns time constant decrease per code tc 5 bits, exponential decrease ? 7.16 ? % detection level of v led to be too low vled_lmt 1.62 1.8 1.98 v t off time for low v led voltages tc_low vled < vled_lmt 78 105 120 s openled detection time ton_open 40 50 60 s buck minimum t on time ton_min for vinbck ? lbcksw < 2.4 v, no failure at lbcksw pin 50 ? 250 ns delay from buck isens comparator input voltage balance to buck switch going off isenscmp_del isens cmp. over-drive ramp > 1 mv/10 ns ? 70 ? ns 5 v tolerant digital inputs (sclk, csb, sdi, ledctrl, rstb) high-level input voltage vinhi 2 ? ? v low-level input voltage vinlo ? ? 0.8 v pull resistance (note 21) r pull 40 ? 160 k led pwm propagation delay (note 22) buck_sw_del activation time of the buck switch from the ledctrl pin 4.4 5.5 6.95 s sampling resolution ledctrl_sr ? 100 125 ns rstb debouncer time rstb_deb ? 100 200 ns 5 v tolerant open-drain digital output (sdo) low-voltage output voltage voutlo i out = ?10 ma (current flows into the pin) ? ? 0.4 v equivalent output resistance rdson low-side switch ? 10 40 sdo pin leakage current sdo_ileak ? ? 2 a sdo pin capacitance sdo_c ? ? 10 pf clk to sdo propagation delay sdo_dl low-side switch activation/deactivation time; @1k to 5 v, 100 pf to gnd, for falling edge v(sdo) goes below 0.5 v ? ? 60 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 21. pull down resistor (r pd ) for rstb, ledctrl, sdi and sclk, pull up resistor (r pu ) for csb to vdd. 22. jitter is present due to the internal resynchronization.
ncv78713 www.onsemi.com 11 table 6. electrical characteristics (continued) (all min and max parameters are guaranteed over full junction temperature (t jp ) range (?40 c; 150 c), unless otherwise specified) characteristic unit max typ min condition symbol 3 v digital inputs (test, test1, test2) high-level input voltage vin3hi 2.3 ? ? v low-level input voltage vin3lo ? ? 0.8 v pull resistance r pd3 pull-down resistance ? ? 60 k spi interface csb setup time t css 0.5 ? ? s csb hold time t csh 0.25 ? ? s sclk low time t wl 0.5 ? ? s sclk high time t wh 0.5 ? ? s data-in (din) setup time, valid data before rising edge of clk t su 0.25 ? ? s data-in (din) hold time, hold data after rising edge of clk t h 0.275 ? ? s output (dout) disable time (note 23) t dis 0.08 ? 0.32 s output (dout) valid (note 23) t v1 0 ? ? 0.32 s output (dout) valid (note 24) t v0 1 ? ? 0.32 + t (rc) s output (dout) hold time t ho 0.01 ? ? s csb high time t cs 1 ? ? s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 23. sdo low-side switch activation time. 24. time depends on the sdo load and pull-up resistor. figure 5. spi communication timing din15 dout15 dout14 dout13 dout1 dout0 din14 din13 din1 din0 hi?z din csb dout sclk v ih v il initial state of sclk after csb falling edge is don?t care, it can be low or high hi?z v ih v il v ih v il v ih v il t cs t csh t dis t wl t wh t ho t v t h t su t css
ncv78713 www.onsemi.com 12 typical characteristics figure 6. buck peak current vs. ranges and vthr code 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 32 64 96 128 160 192 224 256 buck current threshold (ma) buck vthr code (?) 110 ithr = 1 ithr = 2 ithr = 3 ithr = 4 +0.77 ma/step in range 1 +1.54 ma/step in range 2 +3.08 ma/step in range 3 +6.15 ma/step in range 4 225 ma at vthr = 0 in range 4 112.5 ma at vthr = 0 in range 3 56.25 ma at vthr = 0 in range 2 28.125 ma at vthr = 0 in range 1 1791.15 ma at vthr = 255 in range 4 896.6 ma at vthr = 255 in range 3 448.3 ma at vthr = 255 in range 2 224.15 ma at vthr = 255 in range 1 accuracy ( 3%/ 6%/ 8%) guaranteed from vthr code 110 [dec] figure 7. typical temperature behavior of buck switch r dson relative to the value at 150 c 0 20 40 60 80 100 120 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 temperature ( c) buck r dson relative to value at 150 c (%)
ncv78713 www.onsemi.com 13 typical characteristics figure 8. typical temperature dependency of t off v led constant (shortest t off v led = 5 s v and longest t off v led = 50 s v) 4.90 ?40 0 40 80 120 temperature ( c) t off v led ( s v) 4.95 5.00 5.05 5.10 5.15 5.20 t off ? v led = 5 s ? v 48.0 49.0 50.0 51.0 52.0 ?40 0 40 80 120 temperature ( c) t off v led ( s v) t off ? v led = 50 s ? v figure 9. typical comparator delay vs. slope slope (a/ s) (for range 4*) delay (ns) 0 20 40 60 80 100 120 140 0.001 0.01 0.1 1 10 ?40 c 25 c 150 c * in lower ranges, the same current slope (a/s) translates into a higher voltage slope (v/s) at the input of the comparator, because of the higher r dson . resulting equations for all ranges: range 4: comp. delay [ns] = (0.0365 temp [ c] ? 10.41) ln(slope [a/ s, range 4]) + 46 range 3: comp. delay [ns] = (0.0365 temp [ c] ? 10.41) ln(slope 2 [a/ s, range 4]) + 46 range 2: comp. delay [ns] = (0.0365 temp [ c] ? 10.41) ln(slope 4 [a/ s, range 4]) + 46 range 1: comp. delay [ns] = (0.0365 temp [ c] ? 10.41) ln(slope 8 [a/ s, range 4]) + 46
ncv78713 www.onsemi.com 14 detailed operating description supply concept in general two voltages have to be supplied to the ncv78713 chip ? low voltage vdd logic supply and high voltage vboost for providing energy to the buck regulator. more detailed description follows. vdd supply the vdd supply is the low voltage digital and analog supply for the chip. ncv78713 does not contain internal vdd regulator and this voltage is supposed to be provided externally by a dedicated voltage regulator that fulfills specified voltage and current needs or can be supplied from the ncv78702/ncv78703 vdd pin. the power-on-reset circuit (por) monitors the vdd voltage and rstb pin to control the out-of-reset and reset entering state. at power-up, the chip will exit from reset state when vdd > por3v_h and rstb pin is in ?log. 1?. no spi communication is possible in reset state. vboost supply the vboost supply voltage is the main high voltage supply for the chip. the voltage is supposed to be provided by booster chip such as ncv78702/ncv78703 or ncv878763 in an application. vinbck pin has to be connected by low impedance track to this supply to ensure proper buck performance. the vboost voltage is monitored by under-voltage comparator to check suf ficient zapping voltage at vboost pin during otp programming operation. vboostm3v supply the vboostm3v is the high side auxiliary supply for the gate drive of the buck regulator?s integrated high-side p-mosfet switch. this supply receives energy directly from the vboost pin. internal clock generation ? osc10m an internal rc clock named osc10m is used to run all the digital functions in the chip. the clock is trimmed in the factory prior to delivery. its accuracy is guaranteed under full operating conditions and is independent from external component selection (refer to table 6 ? osc10m: system oscillator clock for details). all timings depend on osc10m accuracy. buck regulator general the ncv78713 contains one high-current integrated buck current regulator, which is the source for the led string. the buck is powered from the external booster regulator. buck current regulation principle buck controls the inductor peak current (i buckpeak ) and incorporates a constant ripple ( i buckpkpk ) control circuit to ensure also stable average current through the led string, independently from the string voltage. the buck average current is in fact described by the formula: i buck avg i buck peak i buck pkpk 2 (eq. 1) this is graphically exemplified by figure 10. figure 10. buck regulator controlled average current time buck current buck peak current buck average current buck current ripple = t off_ v led_ i spi / l buc k t off the parameter i buckpeak is programmable through the device by means of the internal registers for range selection buck_isens_thr[1:0] and code buck_vthr[7:0]. the formula that defines the total ripple current over the buck inductor is also hereby reported: i buck pkpk t off v led v diode l buck (eq. 2) t off v led l buck t off _ v led _ i spi l buck in the formula above, t off represents the buck switch off time, v led is the led voltage feedback sensed at the ncv78713 vled pin and l buck is the buck inductance value. the parameter t off _v led _i spi is programmable by spi (buck_toff[4:0] register), with values related to table 6 ? buck regulator ? current regulation . in order to achieve a constant ripple current value, the device varies the t off time inversely proportional to the v led sensed at the device pin, according to the selected factor t off _v led _i spi . as a consequence to the constant ripple control and variable off time, the buck switching frequency depends on the boost voltage and led voltage in the following way: f buck v boost v led v boost 1 t off (eq. 3) v boost v led v boost v led t off _ v led _ i spi
ncv78713 www.onsemi.com 15 the led average current in time (dc) is equal to the buck time average current. therefore, to achieve a given led current tar get, it is sufficient to know the buck peak current and the buck current ripple. a rule of thumb is to count a minimum of 50% ripple reduction by means of the capacitor c buck and this is normally obtained with a low cost ceramic component ranging from 100 nf to 470 nf (such values are typically used at connector sides anyway, so this is included in a standard bom). the following figure reports a typical example waveform: figure 11. led current ac components filtered out by output impedance (oscilloscope snapshot) the use of c buck is a cost ef fective way to improve emc performances without the need to increase the value of l buck , which would be certainly a far more expensive solution. figure 12. buck regulator circuit diagram led string c d vled lbcksw vinbck l vboost vboostm3v c m3v power stage driver i sense /oc digital control constant ripple control vboostm3v reg. vboost supply
ncv78713 www.onsemi.com 16 sw compensation of the buck current accuracy in order to ensure buck current accuracy as specified in table 6 ? buck regulator ? current regulation, set of constants trimmed during manufacturing process is available. microcontroller should use them in the following way: to reach 8% accuracy ( 6% for range 4) over whole temperature operating range: all ranges: buck_isens_trim[6:0] = buck_isens_rng[6:0] buck_isens_rng[6:0] is trimming constant for the highest current range (range 4) at hot temperature. buck_isens_rng[6:0] constant is loaded into buck_isens_trim[6:0] register automatically after the reset of the device. to reach 6% accuracy over whole temperature operating range: buck_isens_dx[3:0] registers, meaning delta of the trimming constant with respect to the higher current range at hot temperature, have to be used. trimming constant for the particular range at hot temperature can be then calculated as: range 4: buck_r4_trim_hot = buck_isens_rng[6:0] , range 3: buck_r3_trim_hot = buck_isens_rng[6:0] + buck_isens_d3[3:0] , range 2: buck_r2_trim_hot = buck_isens_rng[6:0] + buck_isens_d3[3:0] + buck_isens_d2[3:0] , range 1: buck_r1_trim_hot = buck_isens_rng[6:0] + buck_isens_d3[3:0] + buck_isens_d2[3:0] + buck_isens_d1[3:0] , where: delta of the trimming constant buck_isens_dx[3:0] is signed, coded as two?s complement. range of this constant is decadic , binary <1000; 0111>. calculated trimming constant has to be then written into trimming spi register: buck_isens_trim[6:0] = buck_ry_trim_hot to reach 3% accuracy over whole temperature operating range: in addition to buck_isens_dx[3:0] registers, the buck_isens_tcx[3:0] registers, meaning temperature coef ficients for the appropriate ranges, have to be used. trimming value for a certain temperature can be then calculated as: range 4: buck_r4_trim = buck_r4_trim_hot + k l3 (tj ? thot) + k q (tj ? thot) 2 , range 3: buck_r3_trim = buck_r3_trim_hot + k l2 (tj ? thot) + k q (tj ? thot) 2 , range 2: buck_r2_trim = buck_r2_trim_hot + k l1 (tj ? thot) + k q (tj ? thot) 2 , range 1: buck_r1_trim = buck_r0_trim_hot + k l0 (tj ? thot) + k q (tj ? thot) 2 , where: buck temperature coefficient buck_isens_tcx[3:0] is signed, coded as two?s complement. range of this constant is decadic , binary <1000; 0111>, k lx is linear coefficient for each current range calculated: k lx = (buck_isens_tcx[3:0] ? k q (170 c) 2 )/(?170 c) [code/ c] k q is quadratic constant for all current ranges: k q = 2.18 10 ?4 [code/( c) 2 ] tj is junction temperature in c calculated from vtemp[7:0] spi register value according to the equation defined in chapter adc: device temperature adc: v temp . thot temperature is constant equal to 125 c. calculated trimming constant has to be then written into trimming spi register : buck_isens_trim[6:0] = buck_ry_trim note : the buck_isens_trim[6:0] spi register allows compensation of the peak current app. in range 40 % from actual value according to the following equation: ibuck = (ithrx_000 + ithrx buck_vthr[7:0]) (1 + 0.4 ((buck_isens_trim[6:0] ? 63)/63)), where: ithrx_000 is current for vthr code 0 in ithrx range (see table 6 ? buck regulator ? current regulation), ithrx code step in range ithrx (see table 6 ? buck regulator ? current regulation).
ncv78713 www.onsemi.com 17 buck overcurrent protection being a current regulator, the ncv78713 buck is by nature preventing overcurrent in all normal situations. however, in order to protect the system from overcurrent even in case of failures, protection mechanism is available. this protection is based on internal sensing over the buck switch: when the peak current rises above the maximum limit (ocdrx level, see t able 6 ? buck regulator ? current regulation), an internal counter starts to increment at each period, until the count written in buck_oc_occmp _ thr[1:0] + 1 is attained. the count is reset if the current drops below ocdrx level or the buck channel is disabled and also at each dimming cycle. from the moment the count is reached onwards, the buck is kept continuously off, until the spi error flag ocled is read. after reading the flag, the buck is automatically re-enabled and will try to regulate the current again. dimming the ncv78713 supports both analog and digital dimming (or so called pwm dimming). analog dimming is performed by controlling the led amplitude current during operation. this can be done by means of changing the peak current level and/or the t off _v led _i spi constants by spi commands (see buck regulator section). in this section, we only describe pwm dimming as this is the preferred method to maintain the desired led color temperature for a given current rating. in pwm dimming, the led current waveform frequency is constant and the duty cycle is set according to the required light intensity. in order to avoid the beats effect, the dimming frequency should be set at ?high enough? values, typically above 300 hz. pwm dimming is controlled externally by means of ledctrl input. digital dimming in digital dimming, the buck activation is transparently linked to the logic status of the ledctrl pin, which handles dimming signal. the only difference is the controlled phase shift of typical 5.5 s (table 6 ? 5v tolerant digital inputs) that allows synchronized measurements of the vled pin via the adc (see dedicated section for more details). as the phase shift is applied both to rising edges and falling edges, with a very limited jitter, the pwm duty cycle is not affected. apart from the phase shift and the system clock osc10m, there is no limitation to the pwm duty cycle values or resolutions at the buck, which is a copy of the reference provided at the input. figure 13. buck current digital or pwm dimming dim_t on dim_t dim_duty = dim_t on / dim_t = dim_t on ? f zoom: buck inductor switching current adc general the built-in analog to digital converter (adc) is an 8-bit successive approximation register (sar). this embedded peripheral can be used to provide the following measurements to the external micro controller unit (mcu): ? vboost voltage: sampled at the vboost pin ? vdd voltage: sampled at the vdd pin ? vledon voltage ? vled voltage ? vtemp measurement (chip temperature) the internal ncv78713 adc state machine samples all the above channels automatically, taking care for setting the analog mux and storing the converted values in memory. the external mcu can read out all adc measured values via the spi interface, in order to take application specific decisions. please note that none of the mcu spi commands interfere with the internal adc state machine sample and conversion operations: the mcu will always get the last available data at the moment of the register read. the state machine sampling and conversion scheme is represented in the figure below. figure 14. adc sample and conversion main sequence v dd sample & convert v boost sample & convert v temp sample & convert v boost sample & convert update led_sel_dur count; when counter ripples, trigger vled interrupt for once
ncv78713 www.onsemi.com 18 referring to the figure above, the typical rate for a full sar plus digital conversion per channel is 8 s (table 6 ? adc for measuring vboost, vdd, vled, temp). for instance, each new vboost adc converted sample occurs at 16 s typical rate, whereas for both the vdd and vtemp channel the sampling rate is typically 32 s, that is to say a complete cycle of the depicted sequence. this time is referred to as tadc_seq. if the spi setting led_sel_dur[8:0] is not zero, then interrupts for the vled measurements are allowed at the points marked with a rhombus, with a minimum cadence corresponding to the number of the elapsed adc sequences (forced interrupt). in formulas: t vled_int_forced led_sel_dur[8 : 0] t adc_seq (eq. 4) in general, prior to the forced interrupt status, the vled on adc interrupts are generated when a falling edge on the control line for the buck is detected by the device. in case of digital dimming , this interrupt start signal corresponds to the ledctrl falling edge together with a controlled phase delay (table 6 ? 5 v tolerant digital inputs). the purpose of the phase delay is to allow completion the ongoing adc conversion before starting the one linked to the vled interrupt: if at the moment of the conversion ledctrl pin is logic high, then the updated registers are vledon[7:0] and vled[7:0]; otherwise, if ledctrl pin is logic low, the only register refreshed is vled[7:0]. this mechanism is handled automatically by the ncv78713 logic without need of intervention from the user, thus drastically reducing the mcu cycles and embedded firmware and cpu cycles overhead that would be otherwise required. a flow chart referring to the adc interrupts is also displayed. figure 15. adc vled interrupt sequence interrupts enabled? yes no v led synchronization signal? v led sample & convert no yes proceed to next step in the adc sequence all ncv78713 adc registers data integrity is protected by odd parity on the bit 8 (that is to say the 9th bit if counting from the lsbit named ?0?). please refer to the spi map section for further details. logic supply voltage adc: v dd the logic supply voltage is sampled at vdd pin. the (8-bit) conversion ratio is 4/255 (v/dec) = 0.0157 (v/dec) typical. the converted value can be found in the spi register vdd[7:0], protected with odd parity bit. boost voltage adc: v boost this measurement refers to the boost voltage at the vboost pin, with an 8 bit conversion ratio of 70/255 (v/dec) = 0.274 (v/dec) typical, result can be found inside the spi register vboost[7:0]. the value is protected by odd parity bit. this measurement can be used by the mcu for diagnostics and booster control loop monitoring. device temperature adc: v temp by means of the vtemp measurement, the mcu can monitor the device junction temperature (t j ) over time. the conversion formula is: t j (vtemp[7 : 0] 50.5) 0.805 (eq. 5) vtemp[7:0] is the value read out directly from the related 8bit-spi register (please refer to the spi map). the value is also used internally by the device for the thermal warning and thermal shutdown functions. more details on these two can be found in the dedicated sections in this document. the value is protected by odd parity bit. led string voltage adc: v led , v ledon the voltage at the pin vled is measured. there are 4 ranges available, that can be selected by means of adc_vled_rng_sel[1:0] register, to obtain higher resolution for led voltage measurement. conversion ratios in dependency on selected range are: 0x0: 70/255 (v/dec) = 0.274 (v/dec); 0x1: 50/255 (v/dec) = 0.196 (v/dec); 0x2: 40/255 (v/dec) = 0.157 (v/dec); 0x3: 30/255 (v/dec) = 0.118 (v/dec). this information, found in registers vledon[7:0] and vled[7:0], can be used by the mcu to infer about the led string status, for example, individual shorted leds. as for the other adc registers, the values are protected by odd parity. please note that in the case of constant ledctrl inputs and no dimming (in other words dimming duty cycle equals to 0% or 100%) the vled interrupt is forced with a rate equal to t vled_int_forced , given in the adc general section. this feature can be exploited by mcu embedded algorithm diagnostics to read the led channel voltage even when in off state, before module outputs activation (module startup pre-check).
ncv78713 www.onsemi.com 19 diagnostics the ncv78713 features a wide range of embedded diagnostic features. their description follows. please also refer to the previous spi section for more details. diagnostic description ? thermal warning: this mechanism detects a user-programmable junction temperature which is in principle close, but lower, to the chip maximum allowed, thus providing the information that some action (power de-rating) is required to prevent overheating that would cause thermal shutdown. a typical power de-rating technique consists in reducing the output dimming duty cycle in function of the temperature: the higher the temperature above the thermal warning, the lower the duty cycle. the thermal warning flag (tw) is given in status register 0x14 and is latched. when vtemp[7:0] raises to or above thermal_warning_thr[7:0] threshold, the tw flag is set. at power up the default thermal warning threshold is typically 159 c (spi code 179). ? thermal shutdown: this safety mechanism intends to protect the device from damage caused by overheating, by disabling the both buck channels. the diagnostic is displayed per means of the tsd bit in status register 0x14 (latched). once occurred, the thermal shutdown condition is exited when the temperature drops below the thermal warning level, thus providing hysteresis for thermal shutdown recovery process. output is re-enabled automatically if buck_tsd_aut_rcrv_en = 1, or it is re-enabled by rising edge on buck_en if buck_tsd_aut_rcrv_en = 0. the application thermal design should be made as such to avoid the thermal shutdown in the worst case conditions. the thermal shutdown level is not user programmable and is factory trimmed (see adc_tsd in table 6 ? buck regulator ? switch). ? spi error: in case of spi communication errors the spierr bit in status register 0x14 is set. the bit is latched. for more details, please refer to section ?spi protocol: framing and parity error?. ? open led string: open led diagnostic flag indicates whether the string is detected open. the detection is based on a counter overflow of typical 50 s when the channel is activated. openled flag (latched) is contained in status register 0x13. please note that the open detection does not disable the buck channel(s). ? short led string: a short circuit detection is available per means of the flag shortled (non-latched, status register 0x13). the detection is based on the voltage measured at the vled pin via a dedicated internal comparator: when the voltage drops below the vled_lmt minimum threshold (typical 1.8 v, see table 6 ? buck regulator ? current regulation) the flag is set. together with the detection, a fixed toff is used. note that the detection is active also when the led channel is off (in this case the fixed toff does not play any role). ? overcurrent: this diagnostics protects the led and the buck electronics from overcurrent. as the overcurrent is detected, the ocled flag (latched, status register 0x13) is raised and the buck channel is disabled. more details about the detection mechanisms and parameters are given in section ?buck overcurrent protection?. ? buck status: register buck_status shows the actual status of buck output. when buck_status is 1, the output regulates current to the led. ? ledctrl pin status: spi register ledval indicates the actual logic level of the debounced ledctrl pin. this signal follows the output of 200 ns digital debouncer implemented on ledctrl pin. ? buck running at minimum ton time: register buck_min_ton (latched) indicates that minimal ton time is detected on the buck channel. it is clear by read flag. this information can be used for detection of transition period during which the buck output current decreases due to the change of buck_vthr code or buck_isens_thr range. ? buck ton time duration: spi register buck_ton_dur[7:0] reflects the last measured buck ton time (1lsb = 200 ns) on the corresponding channel. when buck runs with ton time < typ. 200 ns, the buck_ton_dur[7:0] spi register returns value 0x00. when buck is stopped, the buck_ton_dur[7:0] register keeps the last measured ton time. ? hw reset: the out of reset condition is reported through the hwr bit (latched). this bit is set only at each power on reset (por) and indicates the device is ready to operate. a short summary table of the main diagnostic bits related to the led outputs follows.
ncv78713 www.onsemi.com 20 table 7. led output diagnostic summary diagnose detection level led output latched flag description tw thermal warning spi register programmable not disabled (if no tsd, otherwise disabled) yes tsd thermal shutdown factory trimmed disabled (automatically re-enabled when temp falls below tw and buck_tsd_aut_rcvr_en = 1) yes spierr spi error (see spi section) not disabled yes openled led string open circuit buck on time > ton_open not disabled yes shortled led string short circuit vled < vled_lmt not disabled (fixed buck toff applied when output is on) no ocled led string overcurrent ibuck > ocdr{1..4} disabled yes figure 16. led dimming state diagram mode = reset (0) tsd = 1 (1) tsd = 1 (1) tsd = 1 (1) off led is off dimming normal mode: led is on if ledctrl = 1 fso/standalone mode: led is on ocled = 0 and buck_en = 1 (2) ocled = 1 or buck_en = 0 (2) buck_tsd_aut_rcvr_en = 1 or rising edge on buck_en detected (3) vtemp < thermal_warning_thr(1) (buck_tsd_aut_rcvr_en = 1 or rising edge on buck_en detected) and (ocled = 1 or buck_en = 0) (2) transition priority (0) ? highest (1) (2) (3) ? lowest recovery led is off tsd led is off
ncv78713 www.onsemi.com 21 functional mode description overview of all functional modes is in accordance to the state diagram on figure 17. individual states are described below. figure 17. functional modes state diagram transition condition (priority level) action executed when transition is performed transition priority: (0) ? highest (1) (2) ? lowest reset spi disabled dimming disabled hwr:=1 por (0) init spi disabled dimming disabled otp refresh ongoing rstb = 0 (1) rstb = 1 (1) rstb = 0 and (fso_md = 000 or 001 or 110 or 111) (1) rstb = 0 (1) rstb = 0 and (fso_md = 010 or 011 or 100 or 101) and otp_cust_lock = 1 (2) spi pre-load from otps fso:=1 normal spi enabled dimming: ledctrl fso spi enabled when fso_md = 010 or 100 dimming: buck_en rstb = 1 or (fso_md = 000 or 001) (1) fso_md = 000 or 001 (2) (fso_md = 110 or 111) and otp_cust_lock = 1 (2) spi pre-load from otps fso:=1 standalone spi disabled when fso_md = 110 dimming: buck_en 150 s timeout expired (2) spi pre-load from otps when fso_md = 001 or 100 or 101 or 110 or 111
ncv78713 www.onsemi.com 22 reset asynchronous reset is caused either by por (por always causes asynchronous reset ? transition to reset state) or by falling edge on rstb pin (in normal/stand-alone mode, when fso_md[2:0] = 000 or 001 or 110 or 111). init and normal mode normal mode is entered through init state after internal delay of 150 s. in init state, otp refresh is performed. if otp bits for fso_md[2:0] register and otp lock bit are programmed, transition to fso/sa mode is possible. fso/stand-alone mode fso (fail-safe operation)/stand-alone modes can be used for two main purposes: ? default power-up operation of the chip ( stand-alone functionality without external microcontroller or preloading of the registers with default content for default operation before microcontroller starts sending spi commands for chip settings) ? fail-safe functionality (chip functionality definition in fail-safe mode when the external microcontroller functionality is not guaranteed) fso/stand-alone function is controlled according to table 8. entrance into fso/stand-alone mode is possible only after customer otp zapping when otp lock bit is set. after fso mode activation, the fso bit in status register is set. fso register is cleared by read register. when fso/stand-alone mode is activated, content of the following spi registers is preloaded from otp memory: buck_vthr[7:0], buck_isens_thr[1:0], buck_toff[4:0], buck_en, fso_md[2:0], buck_tsd_aut_rcvr_en, buck_oc_occmp_thr[1:0]. buck_isens_trim[6:0] register is preloaded from buck_isens_rng[6:0] register. in fso (entered via falling edge on rstb pin) and stand-alone modes, buck_en is controlled from spi register map (spi registers are updated from otp?s after entrance into these modes). buck_en is supposed to be set ?1? for the buck operation in the fso/stand-alone mode. when control registers are pre-loaded from otp?s after por and fso mode is not entered (valid for fso_md[2:0] = 100 or 101), buck_en is kept inactive (?0?) until the first valid spi operation is finished to avoid potential activation of buck regulator immediately after por (to prevent undefined state of ledctrl pin in case mcu leaves por later than ncv78713). in fso and stand-alone modes, the logic level at ledctrl pin is ignored and digital pwm dimming with ledctrl pin is not available. the output can be dimmed only by means of buck_en register. a falling edge on rstb pin may trigger either entrance into fso mode or reset in dependency on fso_md[2:0] register value. please refer to t able 8 and figure 17 for more details. once fso mode is entered via falling edge on rstb pin, reset function of rstb pin is blocked until fso mode is exited. fso mode can be exited by the rising edge on rstb pin or by writing fso_md[2:0] = 000 or 001 (possible only in fso modes, where spi control register update is allowed: fso_md[2:0] = 011 or 101). in stand-alone mode (fso_md[2:0] = 110 or 111), rstb has always reset functionality. during entrance into fso mode, value of fso_md[2:0] spi register (preloaded from otp) is latched into internal register and all fso related functions are then controlled according to it. purpose is to avoid the reset of the device when fso mode is active and fso_md[2:0] is changed to value corresp onding to stand-alone mode, where rstb pin has reset functionality. the internal register is cleared after por or when fso mode is exited.
ncv78713 www.onsemi.com 23 figure 18. rstb pin functionality in normal, stand-alone and fso modes rstb in normal or stand-alone mode reset mode (no spi) normal mode normal mode (spi possible) power-up possible otp pre-load possible otp pre-load rstb porb (internal) reset mode power-up otp pre-load otp pre-load rstb porb (internal) otp pre-load rstb in fso mode fso mode (spi possible/no spi) normal mode normal mode (spi possible) fso mode table 8. fso modes fso_md[2:0] description 000 b = 0 fso mode disabled, registers are loaded with safe value = 0x00h after por, default ? after the reset, control registers are loaded with 0x00h value. ? entrance into fso mode is not possible ? rstb pin has reset functionality ? ledctrl pin is functional (buck enable/disable, digital pwm dimming available) 001 b = 1 fso mode disabled, registers are loaded with data from otp memory after por ? after the reset, control registers are loaded with data stored in otp memory (device?s otp memory has to be programmed, otp lock bit has to be set). it reduces number of spi transfers needed to configure the device after the reset. ? entrance into fso mode is not possible ? rstb pin has reset functionality ? ledctrl pin is functional (buck enable/disable, digital pwm dimming available) 010 b = 2 fso entered after falling edge on rstb pin, registers are loaded with safe value = 0x00h after por ? after fso mode activation, control registers are loaded with data stored in otp memory. ? spi register update (spi write/read operation) in fso mode is disabled (spi write operation is blocked; clearing of spi registers is blocked; in case of invalid spi frame, spierr flag is set). ? rstb pin serves to enter/exit fso mode. ? ledctrl pin is not functional (buck enable/disable only by means of buck_en spi/otp bit, digital pwm dimming not available). 011 b = 3 fso entered after falling edge on rstb pin, registers are loaded with safe value = 0x00h after por ? after fso mode activation, control registers are loaded with data stored in otp memory. ? spi register update (spi write/read operation) in fso mode is enabled ? fso mode can be exited by writing fso_md[2:0] = 000 ? rstb pins serves to enter/exit fso mode. ? ledctrl pin is not functional (buck enable/disable only by means of buck_en spi/otp bit, digital pwm dimming not available). 100 b = 4 fso entered after falling edge on rstb pin, registers are loaded with data from otp memory after por ? after fso mode activation, control registers are loaded with data stored in otp memory. ? spi register update (spi write/read operation) in fso mode is disabled (spi write operation is blocked; clearing of spi registers is blocked; in case of invalid spi frame, spierr flag is set). ? rstb pin serves to enter/exit fso mode. ? ledctrl pin is not functional (buck enable/disable only by means of buck_en spi/otp bit, digital pwm dimming not available).
ncv78713 www.onsemi.com 24 table 8. fso modes (continued) fso_md[2:0] description 101 b = 5 fso entered after falling edge on rstb pin, registers are loaded with data from otp memory after por ? after fso mode activation, control registers are loaded with data stored in otp memory. ? spi register update (spi write/read operation) in fso mode is enabled ? fso mode can be exited by writing fso_md[2:0] = 000 ? rstb pin serves to enter/exit fso mode. ? ledctrl pin is not functional (buck enable/disable only by means of buck_en spi/otp bit, digital pwm dimming not available). 110 b = 6 sa (stand-alone)/fso entered after por (rstb pin rising edge), registers are loaded with data from otp memory ? after fso/sa mode activation, control registers are loaded with data from otp memory ? spi register update (spi write/read operation) in sa/fso mode is disabled (spi write operation is blocked; clearing of spi registers is blocked; in case of invalid spi frame, spierr flag is set). ? rstb pin has reset functionality ? ledctrl pin is not functional (buck enable/disable only by means of buck_en spi/otp bit, digital pwm dimming not available). 111 b = 7 sa (stand-alone)/fso entered after por (rstb pin rising edge), registers are loaded with data from otp memory ? after sa/fso mode activation, control registers are loaded with data from otp memory ? spi register update (spi write/read operation) in sa/fso mode is enabled ? fso mode can be exited by writing fso_md[2:0] = 000 ? rstb pin has reset functionality ? ledctrl pin is not functional (buck enable/disable only by means of buck_en spi/otp bit, digital pwm dimming not available). spi interface general the serial peripheral interface (spi) is used to allow an external microcontroller (mcu) to communicate with the device. ncv78713 acts always as a slave and it cannot initiate any transmission. the operation of the device is configured and controlled by means of spi registers, which are observable for read and/or write from the master. the ncv78713 spi transfer size is 16 bits. during an spi transfer, the data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (sclk) synchronizes shifting and sampling of the information on the two serial data lines: sdo and sdi. the sdo signal is the output from the slave (ncv78713), and the sdi signal is the output from the master. a slave or chip select line (csb) allows individual selection of a slave spi device in a time multiplexed multiple-slave system. the csb line is active low. if an ncv78713 is not selected, sdo is in high impedance state and it does not interfere with spi bus activities. since the ncv78713 always clocks data out on the falling edge and samples data in on rising edge of clock, the mcu spi port must be configured to match this operation. the implemented spi allows connection to multiple slaves by means of star connection (csb per slave) or by means of daisy chain. an spi star connection requires a bus = (3 + n) total lines, where n is the number of slaves used, the spi frame length is 16 bits per communication. figure 19. spi star vs. daisy chain connection mcu (spi master) mosi miso sdo 1 sdi2 sdo 2 sdin sdon scb1 scb2 scbn ncv78713 dev#1 (spi slave) ncv78713 dev#2 (spi slave) ncv78713 dev#n (spi slave) ncv78713 dev#1 (spi slave) ncv78713 dev#2 (spi slave) ncv78713 dev#n (spi slave) mcu (spi master) spi daisy chain mode spi daisy chain connection bus width is always four lines independently on the number of slaves. however, the spi transfer frame length will be a multiple of the base frame length so n 16 bits per communication: the data will be interpreted and read in by the devices at the moment the csb rises. a diagram showing the data transfer between devices in daisy chain connection is given further: cmdx represents
ncv78713 www.onsemi.com 25 the 16-bit command frame on the data input line transmitted by the master, shifting via the chips? shift registers through the daisy chain. the chips interpret the command once the chip select line rises. figure 20. spi daisy chain data shift between slaves. the symbol ?x? represents the previous content of the spi shift register buffer 16 cycles cs sclk din 1 dout 1 din 2 dout 3 16 cycles 16 cycles cmd1 cmd2 cmd3 x cmd1 cmd2 x x cmd1 xxx dout 2 din 3 1 commands in the shift registers are executed on rising edge of cs the ncv78713 default power up communication mode is ?star?. in order to enable daisy chain mode, a multiple of 16 bits clock cycles must be sent to the devices, while the sdi line is left to zero. note: to come back to star mode the nop register (address 0x0000) must be written with all ones, with the proper data parity bit and parity framing bit: see spi protocol for details about parity and write operation. spi transfer format two types of spi commands (to sdi pin of ncv78713) from the micro controller can be distinguished: ?write to a control register? and ?read from register (control or status)?. the frame protocol for the write operation : figure 21. spi write frame c m d a 3 a 2 a 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sdi sdo sclk low p a 0 d 9 low high low p = not (cmd xor a3 xor a2 xor a1 xor a0 xor d9 xor d8 xor d7 xor d6 xor d5 xor d4 xor d 3 xor d2 xor d1 xor d0) write; cmd = ?1? d 8 high ?z d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 d 8 previous spi write command resp. ?spierr + 0x000hex? after por or spi command parity/framing error a 3 a 2 a 1 a 0 p 0 1 1 b u c k o c l e d t s d t w a 4 c m d a 3 a 2 a 1 a 0 previous spi read command & ncv78713 status bits resp. ?spierr + 0x000hex? after por or spi command parity/framing error p c m d s p i e r r s p i e r r 1 0 referring to the previous picture, the write frame coming from the master (into the sdi) is composed from the following fields: ? bit[15] (msb): cmd bit = 1 for write operation, ? bits[14:11]: 4 bits write address field, ? bit[10]: frame parity bit. it is odd parity formed by the negated xor of all other bits in the frame, ? bits[9:0]: 10 bit data to write device in the same time replies to the master (on the sdo): ? if the previous command was a write and no spi error had occurred, a copy of the command, address and data written fields, ? if the previous command was a read, the response frame summarizes the address used and an overall diagnostic check (copy of the main detected errors, see figures 21 and 22 for details), ? in case of previous spi error or after power-on-reset, only the msb bit will be 1, followed by zeros. if parity bit in the frame is wrong, device will not perform command and flag will be set. the frame protocol for the read operation : figure 22. spi read frame c m d a 3 a 2 a 1 d 1 d 0 d 8 d 7 d 6 d 5 d 4 d 3 d 2 sdi sdo sclk low a 4 a 0 d 9 low high low read; cmd = ?0? high? z low p p = not(cmd xor a4 xor a3 xor a2 xor a1 xor a0) t s d t w led = openled or shortled buckoc = ocled ?> immediate value of status bits; dedicated spi read command of the status register has to be performed to clear the value of read?by?clear status bits data from address a [4:0] shall be returned s p i e r r b u c k o c l e d 0 referring to the previous picture, the read frame coming from the master (into the sdi) is composed from the following fields: ? bit[15] (msb): cmd bit = 0 for read operation, ? bits[14:10]: 5 bits read address field, ? bit[10]: frame parity bit. it is odd parity formed by the negated xor of all other bits in the frame, ? bits [8:0]: 9 bits zeroes field. device in the same frame provides to the master (on the sdo) data from the required address (in frame response), thus achieving the lowest communication latency. spi framing and parity error spi communication framing error is detected by the ncv78713 in the following situations: ? not an integer multiple of 16 clk pulses are received during the active-low csb signal; ? lsb bits (8..0) of a read command are not all zero; ? spi parity errors, either on write or read operation. once an spi error occurs, the flag can be reset only by reading the status register in which it is contained (using in the read frame the right communication parity bit).
ncv78713 www.onsemi.com 26 spi address map table 9. ncv78713 spi address map addr r/w bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 na nop register (read/write operation ignored) 0x01 r/w 0x0 0x0 0x02 r/w buck_isens_thr[1:0] buck_vthr[7:0] 0x03 r/w 0x0 buck_toff[4:0] 0x04 r/w 0x0 buck_oc_occmp_ thr[1:0] fso_md[2:0] 0x0 buck_en 0x05 r/w 0x0 buck_ tsd_aut_ rcvr_en thermal_warning_thr[7:0] 0x06 r/w vtemp_off_ comp odd par.* led_sel_dur[8:0] 0x07 r/w vtemp_off_comp[2:0]* 0x0 0x08 r/w vtemp_off_comp[5:3]* buck_isens_trim[6:0] 0x09 r/w 0x0 adc_vled_rng_ sel[1:0] otp_bias_h otp_bias_l otp_addr[1:0] otp_operation[1:0] 0x0a r 0x0 odd parity 0x0 0x0b r 0x0 odd parity vledon[7:0] 0x0c r 0x0 odd parity 0x0 0x0d r 0x0 odd parity vled[7:0] 0x0e r 0x0 odd parity vtemp[7:0] 0x0f r 0x0 odd parity vboost[7:0] 0x10 r 0x0 odd parity vdd[7:0] 0x11 r 0x0 odd parity 0x0 0x12 r 0x0 odd parity buck_ton_dur[7:0] 0x13 r 0x0 odd parity 0x0 0x0 0x0 0x0 openled shortled ocled 0x14 r 0x0 odd parity otp_fail fso hwr 0x0 ledval spierr tsd tw 0x15 r 0x0 odd parity 0x0 otp_ active 0x0 buck_ min_ton 0x0 buck_ status 0x16 r 0x0 odd parity 0x0 0x0 0x17 r 0x0 odd parity 0x0 buck_isens_rng[6:0] 0x18 r 0x0 odd parity buck_isens_d1[3:0] 0x0 0x19 r 0x0 odd parity buck_isens_d2[3:0] 0x0 0x1a r 0x0 odd parity buck_isens_d3[3:0] 0x0 0x1b r 0x0 odd parity buck_isens_tc1[3:0] buck_isens_tc0[3:0] 0x1c r 0x0 odd parity buck_isens_tc3[3:0] buck_isens_tc2[3:0] 0x1d r 0x0 odd parity 0x0 0x1e r otp_data[9:0] 0x1f r 0x0 revid[7:0] other r 0x0 *read only
ncv78713 www.onsemi.com 27 table 10. bit definition symbol map position description register 0x00 (cr): nop register, reset value (por) = 0000000000 2 nop bits [9:0] ? addr_0x00 nop register (read/write operation ignored) register 0x01 (cr): nop register, reset value (por) = 0000000000 2 nop bits [9:0] ? addr_0x01 nop register (read/write operation ignored) register 0x02 (cr): buck peak current settings, reset value (por) = 0000000000 2 buck_isens_thr[1:0] bits [9:8] ? addr_0x02 peak current: selection of the range 1, 2, 3 or 4 buck_vthr[7:0] bits [7:0] ? addr_0x02 peak current comparator threshold value register 0x03 (cr): buck toff settings, reset value (por) = 0000000000 2 buck_toff[4:0] bits [4:0] ? addr_0x03 buck toff vled constant settings register 0x04 (cr): buck settings, reset value (por) = 0000000000 2 buck_oc_occmp_thr[1:0] bits [6:5] ? addr_0x04 overcurrent detection settings fso_md[2:0] bits [4:2] ? addr_0x04 fso mode selection buck_en bit 0 ? addr_0x04 buck regulator enable bit register 0x05 (cr): buck settings, reset value (por) = 0010110011 2 buck_tsd_aut_rcvr_en bit 8 ? addr_0x05 buck automatic recovery after tsd thermal_warning_thr[7:0] bits [7:0] ? addr_0x05 thermal warning threshold settings register 0x06 (cr): buck settings, reset value (por) = x000000000 2 vtemp_off_comp odd par. bit 9 ? addr_0x06 adc vtemp trimming parity bit led_sel_dur[8:0] bits [8:0] ? addr_0x06 vled measurement settings register 0x07 (cr): buck settings, reset value (por) = xxx0000000 2 vtemp_off_comp[2:0] bits [9:7] ? addr_0x07 adc vtemp trimming register 0x08 (cr): buck settings, reset value (por) = xxx0000000 2 vtemp_off_comp[5:3] bits [9:7] ? addr_0x08 adc vtemp trimming buck_isens_trim[6:0] bits [6:0] ? addr_0x08 compensation of the buck peak current register 0x09 (cr): buck settings, reset value (por) = 0000000000 2 adc_vled_rng_sel[1:0] bits [7:6] ? addr_0x09 range select for vled adc otp_bias_h bit 5 ? addr_0x09 otp bias high otp_bias_l bit 4 ? addr_0x09 otp bias low otp_addr[1:0] bits [3:2] ? addr_0x09 otp address otp_operation[1:0] bits [1:0] ? addr_0x09 otp operation register 0x0b (sr): vledon, reset value (por) = 0100000000 2 odd parity bit 8 ? addr_0x0b odd parity over data vledon[7:0] bits [7:0] ? addr_0x0b output of vled adc register 0x0d (sr): vled, reset value (por) = 0100000000 2 odd parity bit 8 ? addr_0x0d odd parity over data vled[7:0] bits [7:0] ? addr_0x0d output of vled adc register 0x0e (sr): vtemp, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x0e odd parity over data vtemp[7:0] bits [7:0] ? addr_0x0e output of vtemp adc register 0x0f (sr): vboost, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x0f odd parity over data vboost[7:0] bits [7:0] ? addr_0x0f output of vboost adc register 0x10 (sr): vdd, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x10 odd parity over data vdd[7:0] bits [7:0] ? addr_0x10 output of vdd adc
ncv78713 www.onsemi.com 28 table 10. bit definition (continued) symbol description map position register 0x12 (sr): buck_ton_dur, reset value (por) = 0100000000 2 odd parity bit 8 ? addr_0x12 odd parity over data buck_ton_dur[7:0] bits [7:0] ? addr_0x12 buck ton duration register 0x13 (sr): buck diagnostics, reset value (por) = 0x000000x0 2 odd parity bit 8 ? addr_0x13 odd parity over data openled bit 2 ? addr_0x13 buck open led flag, latched shortled bit 1 ? addr_0x13 buck short led flag, non-latched ocled bit 0 ? addr_0x13 buck overcurrent flag, latched register 0x14 (sr): buck diagnostics, reset value (por) = 0x0010xxxx 2 odd parity bit 8 ? addr_0x14 odd parity over data otp_fail bit 7 ? addr_0x14 otp failure flag, latched fso bit 6 ? addr_0x14 chip being in fso mode flag, non-latched hwr bit 5 ? addr_0x14 hardware reset flag, latched ledval bit 3 ? addr_0x14 actual status of ledctrl pin, non-latched spierr bit 2 ? addr_0x14 spi error flag, latched tsd bit 1 ? addr_0x14 thermal shutdown flag, latched tw bit 0 ? addr_0x14 thermal warning flag, latched register 0x15 (sr): buck diagnostics, reset value (por) = 0100000000 2 odd parity bit 8 ? addr_0x15 odd parity over data otp_active bit 4 ? addr_0x15 otp active flag, non-latched buck_min_ton bit 2 ? addr_0x15 minimal ton detected on buck, latched buck_status bit 0 ? addr_0x15 actual status of buck regulator, non-latched register 0x17: buck trimming, reset value (por) = 0x0xxxxxxx 2 odd parity bit 8 ? addr_0x17 odd parity over data buck_isens_rng[6:0] bits [6:0] ? addr_0x17 trimming constant for highest range on hot for buck peak current register 0x18: buck trimming, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x18 odd parity over data buck_isens_d1[3:0] bits [7:4] ? addr_0x18 delta trimming constant for buck peak current register 0x19: buck trimming, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x19 odd parity over data buck_isens_d2[3:0] bits [7:4] ? addr_0x19 delta trimming constant for buck peak current register 0x1a: buck trimming, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x1a odd parity over data buck_isens_d3[3:0] bits [7:4] ? addr_0x1a delta trimming constant for buck peak current register 0x1b: buck trimming, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x1b odd parity over data buck_isens_tc1[3:0] bits [7:4] ? addr_0x1b temperature coefficient trimming constant for buck peak current buck_isens_tc0[3:0] bits [3:0] ? addr_0x1b temperature coefficient trimming constant for buck peak current register 0x1c: buck trimming, reset value (por) = 0xxxxxxxxx 2 odd parity bit 8 ? addr_0x1c odd parity over data buck_isens_tc3[3:0] bits [7:4] ? addr_0x1c temperature coefficient trimming constant for buck peak current buck_isens_tc2[3:0] bits [3:0] ? addr_0x1c temperature coefficient trimming constant for buck peak current
ncv78713 www.onsemi.com 29 table 10. bit definition (continued) symbol description map position register 0x1e: otp data, reset value (por) = 0000000000 2 otp_data[9:0] bits [9:0] ? addr_0x1e otp data register 0x1f: revid, reset value (por) = 00000xxxxxxx 2 revid[7:0] bits [7:0] ? addr_0x1f revision id por values of status registers are shown in situation that fso mode is not entered after por. all latched flags are ?cleared by read?. ?x? means that value after reset is defined during reset phase (diagnostics) or is trimmed during manufacturing process. spi register spi_revid[7:0] is used to track the silicon version, following encoding mechanism is used: ? spi_revid[2:0]: metal tune <0 to 7> ? spi_revid[4:3]: full mask version <0 to 3> ? spi_revid[5]: l713/l723 distinguishing bit (revid[5] = 1 means l713) ? spi_revid[7:6]: constant 00 [binary] first full mask version has spi_revid[7:0] = 0x28hex (full mask = 0x1 & metal-tune = 0x0, revid[5] = 1). otp memory description the otp (once time programmable) memory contains 40 bits which bear the most important application dependant parameters and is user programmable via spi interface. the programming of these bits is typically done at the end of the module manufacturing line. otp memory serves to store configuration data for fail-safe or stand-alone functionality or default configuration of the chip after power-up. the otp bits can be programmed only once, this is ensured by dedicated otp lock bit which is set during programming. table 11. otp map otp bits connection to spi register otp[7:0] not applicable otp[9:8] not applicable otp[17:10] buck_vthr[7:0] otp[19:18] buck_isens_thr[1:0] otp[24:20] not applicable otp[29:25] buck_toff[4:0] otp[30] not applicable otp[31] buck_en otp[34:32] fso_md[2:0] otp[35] not applicable otp[36] buck_tsd_aut_rcr_en otp[38:37] buck_oc_occmp_thr[1:0] otp[39] otp lock bit the otp bits addressed by spi register otp_addr[1:0] are accessible (read only) in the spi register otp_data[9:0] after otp refresh operation (otp_operation[1:0] = 0x1) in the following way: otp_addr[1:0] = 0x0: otp_data[9:0] = otp[9:0] otp_addr[1:0] = 0x1: otp_data[9:0] = otp[19:10] otp_addr[1:0] = 0x2: otp_data[9:0] = otp[29:20] otp_addr[1:0] = 0x3: otp_data[9:0] = otp[39:30] otp operations the ncv78713 supports following operations with otp memory: ? otp_operation[1:0] = 0x0 or 0x3: nop (no operation) ? otp_operation[1:0] = 0x1: otp refresh ? refresh of the whole otp memory (40 bits). data addressed by spi register otp_addr[1:0] are available in spi register otp_data[9:0] after the end of otp refresh operation ? otp_operation[1:0] = 0x2: otp zap ? data from spi register (those listed in table 11) and otp lock bit are programmed into otp memory. otp zap operation is allowed to be performed only once ? when otp lock bit is unprogrammed spi status bit otp_active is set to ?log. 1? when an otp operation is in progress. otp programming procedure following procedure should be applied to program otp memory: ? vboost voltage has to be in range between 15 v and 20 v with current capability at least 50 ma ? vdd voltage has to be kept in range for normal mode operation ? the junction temperature has to stay in range from 0 c to 125 c during otp programming ? spi registers listed in table 11 have to be written with required content ? content of the spi registers (those listed in table 11) is programmed into the otp memory by otp_operation[1:0] = 0x2 spi write command. otp lock bit is programmed automatically at the same time to prevent any further otp programming
ncv78713 www.onsemi.com 30 otp programming verification otp_fail bit in the spi status register is set when vboost under-voltage (see otp_uv parameter) is detected during otp zap operation. it is clear by read flag. the otp_bias_h and otp_bias_l registers are used to check proper otp programming. after otp programming, the otp content has to be the same as programmed when otp is read with otp_bias_h = 1 and otp_bias_l = 1. following procedure should be applied to verify otp content: ? vdd voltage has to be kept in range for normal mode operation ? write spi registers otp_bias_l = 1 and otp_bias_h = 0 ? write spi register otp_operation[1:0] = 0x1 (otp refresh) for all otp_addr[1:0] values and check corresponding otp_data[9:0] content which has to match with previously programmed data ? write spi registers otp_bias_l = 0 and otp_bias_h = 1 ? write spi register otp_operation[1:0] = 0x1 (otp refresh) for all otp_addr[1:0] values and check corresponding otp_data[9:0] content which has to match with previously programmed data ? programming is considered as successful when no mismatch is observed table 12. ordering information device marking package* shipping ? NCV78713MW0R2G n78713?0 qfn24 5 5 with wettable flank (pb-free) 5,000 / tape & reel ncv78713mw0g n78713?0 qfn24 5 5 with wettable flank (pb-free) 60 units / tube *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and m ounting techniques reference manual, solderrm/d. ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv78713 www.onsemi.com 31 package dimensions qfn24 5x5, 0.65p case 485cs issue o seating k 0.15 c (a3) a a1 d2 b 1 13 24 2x 2x e2 24x 7 l 24x bottom view detail a top view side view d a b e 0.15 c pin one reference 0.10 c 0.08 c c e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min max millimeters a 0.80 0.90 a1 ??? 0.05 a3 0.20 ref b 0.25 0.35 d 5.00 bsc d2 3.40 3.60 e 5.00 bsc e2 e 0.65 bsc k l 0.30 0.50 3.40 3.60 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 3.66 0.40 3.66 24x 0.62 24x 5.30 5.30 l1 detail a l alternate terminal constructions a1 a3 l ??? 0.15 pitch dimensions: millimeters 0.20 min a m 0.10 b c m 0.05 c a m 0.10 b c a m 0.10 b c e/2 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv78713/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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