data sheet idt8T79S838-08NLGI revision a january 29, 2014 1 ?2014 integrated device technology, inc. 1-to-8 differential to universal output ? fanout buffer idt8t79s838-08i general description the idt8t79s838-08i is a high performance, 1-to-8, differential input to universal output fanout buffer. the device is designed for signal fanout of high-frequency clock signals in applications requiring output frequencies generated simultaneously. the idt8t79s838-08i is optimized for 3.3v and 2.5v supply voltages and a temperature range of -40c to 85c. the device is packaged in a space-saving 32 lead vfqfn package. features four banks of two output pairs individual output type control, lvds or lvpecl, via ? serial interface individual outputs remain enabled while serial loading new ? device configurations one differential pclk, npclk input pclk, npclk input pair can accept the following differential input levels: lvpecl, lvds levels maximum input frequency: 1.5ghz lvcmos control inputs individual output enable/disable control via serial interface 2.375v to 3.465v supply voltage operation -40c to 85c ambient operating temperature lead-free (rohs 6) packaging block diagram qa0 nqa0 qa1 nqa1 qb0 nqb0 qb1 nqb1 qc0 nqc0 qc1 nqc1 qd0 nqd0 qd1 nqd1 pclk npclk oe le miso sclk sdata vcc vee vee vee vee vee pwr_sel vee pullup / pulldown pulldownpulldown pulldown pulldown pulldown pulldown vee output type and output enable logic idt8t79s838-08i 32 lead vfqfn 5mm x 5mm x 0.925mm pad size 3.15mm x 3.15mm nl package top view 25 26 27 28 29 30 31 1 2 3 4 5 6 7 16 15 14 13 12 11 10 24 23 22 21 20 19 18 v cc v ee nqa1 qa1 nqa0 qa0 v cc sdata 32 8 9 17 v cc v ee qd0 nqd0 qd1 nqd1 v cc pwr_sel s c l k m i s o n c p c l k n p c l k o e v c c l e q b o n q b 0 q b 1 n q b 1 q c 0 n q c 0 q c 1 n q c 1 pin assignment
idt8T79S838-08NLGI revision a january 29, 2014 2 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer pin description and pin characteristic tables table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see ?table 2. pin characteristics? for typical values. table 2. pin characteristics number name type description 1 sclk input pulldown serial control port mode data input. lvcmos/lvttl interface levels. 2 miso output serial control port mode data output. lvcmos/lvttl interface levels. 3 nc unused no connect. 4 pclk input pulldown non-inverting differential clock input. 5n p c l k i n p u t pullup / pulldown inverting differential clock input. v cc / 2 by default when left floating. 6 oe input pulldown default output disable. lvcmos/lvttl interface levels. ? see ?table 3b. oe truth table? . 7, 10, 16, 25, 31 v cc power power supply voltage pin. 8 le input pulldown serial control port mode enable. latc hes data when the pin gets a high level. outputs remain enabled when le is lo w. lvcmos/lvttl interface levels. 9 pwr_sel input pulldown power supply selection. see ?table 3a. pwr_sel truth table? . 11, 12 nqd1, qd1 output differen tial bank d output pair. 13, 14 nqd0, qd0 output differen tial bank d output pair. 15, 26 v ee power negative power supply pins. 17, 18 nqc1, qc1 output diff erential bank c output pair. l vpecl or lvds interface levels. 19, 20 nqc0, qc0 output diff erential bank c output pair. l vpecl or lvds interface levels. 21, 22 nqb1, qb1 output differenti al bank b output pair. lvpecl or lvds interface levels. 23, 24 nqb0, qb0 output differenti al bank b output pair. lvpecl or lvds interface levels. 27, 28 nqa1, qa1 output differenti al bank a output pair. lvpecl or lvds interface levels. 29, 30 nqa0, qa0 output differenti al bank a output pair. lvpecl or lvds interface levels. 32 sdata input pulldown serial control port mode data input. lvcmos/lvt tl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? r out output impedance miso v cc = 3.3v 125 ? v cc = 2.5v 125 ?
idt8T79S838-08NLGI revision a january 29, 2014 3 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer function tables table 3a. pwr_sel truth table table 3b. oe truth table output type control and start-up status two output types are available: lvds and lvpecl. the part features four modes of output type control: ? eight lvds outputs ? eight lvpecl outputs ? two lvds (qax) + six lvpecl (qbx, qcx, qdx) ? two lvpecl (qax) + six lvds (qbx, qcx, qdx) at startup, the outputs are in st atic low/high lvds mode until the part has been configured. disabled outputs are in static low/high mode. a global hardware output enable (oe pin #6) enables or disables all outputs at once. the global hardware oe has priority over a serial interface configuration. table 3c. output type control pwr_sel function l (connect to v ee ) 2.5v power supply h (connect to v cc ) 3.3v power supply oe function l (default) all outputs disabled (low/high static mode), rega rdless of individual oe registers set by serial interface. h outputs enabled according to individual oe registers set by serial interface (see ?table 3e. configuration table? ). control bits output configuration d2 d1 low low 8 lvds outputs high high 8 lvpecl outputs high low 2 lvds (qax) + 6 lvpecl (qbx, qcx, qdx) outputs low high 2 lvpecl (qax) + 6 lvds (qbx, qcx, qdx) outputs
idt8T79S838-08NLGI revision a january 29, 2014 4 ?2014 integrated device technology, inc. idt8t79s838-08i data sheet 1-to-8 differential to universal output fanout buffer serial interface configuration of the idt8t79s838i-08 is achieved by writing 10 configuration bits over serial interface. all 10 bits have to be written in sequence. after writing the 10 configuration bits, the le pin must remain at high level for outputs to toggle. ' ' ' ' ' 0 , 6 2 ' ' ' ' ' 6 & |