View S34MS16G2_9007200.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S34MS16G2 16 gb, 4-bit ecc, 8 i/o, and 1.8 v v cc nand flash for embedded cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00464 rev. *f revised march 16, 2018 distinctive characteristics ? density C 16 gb (4 gb ? 4) ? architecture (for each 4 gb device) C input / output bus width: 8-bits C page size: (2048 + 128) b ytes; 128-byte spare area C block size: 64 pages or (128k + 8k) bytes C plane size C 2048 blocks per plane o r (256m + 16m) bytes Cdevice size C 2 planes per device or 512 mbyte ? nand flash interface C open nand flash interface (onfi) 1.0 compliant C address, data and commands multiplexed ? supply voltage C 1.8v device: v cc = 1.7v ~ 1.95v ? security C one time programmable (otp) area C serial number (unique id) C hardware program/erase disa bled during power transition ? additional features C supports multiplane pro gram and erase commands C supports copy back program C supports multiplane copy back program C supports read cache ? electronic signature C manufacturer id: 01h ? operating te mperature C industrial: ? 40c to 85c performance ? page read / program C random access: 30 s (max) C sequential access: 45 ns (min) C program time / multiplane p rogram time: 300 s (typ) ? block erase / multiplane erase C block erase time: 3.5 ms (typ) ? reliability C 100,000 program / erase cycles (typ) (with 4-bit ecc per 528 bytes) C 10 year data retention (typ) C blocks zero and one are valid and will be valid for at least 1000 program-erase cycles with ecc ? package options C lead free and low halogen C 63-ball bga 9 ? 11 ? 1.2 mm
document number: 002-00464 rev. *f page 2 of 17 S34MS16G2 contents distinctive characteristics .................................................. 1 performance ............................................................... ........... 1 1. general description ..................................................... 3 2. connection diagram .................................................... 3 3. pin description ............................................................. 4 4. block diagrams ............................................................ 5 5. addressing ............................................................... .... 7 6. read status enhanced ................................................ 7 7. read id ............................................................... ........... 7 7.1 read parameter page ......................................... .......... 9 8. electrical characteristics .......................................... 12 8.1 valid blocks ................................................ ................. 12 8.2 dc characteristics .......................................... ............. 12 8.3 pin capacitance............................................. ............... 13 8.4 power consumptions and pi n capacitance for allowed stacking configurations ........................................ ........ 13 9. physical interface ....................................................... 14 9.1 63-ball bga package ......................................... .......... 14 10. ordering information .................................................. 15 11. revision history .......................................................... 16 document history page ......................................... .............16 sales, solutions, and legal information ....................... ....17 worldwide sales and design s upport ......... .............. 17 products ...................................................... .............. 17 psoc? solutions ............................................... ....... 17 cypress developer community . ................................ 17 technical support ........... .................................. ........ 17
document number: 002-00464 rev. *f page 3 of 17 S34MS16G2 1. general description the cypress ? S34MS16G2 16-gb nand is offered in 1.8v v cc with x8 i/o interface. this docu ment contains information for the S34MS16G2 device, which is a quad- die stack of four s34ms04g2 d ie. for detailed specifications, please refer to the discrete d ie data sheet: s34ms01g2_04g2 . 2. connection diagram figure 2.1 63-bga contact, x8 device (balls down, top view) f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc (1) nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss (1) nc nc nc nc h3 h4 h5 h6 h7 h8 v cc nc nc nc i/o0 nc b9 a9 nc nc a2 nc nc nc nc nc vcc (1) nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc nc i/o1 nc k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc
document number: 002-00464 rev. *f page 4 of 17 S34MS16G2 3. pin description notes: 1. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current su rges from the power supply. the pcb track widths must be sufficient to carry the curr ents required during program and erase operations. 2. an internal voltage detector disables all functions whenever v cc is below 1.8v to protect the device from any involuntary program/erase during power transitions. table 3.1 pin description pin name description i/o0 - i/o7 inputs/outputs . the i/o pins are used for comma nd input, address input, data input, and data out put. the i/o pins float to high-z when the devic e is deselected or the outpu ts are disabled. cle command latch enable. this input activates the latchi ng of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable. this input activates the latching of the i/o inputs inside the address register on the rising edge of write enable (we#). ce# chip enable. this input controls the selectio n of the device. when the devic e is not busy ce# low selects the memory. we# write enable. this input latches command, address and data. the i/o inputs ar e latched on the rising edge of we#. re# read enable. the re# input is the se rial data-out control, and when active d rives the data onto the i/o bus. data is valid t rea after the falling edge of re# wh ich also increments the intern al column address counter by one. wp# write protect. the wp# pin, when low, provides hardware protec tion against und esired data modification (program / erase). r/b# ready busy . the ready/busy output is an open drain pin that signals the s tate of the memory. v cc supply voltage . the v cc supplies the power for all the operations (read, program, eras e). an internal lock circuit prevents the insertion of commands when v cc is less than v lko . v ss ground. nc not connected.
document number: 002-00464 rev. *f page 5 of 17 S34MS16G2 4. block diagrams figure 4.1 functional block diagram address register/ counter controller command interface logic command register data register re# i/o buffer y decoder page buffer x d e c o d e r nand flash memory array wp# ce# we# cle ale i/o0~i/o7 program erase hv generation 16 gb device (4 gb x 4)
document number: 002-00464 rev. *f page 6 of 17 S34MS16G2 figure 4.2 block diagram 16 gb (4 gb x 4) 63-ball bga with 1 ce# (one ch ip enable signal) io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 ce# we# rb# re# vss ale vcc cle wp# io0~io7 io0~io7 ce# ce# we# we# rb# rb# re# re# vss vss ale ale vcc vcc cle cle wp# wp# 4 gb x8 nand flash memory#3 4 gb x8 nand flash memory#4 4 gb x8 nand flash memory#1 4 gb x8 nand flash memory#2
document number: 002-00464 rev. *f page 7 of 17 S34MS16G2 5. addressing notes: 1. cax = column address bit. 2. pax = page address bit. 3. pla0 = plane address bit zero. 4. bax = block address bit. 5. block address concatenated with page address and plane address = actual page address, also known as the row address. 6. a31 for 16 gb (4 gb x 4 ? qdp). for the address bits, th e following rules apply: ? a0Ca11: column address in the page ? a12Ca17: page address in the block ? a18: plane address (for multipl ane operations) / block address (for normal operations) ? a19Ca31: block address 6. read status enhanced read status enhanced is used to retrieve the status value for a previous operation in the following cases: ? in the case of concurrent oper ations on a multi-die stack. when four dies are stacked to f orm a quad-die package (qdp), it is possible to run one operati on on the first die, then activa te a different operation on the seco nd die, for example: erase while read, read while program, etc. ? in the case of multiplane o perations in the same die. 7. read id the device contains a product id entification mode , initiated by writing 90h to the command reg ister, followed by an address in put of 00h. note : if you want to execute read st atus command (0x70) after read id sequence, you should input dummy command (0x00) before read status command (0x70). for the S34MS16G2 device, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and 5th cycle id, respectively. t he command register remains in read id mode until further commands are issued to it. table 5.1 address cycle map bus cycle i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1st / col. add. 1 a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca 5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 a8 (ca8) a9 (ca 9) a10 (ca10) a11 (ca11) low low low l ow 3rd / row add. 1 a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a1 7 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 a20 (ba1) a21 ( ba2) a22 (ba3) a23 (ba4) a24 (ba5) a2 5 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 (6) a28 (ba9) a29 (ba10) a30 (ba11) a31 (ba12) low low low low table 7.1 read id for suppor ted configurations density org v cc 1st 2nd 3rd 4th 5th 4 gb x8 1.8v 01h ach 90h 15h 56h 16 gb (4 gb x 4 C qdp with one ce#) x8 1.8v 01h a5h d2h 15h 5eh
document number: 002-00464 rev. *f page 8 of 17 S34MS16G2 figure 7.1 read id operation timing 5 th id data table 7.2 read id byte 5 description description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 ecc level 1 bit / 512 bytes 2 bit / 512 bytes 4 bit / 512 bytes 8 bit / 512 bytes 0 0 0 1 1 0 1 1 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (without spare area) 64 mb 128 mb 256 mb 512 mb 1 gb 2 gb 4 gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 reserved 0 ce# we# cle re# ale twhr tar trea read id command address 1 cycle maker code device code 3rd cycle 4th cycle 5th cycle i/ox 01h 90h 00h 15h 5eh d2h a5h
document number: 002-00464 rev. *f page 9 of 17 S34MS16G2 7.1 read parameter page the device supports the onfi rea d parameter page operation, ini tiated by writing ech to the com mand register, followed by an address input of 00h. the comma nd register remains in parameter page mode until further co mmands are issued to it. table 7.3 explains the parameter fields. note: for 32nm cypress nand, for a particular condition, the read pa rameter page command does not give the correct values. to overcome this issue, the host mus t issue a reset command before the read parameter page comma nd. issuance of reset before the read parameter p age command will provide the correct values and will not out put 00h values. table 7.3 parameter page description byte o/m description values revision information and features block 0-3 m parameter page signature byte 0: 4fh, o byte 1: 4eh, n byte 2: 46h, f byte 3: 49h, i 4fh, 4eh, 46h, 49h 4-5 m revision number 2-15 reserved (0) 1 1 = supports onfi version 1.0 0 reserved (0) 02h, 00h 6-7 m features supported 5-15 reserved (0) 4 1 = supports odd t o even page copyback 3 1 = supports inter leaved operations 2 1 = supports non-seque ntial page programming 1 1 = supports multiple lun operations 0 1 = supports 16-bit data bus width 1eh, 00h 8-9 m optional commands supported 6-15 reserved (0) 5 1 = supports read unique id 4 1 = supports copyback 3 1 = supports rea d status enhanced 2 1 = supports get features and set features 1 1 = supports read cache commands 0 1 = supports page c ache program command 3bh, 00h 10-31 reserved (0) 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) 53h, 50h, 41h, 4e h, 53h, 49h, 4fh, 4eh, 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) 53h, 33h, 34h, 4dh, 53h, 31h, 36h, 47h, 32h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 m jedec manufacturer id 01h 65-66 o date code 00h 67-79 reserved (0) 00h memory organization block 80-83 m number of data bytes per page 00h, 08h, 00h, 00h 84-85 m number of spare bytes per page 80h, 00h 86-89 m number of data bytes p er partial page 00h, 00h, 00h, 00 h 90-91 m number of spare bytes per partial page 00h, 00h
document number: 002-00464 rev. *f page 10 of 17 S34MS16G2 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per l ogical unit lun 00h, 40h, 00h, 00h 1 ce 100 m number of logical units luns 01h 1 ce 101 m number of address cycles 4-7 column address cycles 0-3 row address cycles 23h 102 m number of bits per cell 01h 103-104 m bad blocks maximum per lun 47h, 01h 1 ce 105-106 m block endurance 01h, 05h 107 m guaranteed valid blocks at beginning of target 01h 108-109 m block endurance for guaranteed valid blocks 01h, 03h 110 m number of programs per page 04h 111 m partial programming attributes 5-7 reserved 4 1 partial page la yout is partial page data followed by partial page spare 1-3 reserved 0 1 partial page prog ramming has constraints 00h 112 m number of bits ecc correctability 04h 113 m number of interleaved address bits 4-7 reserved 0 0-3 number of interleaved address bits 01h 114 o interleaved operation attributes 4-7 reserved 0 3 address restrictions for program cache 2 1 program cache supported 1 1 no block address restrictions 0 overlapped / concurrent interleaving support 04h 115-127 reserved 0 00h electrical parameters block 128 m i/o pin capacitance 0ah 129-130 m timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 03h, 00h 131-132 o program cache timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 03h, 00h 133-134 m t prog maximum page program time (s) bch, 02h table 7.3 parameter page descr iption (continued) byte o/m description values
document number: 002-00464 rev. *f page 11 of 17 S34MS16G2 note: 1. ?o? stands for optional, ?m? for mandatory. 135-136 m t bers maximum block erase time (s) 10h, 27h 137-138 m t r maximum page read time (s) 1eh, 00h 139-140 m t ccs minimum change column s etup time (ns) c8h, 00h 141-163 reserved (0) 00h vendor block 164-165 m vendor specif ic revision number 00h 166-253 vendor specific 00h 254-255 m integrity crc 11h, f5h (1ce#) redundant parameter pages 256-511 m value of bytes 0-255 repeat value of bytes 0-255 512-767 m value of bytes 0-255 repeat value of bytes 0-255 768+ o additional redundan t parameter pages ffh table 7.3 parameter page descr iption (continued) byte o/m description values
document number: 002-00464 rev. *f page 12 of 17 S34MS16G2 8. electrical c haracteristics 8.1 valid blocks note: 1. each 4 gb can have a maximum 80 bad blocks. 8.2 dc characteristics notes: 1. all v cc pins, and v ss pins respectively, are shorted together. 2. values listed in this table refer to the complete voltage range for v cc and to a single device in case of device stacking. 3. all current measurements are performed with a 0.1 f capacitor connected between the v cc supply voltage pin and the v ss ground pin. 4. standby current measurement can be performed after the dev ice has completed the initialization process at power up. table 8.1 valid blocks device symbol min typ max unit s34ms04g2 n vb 4016 4096 blocks S34MS16G2 n vb 16057 (1) 16384 blocks table 8.2 dc characteristics and o perating conditions (values listed are fo r each 4 gb nand, 16 gb (4 gb x 4) will di ffer accordingly) parameter symbol test conditions min typ max units power on current i cc0 ffh command input after power on 50 per device ma operating current sequential read i cc1 t rc = t rc (min) ce# = v il , iout = 0 ma 1530ma program i cc2 normal 15 30 ma cache 15 30 ma erase i cc3 15 30 ma standby current, (ttl) i cc4 ce# = v ih , wp# = 0v/vcc 1ma standby current, (cmos) i cc5 ce# = v cc -0.2, wp# = 0/v cc 1050a input leakage current i li v in = 0 to v cc (max) 10 a output leakage current i lo v out = 0 to v cc (max) 10 a input high voltage v ih v cc x 0.8 v cc + 0.3 v input low voltage v il -0.3v cc x 0.2 v output high voltage v oh i oh = -100 a v cc -0.1 v output low voltage v ol i ol = 100 a 0.1 v output low current (r/b#) i ol(r/b#) v ol = 0.1v 3 4 ma erase and program lockout voltage v lko 1.1v
document number: 002-00464 rev. *f page 13 of 17 S34MS16G2 8.3 pin capacitance note: 1. for the stacked devices version the input is 10 pf x [number of stacked chips] and the input/output is 10 pf x [number of sta cked chips]. 8.4 power consumptions and pin capacitance for allowed stacking configurations when multiple dies are stacked in the same package, the power c onsumption of the sta ck will increase according to the number o f chips. as an example, the standby current is the sum of the sta ndby currents of all the chips, w hile the active power consumpt ion depends on the number of chips c oncurrently executing different operations. when multiple dies are stacked in the same package the pin/ball capacitance for the single inpu t and the single input/output o f the combo package must be calculated based on the number of chips s haring that input or that pin/ball. table 8.3 pin capacitance (ta = 25c, f=1.0 mhz) parameter symbol test condition min max unit input c in v in = 0v 10 pf input / output c io v il = 0v 10 pf
document number: 002-00464 rev. *f page 14 of 17 S34MS16G2 9. physical interface 9.1 63-ball bga package figure 9.1 63-ball bga 9 x 11 x 1.2 mm package jedec d x e symbol a a1 d e d1 e1 md me n o b ee ed min. --- 0.25 0.40 a3-a8,b2-b8,c1,c2,c9,c10,d1, d2,d9,d10,e1,e2,e9,e10,f1,f2, f9,f10,g1,g2,g9,g10,h1,h2,h9, h10,j1,j2,j9,j10,k1,k2,k9,k10, l3-l8,m3-m8 tna 063 mo-207(n) 11.00mm x 9.00mm package nom. --- --- 11.00 bsc 9.00 bsc 8.80 bsc 7.20 bsc 12 10 63 0.45 0.80 bsc 0.80 bsc max. 1.20 --- 0.50 note profile ball height body size body size matrix footprint matrix footprint matrix size d direction matrix size e direction ball count ball diameter ball pitch ball pitch solder ball placement solder ball placement sd 0.40 bsc gs5038-tna063-09.05.14 notes: dimensioning and tolerancing methods per asme y14.5m-1994. all dimensions are in millimeters. ball p osition designation per jep 95, section 3, spp-020. e represents the solder ball grid pitch. symbol md is the ball matrix size in the d direction. symbol me is the ball matrix size in the e direction. n is the number of populated solder ball positions for matrix size md x me. dimension b is measured at the maximum ball diameter in a plane parallel to datum c. sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0. when there is an even number of solder balls in the outer row sd = ed/2 and se = ee/2. a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. + indicates the theoretical center of depopulated balls. 1. 2. 3. 4. 5. 6. 7. 8. 9. se 0.40 bsc depopulated solder balls
document number: 002-00464 rev. *f page 15 of 17 S34MS16G2 10. ordering information the ordering part number is form ed by a valid combination of th e following: valid combinations valid combinations list configur ations planned to be supported in volume for th is device. consult your l ocal sales office to c onfirm availability of specific valid c ombinations and to check on new ly released combinations. s34ms 16g 2 02 b h i 00 0 packing type 0 = tray 3 = 13 tape and reel model number 00 = standard interface / onfi (x8) 20 = two chip enable with standard onfi (x8) temperature range i = industrial (C40c to + 85c) materials set f = lead (pb)-free h = lead (pb)-free and low halogen package b = bga t = tsop bus width 00 = x8 nand, single die 04 = x16 nand, single die 01 = x8 nand, dual die 02 = x8 nand, quad die 05 = x16 nand, dual die technology 2 = cypress nand revision 2 (32 nm) density 01g = 1 gb 02g = 2 gb 04g = 4 gb 08g = 8 gb 16g = 16 gb device family s34ms cypress slc nand flash memory for embedded valid combinations device family density technology bus width package type temperature range additional ordering options packing type package description s34ms 16g 2 02 bh i bh C 00 0, 3 bga
document number: 002-00464 rev. *f page 16 of 17 S34MS16G2 11. revision history document history page document title: S34MS16G2, 16 gb , 4-bit ecc, x8 i/o, and 1.8 v v cc nand flash for embedded document number: 002-00464 rev. ecn no. orig. of change submission date description of change ** C xila 12/12/2014 initial release *a C xila 04/24/2015 performance: corrected package options for 63- ball bga to 9 x 11 x 1.2 mm physical interface: corrected fi gure title to 63-ball bga 9 x 11 x 1.2 mm ordering information: ordering in formation table: corrected mod el number and materials set *b 4962771 xila 10/14/2015 updated to cypress template. *c 5244672 xila 04/28/2016 changed status from advance to final. updated read id : updated read parameter page : updated description. updated to new template. *d 5497766 xila 10/27/2016 updated electrical characteristics : updated dc characteristics : updated table 8.2 . updated notes 1 and 2 . updated to new template. *e 5962114 aesatmp8 11/09/2017 updated logo and copyright. *f 6100827 mnad 03/16/2018 updated to new template. completing sunset review.
document number: 002-00464 rev. *f revised march 16, 2018 page 1 7 of 17 ? cypress semiconductor corporation, 2014-2018. this document i s the property of cypress semicond uctor corporation and its sub sidiaries, including spansion llc (cypress). this document, including any software or firmware included or referenced in th is document (software), is owned by cypress under the intelle ctual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and trea ties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademark s, or other intellectual property rights. if the software is not accompanie d by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, the n cypress hereby grants you a personal, non-exclusive, nontransferable li cense (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source cod e form, to modify and reproduce the software solely for use with cypress h ardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributo rs), solely for use on cypress hardware product units, and (2) under those claims of cypress's patents that are infringed by t he software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware produc ts. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no war ranty of any kind, express or implied, with regard to this docu ment or any software or accompanying hardware, includi ng, but not limited to, the im plied warranties of merchantability and fitness for a particula r purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purpose s. it is the responsibility of the user of this document to properly des ign, program, and test the functionality and safety of any appl ication made of this information and any resulting product. cyp ress products are not designed, intended, or authorized for use as critical c omponents in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support d evices or systems, other medical devices or systems (including resuscitat ion equipment and surgical implants), pollution control or haza rdous substances management, or other uses where the failure of the device or system could cause personal injury, death, or propert y damage (unintended uses). a critical component is any compo nent of a device or system whose failure to perform can be reas onably expected to cause the failure of the device or system, or to af fect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unint ended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims fo r personal injury or death, ari sing from or related to any unint ended uses of cypress products . cypress, the cypress logo, spansion, the spansion logo, and com binations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tr aveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and bran ds may be claimed as property of their respective owners. S34MS16G2 sales, solutions, an d legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturers representati ves, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 mcu cypress developer community community | projects | video | blogs | training | components technical support cypress.com/support

▲Up To Search▲

Price & Availability of S34MS16G2

	To Download S34MS16G2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .