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copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. high-performance, high-current drmos power module APW8703/6/7 features general description 4.5v ~ 5.5v input range for vcc & pvcc 4.5v ~ 25v input range for vin power-on-reset monitoring on vcc pin APW8703-up to 10a (peak), 8a (continuous) output current scale apw8706-up to 8a (peak), 6a (continuous) output current scale apw8707-up to 25a (peak), 13a (continuous) output current scale adjustable over-current protection threshold up to 1.5mhz pwm operation built-in tri-state pwm input function built in en timing control function build in n-ch mosfet for high side, n-ch mosfet for low side skip mode operation over-temperature protection tqfn 4x4-23p package and tqfn 5x5-30 packages lead free and green devices available (rohs compliant) desktops graphics cards severs portable/notebook regulators the APW8703/6/7 integrates a high-side n-channel mosfet and a low-side n-channel mosfet with adap- tive dead-time control. the APW8703/6/7 have a built-in tri-state pwm input function which can support a number of pwm controllers. when the pwm input signal stays tri- state, the tri-state function shuts off the high-side mosfet and turns on the low-side mosfet without consider zc function. the device is also equipped with power-on- reset(por) and enable control functions into a single package and accurate current limit. the device over-cur- rent protection monitors the output current by using the voltage drop across the r ds(on) of low-side mosfet, elimi- nating the need for a current sensing resistor that fea- tures high efficiency and low cost. the por circuit with hysteresis monitors vcc supply voltage to start up/shut- down the ic at power-on/off. the APW8703/6/7 also can be enabled or disabled by other power system. pulling the en pin high or low will turn on or shut off the device. simplified application circuit applications c in vin agnd pwm APW8703 vcc pgnd lx en v cc v out v in c vcc 1uf c out l pwm controller vcc pvcc apw8706 apw8707
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 2 APW8703/6/7 ordering and marking information pin configuration note:anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j-std-020d for msl classification at lead-free peak reflow temperature. anpec defines green to mean lead-free (rohs compliant) and halogen free (br or cl does not exceed 900ppm by weight in homogeneous material and total of br and cl does not exceed 1500ppm by weight). APW8703/6 = exposed and thermal pad tqfn 4x4-23 (top view) lx agnd5 pwm6 ocset1 ocb2 en3 smod4 n c 7 8 9 1 0 l x 1 1 17lx 16lx 15 14pgnd 13pgnd 12 pgnd 2 3 2 2 v c c 2 1 2 0 1 9 b s t 1 8 l x vin v i n p v c c l x v i n v i n p g n d pgnd 24 25 APW8703 apw8706 apw8707 handling code temperature range package code assembly material APW8703qb: package code qb : tqfn 4x4-23 operating ambient temperature range handling code tr : tape & reel assembly material g : halogen and lead free device apw8706qb: apw8707qb: x - date code apw8707 xxxxx x - date code x - date code i : -40 to 85 o c qb : tqfn 5x5-30 APW8703 xxxxx apw8706 xxxxx tqfn5x5-30 (top view) agnd vin lx ocset1 ocb2 en 3 agnd4 smod5 pwm6 nc7 v i n 8 v i n 9 v i n 10 v i n 11 p g n d 12 p g n d 13 p g n d 14 lx 22 lx 21 lx 20 pgnd 19 pgnd 18 pgnd 17 pgnd 16 pgnd 15 v c c 30 a g n d 29 n c 28 b o o t 27 l x 25 l x 24 l x 23 p g n d 26 = exposed and thermal pad apw8707 31 32 33
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 3 APW8703/6/7 absolute maximum ratings (note 1) symbol parameter rating unit v cc & v pvcc vcc & pvcc to gnd voltage -0.3 ~ 7 v v in vin to pgnd voltage -0.3 ~ 30 v v lx lx to pgnd voltage >20ns pulse width <20ns pulse width -0.3 ~ 30 -5 ~ 38 v v bst bst to gnd voltage -0.3 ~ 37 v v bst -v lx bst to lx voltage -0.3 ~ 7 v other pins en,smod, ocset and pwm to agnd voltage -0.3 ~ v cc +0.3 v agnd to pgnd voltage -0.3 ~0.3 v t j junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr maximum lead soldering temperature(10 seconds) 300 o c note1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recom- mended operating conditions is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics symbol parameter typical value unit tqfn4x4-23 50 q ja junction-to-ambient resistance in free air (note 2) tqfn5x5-30 25 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. symbol parameter range unit v cc &p vcc vcc and pvcc to agnd voltage 4.5 ~ 5.5 v v in vin to pgnd voltage 4.5 ~ 25 v APW8703 8 a apw8706 6 a maximum continuous output current apw8707 13 a APW8703 10 a apw8706 8 a i out maximum peak output current apw8707 25 a f pwm pwm operation frequency 0.1 ~ 1.5 mhz t a ambient temperature -40 ~ 85 o c t j junction temperature -40 ~ 125 o c recommended operating conditions (note 3) note 3: refer to the typical application circuit.
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 4 APW8703/6/7 electrical characteristics APW8703/6/7 parameter test conditions min typ max unit supply current en = high, pwm = high, smod=l - 90 120 ua en = high, pwm = low, smod=l - 60 90 ua i vcc vcc supply current en = low - - 1.0 ua power-on-reset(por) vcc rising por thresold 3.7 4.0 4.3 v vcc por hysteresis 50 100 150 mv power stage APW8703 - 25 - apw8706 - 30 - r on_h high-side switch on resistance apw8707 - 9.7 - m APW8703 - 7 - apw8706 - 12 - r on_l low-side switch on resistance apw8707 - 5.2 - m i lx lx leakage current v in = v cc = lx = 25v, en = gnd -1 - 1 ua vin pin leakage current en = low, v in =25v - - 1 ua boot pin current v boot-pgnd =30v, v lx =25v - - 1 ua zero current detect v zc zero current detect v lx - pgnd -5 - 5 mv over-current protection(ocp) i ocset ocset current source 9 10 11 a v ocp ocp threshold - 190 - mv ocb output low voltage sink current=5ma - 0.5 0.7 v ocb leakage current v ocb =5v - - 1 ua t d(ocb) ocb deglitch time ocb go low - 0.6 - ms over-temperature protection (otp) t otr otp rising threshold - 145 - o c otp hysteresis - 45 - o c pwm input pin v pwm rising 3.6 3.9 4.1 v v pwm pwm input logic threshold v pwm falling 1 1.2 1.4 v v pwm rising 1.0 1.3 1.6 v v tri tri-state input rising logic threshold hysteresis 140 280 420 mv v pwm falling 3.4 3.7 4.0 v v tri tri-state input falling logic threshold hysteresis 85 170 255 mv i pwm pwm pin input current source/ sink , v pwm = 0v to 5v -1 - 1 ua unless otherwise specified, these specifications apply over v cc = v pvcc = v en = 5v, v in =12v and t a = 25 o c.
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 5 APW8703/6/7 electrical characteristics APW8703/6/7 parameter test conditions min typ max unit en input and smod input en/smod input logic high 2.0 - - v en/smod input logic low - - 0.8 v en/smod input current v en = 5v or v smod =5v -1 - 1 ua gate driver timings(refer to figure 1 and table 1) t pdlu pwm to high side gate pwm h to l to gh h to l (note4) - 18 - ns t pdll pwm to low side gate pwm l to h to gl h to l (note4) - 25 - ns t pdhu ls to hs gate deadtime gl h to l to gh l to h (note4) - 20 - ns t pdhl hs to ls gate deadtime gh h to l to gl l to h (note4) - 20 - ns unless otherwise specified, these specifications apply over vdd=5v. typical values are at t a =25 o c. note4: not tested in production.
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 6 APW8703/6/7 pwm operation characteristics figure 1 : timing chart table 1 : truth table en smod pwm gh gl l x x l l h l h h l h l l l skip mode h x tri-state l h h h h h l h h l l h pwm gl t pdll t pdlu t pdll t gh t pdhl tri-state band pdlu t pdhu pdhl t t pdhu
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 7 APW8703/6/7 pin descriptions pin number APW8703/6 apw8707 name function 1 1 ocset ov er-current setting input. connect a resistor to gnd to set the ocp trip level. 2 2 ocb fault indication pin. this pin goes low when a ocp condition is detected after a 1ms deglitch time. 3 3 en enable pin. logic high enables the device. logic low disables the device. the pin is not floating. 4 5 smod skip mode input. pull smod high to enter diode emulation or skip mode. 5 4,29,31 agnd signal ground for the ic. all voltage levels are measured with respect to this pin. tie this pin to the ground island/plane through the lowest impedance connection available. 6 6 pwm pwm drive logic input. 7 7,28 nc no connection. 8,9,22,24 8,9,10,11,32 vin supply voltage input pin for power stage. 10,11,16,17, 18,25 20,21,22,23, 24,25,33 lx junction point of the high-side and low-side mosfet. connect the output lc filter for pwm output voltage. 12,13,14,15, 19 12,13,14,15, 16,17,18,19, 26 pgnd power ground. 20 27 bst high-side gate driver power input pin. connect a 0.1uf capacitor from bst to lx. 21 - pvcc supply voltage input pin for low side gate driver. 23 30 vcc supply voltage input pin for control circuitry. decoupling at least 1uf of a mlcc capacitor from the vcc pin to the agnd pin.
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 8 APW8703/6/7 block diagram power-on reset tri -state input circuit controller shoot through control pvcc vin lx pgnd vcc vcc en pwm agnd zero crossing detect lx gh gl gh gl bst smod ocb ocset 10ua + - + 115mv lx ocp pvcc + (for APW8703/06)
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 9 APW8703/6/7 typical application circuit note 5: vcc voltage rail must be sync with pwm controller vcc voltage level. note 6: pvcc pin is only for APW8703/06 c in vin agnd pwm APW8703 (note6) vcc pgnd lx en v cc(note5) v out v in c vcc 1uf c out l pwm controller vcc smod bst ocb 0.1uf pvcc r ocb 50k ocset r ocset c bst apw8706 (note6) apw8707
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 10 APW8703/6/7 function description vcc power-on-reset (por) a power-on-reset (por) function is designed to pre- vent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply voltage on the vcc pin if at least one of the enable pins is set high. when the vcc supply voltage exceeds the rising por threshold, the por enables the device. the por circuit has a hysteresis and a deglitch feature so that it will typically ignore undershoot transients on the vcc pin. smod APW8703/6/7 can be operated in the skip mode using smod pin. when smod is low, the ic will enter the skip mode. in skip mode if the pwm is low and the zc is detected, the gl will be pulled low, and low-side mosfet will be off. it is useful if the converter has to operation in skip mode to improve efficiency at light load. when smod is high, the converter will operate in force pwm mode. enable control pulling the ven above 2v will enable the driver output, and pulling ven below 0.8v will disable the driver output. if enable function is not used, connect en to vcc for normal operation. over-current protection (ocp) the over-current protection function protects the switch- ing converter to against over-current or short-circuit conditions. the ic senses the inductor current by detect- ing the drain to source voltage of low-side mosfet dur- ing it s on-state. when the inductor current is over the internal ocp trip point, the both of gate drivers will be latched off. figure 2. current limit algorithm pwm control the pwm pin has three states. if the pin is gave high level state, the internal pre-driver output of high-side (gh) goes high and internal pre-driver output of low-side (gl) goes low. if the pin is gave low level state, the gh goes low and gl goes high. if the pin is gave tri-state level, the gh goes low and gl goes high. please refer to table 1. the current limit circuit employs a "valley" current-sens- ing algorithm (see figure 2). the APW8703/6/7 use the low-side mosfet s r ds(on) of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at lx pin is above the current-limit threshold, the pwm is not allowed to initiate a new cycle. the current-limit threshold is given by: i limit =(190mv-r ocset *10ua)/r on_l the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and input voltage. time i n d u c t o r c u r r e n t 0 i peak i out i limit i ocb output the APW8703/6/7 provide an open-drain output to indi- cate that a fault has occurred. when current-limit occurs for a deglitch time of t d(ocb) , the ocb goes low. since the ocb pin is an open-drain output, connecting a resistor to a pull high voltage is necessary. over-temperature protection (otp) when the junction temperature increases above the ris- ing threshold temperature t otr , the ic will enter the over temperature protection state that suspends the pwm, which forces the ug and lg gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 45 o c. the otp designed with a 45 o c hysteresis lowers the average t j during con- tinuous thermal overload conditions, which increases life- time of the APW8703/6/7.
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 11 APW8703/6/7 layout consideration for all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. if the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. the input capacitors should be placed close to the vin pin, and the ground terminals of input capacitors and output capacitors should be close pgnd pin. 2. to minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the lx pin to minimize the noise coupling into other circuits. 3. the traces of pwm signal from the pwm controller to the pwm pin of APW8703/6/7 should be short to elimi- nate the parasitical capacitance; the parasitical capaci- tance will cause an invalid pwm signal.
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 12 APW8703/6/7 package information tqfn4x4-23 note : 1. follow from jedec mo-229 wccd-3. e d pin 1 b a a1 a3 nx aaa c e 1 pin 1 corner d1 d2 e 2 k l e 0.124 d2 2.95 3.15 0.116 0.057 e1 1.24 1.44 0.049 0.70 0.041 0.028 0.002 0.50 bsc 0.020 bsc k 0.20 0.008 3.90 4.10 0.154 0.161 3.90 4.10 0.154 0.161 0.08 aaa 0.003 s y m b o l min. max. 0.80 0.00 0.20 0.30 2.58 2.78 0.05 0.85 a a1 b d d1 e e2 e l millimeters a3 0.20 ref tqfn4x4-23 0.35 0.45 1.05 0.008 ref min. max. inches 0.032 0.000 0.008 0.012 0.102 0.109 0.033 0.014 0.018
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 13 APW8703/6/7 package information tqfn5x5-30 d pin 1 e a b a1 a3 nx aaa c pin 1 corner d1 k1 d2 e 1 k 1 e 2 l k e d3 s y m b o l min. max. 0.80 0.00 0.20 0.30 3.56 3.76 0.05 1.80 a a1 b d d3 e e2 e l millimeters a3 0.20 ref tqfn5*5-30 0.35 0.45 2.00 0.008 ref min. max. inches 0.031 0.000 0.008 0.012 0.140 0.148 0.071 0.014 0.018 0.70 0.079 0.028 0.002 0.50 bsc 0.020 bsc 0.20 0.008 k 4.90 5.10 0.193 0.201 4.90 5.10 0.193 0.201 0.08 0.003 aaa 0.046 d2 0.97 1.17 0.038 0.091 2.12 d1 2.32 0.083 0.059 1.29 e1 0.051 1.49 k1 0.37 ref 0.015 ref
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 14 APW8703/6/7 devices per unit carrier tape & reel dimensions package type unit quantity tqfn4x4 tape & reel 3000 tqfn5x5 tape & reel 2500 application a h t1 c d d w e1 f 330.0 2.00 50 min. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 12.0 0.30 1.75 0.10 5.50 0.10 p0 p1 p2 d0 d1 t a0 b0 k0 tqfn4x4 4.00 0.10 8.00 0.10 2.00 0.05 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 4.30 0.20 4.30 0.20 1.00 0.20 application a h t1 c d d w e1 f 330.0 2.00 50 min. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 12.0 0.30 1.75 0.10 5.5 0.10 p0 p1 p2 d0 d1 t a0 b0 k0 tqfn 5x5 4.0 0.10 8.0 0.10 2.0 0.10 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 5.35 0.20 5.35 0.20 1.00 0.20 (mm) h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 15 APW8703/6/7 taping direction information tqfn4x4-23 user direction of feed tqfn5x5-30 user direction of feed
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 16 APW8703/6/7 classification profile
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 17 APW8703/6/7 classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ 125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma reliability test program
copyright ? anpec electronics corp. rev. a.2 - jan, 2016 www.anpec.com.tw 18 APW8703/6/7 customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838

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