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smsc lan9420/lan9420i datasheet revision 1.6 (07-18-11) datasheet product features lan9420/lan9420i single-chip ethernet controller with hp auto-mdix support and pci interface highlights ? optimized for embedded appl ications with 32-bit risc cpus ? integrated descriptor based scatter-gather dma and irq deassertion timer effect ively increase network throughput and reduce cpu loading ? integrated ethernet mac with full-duplex support ? integrated 10/100 etherne t phy with hp auto-mdix support ? 32-bit, 33mhz, pci 3.0 compliant interface ? reduced power operating modes with pci power management specification 1.1 compliance ? supports multiple audio & video streams over ethernet target applications ? cable, satellite, and ip set-top boxes ? digital televisions ? digital video recorders ? home gateways ? digital media clients/servers ? industrial au tomation systems ? industrial/single board pc ? kiosk/pos enterprise equipment key benefits ? integrated high-perfor mance 10/100 ethernet controller ? fully compliant with ieee802.3/802.3u ? integrated ethernet mac and phy ? 10base-t and 100base-tx support ? full- and half-duplex support ? full-duplex flow control ? preamble generation and removal ? automatic 32-bit crc generation and checking ? automatic payload padding and pad removal ? loop-back modes ? flexible address filtering modes ? one 48-bit perfect address ? 64 hash-filtered multicast addresses ? pass all multicast ? promiscuous mode ? inverse filtering ? pass all incoming with status report ? wakeup packet support ? integrated 10/100 ethernet phy ? auto-negotiation ? automatic polarity detection and correction ? supports hp auto-mdix ? supports energy-detect power down ? support for 3 status leds ? receive and transmit tcp checksum offload ? pci interface ? pci local bus specification revision 3.0 compliant ? 32-bit/33-mhz pci bus ? descriptor based scatter-gather dma enables zero- copy drivers ? comprehensive power management features ? supports pci bus power management interface specification, revision 1.1 ? supports optional wake from d3cold (via configuration strap option when vaux is available) ? wake on lan ? wake on link status change (energy detect) ? magic packet wakeup ? general purpose i/o ? 3 programmable gpio pins ? 2 gpo pins ? support for optional eeprom ? serial interface provided for eeprom ? used to store pci and mac address configuration values ? miscellaneous features ? big/little/mixed endian support for registers, descriptors, and buffers ? irq deassertion timer ? general purpose timer ? single 3.3v power supply ? integrated 1.8v regulator ? packaging ? available in 128-pin vtqfp lead-free rohs compliant package ? environmental ? available in commercial & industrial temperature ranges
order numbers: LAN9420-NU for 128-pin vtqfp, lead-free rohs compliant package (0 to 70 o c) lan9420i-nu for 128-pin vtqfp, lead-free rohs compliant package (-40 o to 85 o c) this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 2 smsc lan9420/lan9420i datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000 or 1 (800) 443-semi copyright ? 2011 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 3 revision 1.6 (07-18-11) datasheet table of contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 pci bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 ethernet phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.7 system control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.7.1 interrupt controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.7.2 pll and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.7.3 eeprom controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.7.4 gpio/led controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.7.5 general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 1.7.6 free run counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.8 control and status registers (csr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 chapter 2 pin description and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 chapter 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 pci bridge (pcib). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 pci bridge (pcib) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 pci interface environments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.3 pci master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.3.1 pci master transaction errors....................................................................................... 25 3.2.4 pci target interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.4.1 pci configuration space registers ............................................................................... 26 3.2.4.2 control and status registers (csr) .............................................................................. 26 3.2.4.2.1 csr endianness....................................................................................................... 2 6 3.2.4.2.2 i/o mapping of csr.................................................................................................. 27 3.2.4.3 pci target interface transaction errors ........................................................................ 27 3.2.4.4 pci discard timer....................................................................................................... ... 27 3.2.5 interrupt gating logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 system control block (scb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 interrupt controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.2 wake event detection logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.3 general purpose timer (gpt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.4 free-run counter (frc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.5 eeprom controller (epc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.5.1 eeprom format . ................ ................ ................ ................ ................ ............. ............. 31 3.3.5.2 mac address, subsystem id, and sub system vendor id auto-load ........................... 32 3.3.5.3 eeprom host oper ations............ ................. ................ ............. ............. ............ .......... 32 3.3.5.3.1 supported eeprom oper ations .............. ................ ............. ............. ............ .......... 34 3.3.5.3.2 host initiated mac ad dress, ssid, ssvid re load ........ ................ ................ .......... 37 3.3.5.3.3 eeprom command and da ta registers .......... ................ ................. ............ ..........37 3.3.5.3.4 eeprom timing ................ ................ ................ ................ ................. ............ .......... 37 3.3.6 system control and status registers (scsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 dma controller (dmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.1 dma controller architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 4 smsc lan9420/lan9420i datasheet 3.4.2 data descriptors and buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.2.1 receive descriptors ..................................................................................................... .. 41 3.4.2.2 transmit descriptors.................................................................................................... ... 45 3.4.3 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.4 transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.5 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.6 receive descriptor acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.7 suspend state behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 3.4.7.1 transmit engine ......................................................................................................... .... 51 3.4.7.2 receive engine .......................................................................................................... .... 51 3.4.8 stopping transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.9 tx buffer fragmentation rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.9.1 calculating worst-case tx fifo (mil) usage.............................................................. 52 3.4.10 dmac interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.11 dmac control and status registers (dcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5 10/100 ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5.1 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5.1.1 full-duplex flow control................................................................................................ 54 3.5.2 virtual local area network (vlan) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.5.3 address filtering functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5.3.1 perfect filtering ....................................................................................................... ....... 56 3.5.3.2 hash only filtering mode........................ ....................................................................... 5 6 3.5.3.3 hash perfect filtering .................................................................................................. .. 57 3.5.3.4 inverse filtering ....................................................................................................... ...... 57 3.5.4 wakeup frame detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.4.1 magic packet detection ................................................................................................. 6 0 3.5.5 receive checksum offload engine (rxcoe). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5.5.1 rx checksum calculation ............................................................................................. 63 3.5.6 transmit checksum offload engine (txcoe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.5.6.1 tx checksum calculation..............................................................................................64 3.5.7 mac control and status registers (mcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.6 10/100 ethernet phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.6.1 100base-tx transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.6.1.1 4b/5b encoding .......................................................................................................... ... 65 3.6.1.2 scrambling .............................................................................................................. ....... 67 3.6.1.3 nrzi and mlt3 encoding ............................................................................................. 67 3.6.1.4 100m transmit driver.................................................................................................... .67 3.6.1.5 100m phase lock loop (pll) ....................................................................................... 67 3.6.2 100base-tx receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.6.2.1 100m receive input ...................................................................................................... .68 3.6.2.2 equalizer, baseline wan der correction and clock and data recovery ........................ 68 3.6.2.3 nrzi and mlt-3 decoding ............................................................................................ 68 3.6.2.4 descrambling ............................................................................................................ ..... 69 3.6.2.5 alignment ............................................................................................................... ........ 69 3.6.2.6 5b/4b decoding .......................................................................................................... ... 69 3.6.2.7 receiver errors ......................................................................................................... ..... 69 3.6.3 10base-t transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.6.3.1 10m transmit data across the internal mii bu s ............................................................ 70 3.6.3.2 manchester encoding ................................ .................................................................... 7 0 3.6.3.3 10m transmit drivers.................................................................................................... .70 3.6.4 10base-t receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.6.4.1 10m receive input and squelch ............. ....................................................................... 70 3.6.4.2 manchester decoding .................................................................................................... 7 0 3.6.4.3 jabber detection ........................................................................................................ .... 70
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 5 revision 1.6 (07-18-11) datasheet 3.6.5 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.6.6 parallel detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.6.6.1 re-starting auto-negotiation .......................................................................................... 72 3.6.6.2 disabling auto-negotiation ............................................................................................. 7 2 3.6.6.3 half vs. full-duplex .................................................................................................... .... 72 3.6.7 hp auto-mdix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.6.8 phy power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.6.8.1 general power-down..................................................................................................... 7 3 3.6.8.2 energy detect power-down........................................................................................... 74 3.6.9 phy resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.6.9.1 phy soft reset via pmt_ctrl bit 10 (phy_rst)....................................................... 74 3.6.9.2 phy soft reset via phy basic control register bit 15 (phy reg. 0.15) ...................... 74 3.6.10 required ethernet magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.6.11 phy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.7.2 related external signals and power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.7.3 device clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.7.4 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.7.4.1 g3 state (mechanical off) ............................................................................................. 76 3.7.4.1.1 power management events in g3 ................................................................................................. 76 3.7.4.1.2 exiting the g3 state .................................................................................................. 76 3.7.4.2 d0unintialized state (d0u) ...................................................................................... 77 3.7.4.2.1 exiting the d0u state................................................................................................ 7 7 3.7.4.3 d0active state (d0a).................................................................................................. 77 3.7.4.3.1 power management events in d0a............................................................................................... 77 3.7.4.3.2 exiting the d0a state................................................................................................ 7 8 3.7.4.4 the d3hot state ......................................................................................................... .78 3.7.4.4.1 power management events in d3hot.......................................................................................... 78 3.7.4.4.2 exiting the d3hot state........................................................................................... 78 3.7.4.5 the d3cold state ........................................................................................................ 79 3.7.4.5.1 power management events in d3cold ....................................................................................... 79 3.7.4.5.2 exiting the d3cold state ........................................................................................ 79 3.7.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.7.5.1 phy resets .............................................................................................................. ..... 80 3.7.6 detecting power management events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.7.6.1 enabling wakeup frame wake events ..... .................................................................... 82 3.7.7 enabling link status change (energy detect) wake events . . . . . . . . . . . . . . . . . . . . . 82 chapter 4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.1 register nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.2 system control and status registers (scsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.2.1 id and revision (id_rev) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.2 interrupt control register (int_ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.2.3 interrupt status register (int_sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.4 interrupt configuration register (int_cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.5 general purpose input/output configuration regi ster (gpio_cfg) . . . . . . . . . . . . . . . 93 4.2.6 general purpose timer configuration register (gpt_cfg) . . . . . . . . . . . . . . . . . . . . . 95 4.2.7 general purpose timer current count register (g pt_cnt) . . . . . . . . . . . . . . . . . . . . . 96 4.2.8 bus master bridge configuratio n register (bus_cfg) . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.2.9 power management control register (pmt_ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.2.10 free run counter (free_run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2.11 eeprom command register (e2p_cmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.12 eeprom data register (e2p_data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 6 smsc lan9420/lan9420i datasheet 4.3 dmac control and status registers (dcsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.3.1 bus mode register (bus_mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.2 transmit poll demand register (tx_poll_demand) . . . . . . . . . . . . . . . . . . . . . . . . 106 4.3.3 receive poll demand register (rx_poll_demand). . . . . . . . . . . . . . . . . . . . . . . . . 107 4.3.4 receive list base address re gister (rx_base_addr) . . . . . . . . . . . . . . . . . . . . . . . 108 4.3.5 transmit list base address register (tx_base_addr). . . . . . . . . . . . . . . . . . . . . . . 109 4.3.6 dma controller status register (dmac_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.3.7 dma controller control (operation mode) regi ster (dmac_control) . . . . . . . . . . 112 4.3.8 dma controller interrupt enable register (dmac_intr_ena) . . . . . . . . . . . . . . . . . . 114 4.3.9 missed frame and buffer overflow counte r reg (miss_frame_cntr) . . . . . . . . . . 116 4.3.10 current transmit buffer address register (tx_ buff_addr) . . . . . . . . . . . . . . . . . . . 117 4.3.11 current receive buffer address register (rx_ buff_addr) . . . . . . . . . . . . . . . . . . . 118 4.4 mac control and status registers (mcsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.4.1 mac control register (mac_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.4.2 mac address high register (addrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.3 mac address low register (addrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.4.4 multicast hash table high register (hashh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.4.5 multicast hash table low register (hashl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.4.6 mii access register (mii_access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.4.7 mii data register (mii_data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.4.8 flow control register (flow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.4.9 vlan1 tag register (vlan1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.4.10 vlan2 tag register (vlan2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.4.11 wakeup frame filter (wuff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.4.12 wakeup control and status register (wucsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.4.13 checksum offload engine control register (coe_cr) . . . . . . . . . . . . . . . . . . . . . . . . 135 4.5 phy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.5.1 basic control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.5.2 basic status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.5.3 phy identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.5.4 phy identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.5.5 auto negotiation advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.5.6 auto negotiation link part ner ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.5.7 auto negotiation expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.5.8 mode control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.5.9 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.5.10 special control/status indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.5.11 interrupt source flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.5.12 interrupt mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.5.13 phy special control/status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.6 pci configuration space csr (config csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.6.1 pci power management capabilit ies register (pci_pmc) . . . . . . . . . . . . . . . . . . . . . 152 4.6.2 pci power management control and status re gister (pci_pmcsr) . . . . . . . . . . . . . 154 chapter 5 operational characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.1 absolute maximum ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.2 operating conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.1 d0 - normal operation with ethernet traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.2 d3 - enabled for wake up packet detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.3.3 d3 - enabled for link status change detection (e nergy detect) . . . . . . . . . . . . . . . . . 158 5.3.4 d3 - phy in general power down mo de. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.5 maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.4 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 7 revision 1.6 (07-18-11) datasheet 5.5 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.5.1 equivalent test load (non-pci signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.6 pci clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.7 pci i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.8 eeprom timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 5.9 clock circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 chapter 6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.1 128-vtqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 chapter 7 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 8 smsc lan9420/lan9420i datasheet list of figures figure 1.1 system level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 1.2 lan9420/lan9420i internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2.1 lan9420/lan9420i 128-vtqfp (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3.1 pci bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 3.2 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3.3 csr double endian mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 3.4 i/o bar mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 3.5 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 3.6 interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 3.7 eeprom access flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 3.8 eeprom erase cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 3.9 eeprom eral cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 3.10 eeprom ewds cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 3.11 eeprom ewen cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 3.12 eeprom read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 3.13 eeprom write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 3.14 eeprom wral cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 3.15 ring and chain descriptor structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 3.16 receive descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 3.17 transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 3.18 vlan frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 3.19 rxcoe checksum calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 3.20 type ii ethernet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 3.21 ethernet frame with vlan tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 3.22 ethernet frame with length field and snap header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 3.23 ethernet frame with vlan tag and snap header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 3.24 ethernet frame with multiple vlan tags and sn ap header . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 3.25 100base-tx data path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 3.26 receive data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3.27 direct cable connection vs. cross-over cable connection . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 3.28 lan9420/lan9420i device power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 3.29 wake event detection block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 4.1 lan9420/lan9420i csr memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 4.2 example addrl, addrh address ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 5.1 output equivalent test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 5.2 pci clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 5.3 pci i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 5.4 eeprom timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 6.1 lan9420/lan9420i 128-vtqfp package definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 6.2 lan9420/lan9420i 128-vtqfp recommended pcb land pattern . . . . . . . . . . . . . . . . . 169
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 9 revision 1.6 (07-18-11) datasheet list of tables table 2.1 pci bus interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2.2 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2.3 gpio and led pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2.4 configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2.5 pll and ethernet phy pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 2.6 power and ground pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 2.7 no-connect pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 2.8 128-vtqfp package pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3.1 pci address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 3.2 eeprom format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 3.3 eeprom variable defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 3.4 required eeclk cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 3.5 rdes0 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 3.6 rdes1 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 3.7 rdes2 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 3.8 rdes3 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 3.9 tdes0 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 3.10 tdes1 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 3.11 tdes2 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 3.12 tdes3 bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 3.13 address filtering modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 3.14 wakeup frame filter register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 3.15 filter i byte mask bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 3.16 filter i command bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 3.17 filter i offset bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 3.18 filter i crc-16 bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 3.19 wakeup generation cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 3.20 tx checksum preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 3.21 4b/5b code table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 3.22 reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 3.23 phy resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 4.1 register bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 4.2 system control and status register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 4.3 eeprom enable bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 4.4 dmac control and status register (dcsr) map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 4.5 mac control and status register (mcsr) map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 4.6 addrl, addrh byte ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 4.7 phy control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 4.8 mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 4.9 pci configuration space csr (config csr) addres s map . . . . . . . . . . . . . . . . . . . . . . . 150 table 4.10 standard pci header registers supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 5.1 d0 - normal operation - supply and current (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 5.2 d3 - enabled for wake up packet detection - su pply and current (typical) . . . . . . . . . . . . 158 table 5.3 d3 - enabled for link status change detection - supply and current (typical) . . . . . . . . . . 158 table 5.4 d3 - phy in general power down mode - supply and current (typical) . . . . . . . . . . . . . . . 159 table 5.5 maximum power consumption - supply and current (maximum). . . . . . . . . . . . . . . . . . . . . 159 table 5.6 i/o buffer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 5.7 100base-tx transceiver ch aracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 5.8 10base-t transceiver char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 61 table 5.9 pci clock timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 5.10 pci i/o timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 table 5.11 pci i/o timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 10 smsc lan9420/lan9420i datasheet table 5.12 eeprom timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 5.13 lan9420/lan9420i crystal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 table 6.1 lan9420/lan9420i 128-vtqfp dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 7.1 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 11 revision 1.6 (07-18-11) datasheet chapter 1 introduction 1.1 block diagrams figure 1.1 system level block diagram figure 1.2 lan9420/lan9420i internal block diagram external 25mhz crystal gpios/leds (optional) eeprom (optional) lan9420/lan9420i pci host pci device pci device magnetics to ethernet pci bus lan9420/lan9420i 10/100 ethernet phy ethernet pll eeprom (optional) gpios/leds (optional) 25mhz 3.3v to 1.8v regulator mac interface layer (mil) mac ethernet mac pci pci target pci master pci bridge (pcib) tx dma engine rx dma engine dma controller dma control & status registers (dcsr) mac control & status registers (mcsr) tx fifo (2kb) rx fifo (2kb) tx coe rx coe +3.3v interrupt controller (int) power management (pm) system control & status registers (scsr) eeprom controller (epc) gpio/led controller (gpio) gp timer free-run counter system control block (scb) arbiter
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 12 smsc lan9420/lan9420i datasheet 1.2 general description lan9420/lan9420i is a full-featur ed, fast ethernet controller whic h allows for the easy and cost- effective integration of fast ethernet into a pci-based system. a system configuration diagram of lan9420/lan9420i in a typical embedded environment can be seen in figure 1.1 , followed by an internal block diagram of lan9420/lan9420i in figure 1.2 . lan9420/lan9420i consists of a pci local bus specification revisi on 3.0 compliant interface , dma controller, ethernet mac, and 10/100 ethernet phy. lan9420/lan9420i provides full ieee 802.3 complia nce and all internal components support full/half- duplex 10base-t, 100base-tx, and man ual full-duplex flow control. the descriptor based scatter- gather dma supports usage of zero-copy drivers, effectively increasing throughput while decreasing host load. the integrated irq deassertion timer allows a minimum irq deassertion time to be set, providing reduced host load and greater contro l over service routines. automatic 32-bit crc generation/checking, automatic payload padding, and 2k jumbo packets (2048 byte) are supported. big, little, and mixed endian support provides independe nt control over register, descriptor, and buffer endianess. this feature enables easy integration into various arm/mips/powerpc designs. lan9420/lan9420i supports the pci bus power mana gement interface specification revision 1.1 and provides the optional ability to generate wake events in the d3cold state when vaux is available. wake on lan, wake on link status c hange (energy detect), and magic packet wakeup detection are also supported, allowing for a range of power management options. lan9420/lan9420i contains an eeprom controller for connection to an optional eeprom. this allows for the automatic loading of static configur ation data upon power-up or reset. when connected, the eeprom can be configured to load a predete rmined mac address, the pci ssid, and the pci ssvid of lan9420/lan9420i. in addition to the primary functionality desc ribed above, lan9420/lan9420i provides additional features designed for extended functionality. these include a multipurpose 16-bit configurable general purpose timer (gpt), a free-run counter, a 3-pin configurable gpio/led interface, and 2 gpo pins. all aspects of lan9420/lan9420i are managed vi a a set of memory mapped control and status registers. lan9420/lan9420i?s performance and f eatures make it an ideal solution for many applications in the consumer electronics, enterprise, and industrial auto mation markets. targeted applications include: set top boxes (cable, satellite and ip), digital television s, digital video recorders, home gateways, digital media clients/servers, industrial automation sy stems, industrial single board pcs, and kiosk/pos enterprise equipment.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 13 revision 1.6 (07-18-11) datasheet 1.3 pci bridge lan9420/lan9420i implements a pci local bus spec ification revision 3.0 compliant interface, supporting the pci bus power management interface specification revision 1.1. it provides the pci configuration space control and st atus registers used to configure lan9420/lan9420i for pci device operation. please refer to section 3.2, "pci brid ge (pcib)," on page 23 for more information. 1.4 dma controller the dma controller consists of independent transm it and receive engines and a control and status register (csr) space. the transmit engine transfer s data from host memory to the mac interface layer (mil) while the receive engi ne transfers data from the mil to host memory. the controller utilizes descriptors to efficiently move data from source to destination with minimal processor intervention. descriptors are dword aligned data st ructures in system memory that inform the dma controller of the location of data buffers in host memory and also provide a mechanism for communicating the status to the host cpu. the dma controller has been designed for packet-oriented data transfer, such as frames in et hernet. zero copy dma transfer is supported. copy operations for the purpose of data re-alignment are not required in the case where buffers are fragmented or not aligned to a dword boundary. the controller can be programmed to interrupt the host on the occurrence of particular events, such as frame transmit or rece ive transfer completed, and other normal, as well as error, conditions. please refer to section 3.4, "dma controller (dmac)," on page 38 for more information. 1.5 ethernet mac the transmit and receive data paths are separate within the 10/100 ethernet mac, allowing the highest performance, especially in full duplex mode. the data paths connect to the pci bridge via a dma engine. the mac also implements a csr space used by the host to obtain status and control its operation. the mac interface layer (mil), within t he mac, contains a 2k byte transmit and receive fifo. the mil supports store and forward and operate on second frame mode for minimum inter- packet gap. please refer to section 3.5, "10/100 et hernet mac," on page 53 for more information. 1.6 ethernet phy the phy implements an ieee 802.3 physical layer fo r twisted pair ethernet applications. it can be configured for either 100 mbps (100base-tx) or 10 mbps (10base-t) ethernet o peration in either full or half duplex configurations. the phy block in cludes support for auto-negotiation, auto-polarity correction and auto-mdix. minimal external components are required for the utilization of the integrated phy. please refer to section 3.6, "10/100 et hernet phy," on page 64 for more information. 1.7 system control block the system control block provides the following additional elemen ts for system operation. these elements are controlled via its system control and status registers (scsr). please refer to section 3.3, "system control block (scb)," on page 28 for more information. 1.7.1 interrupt controller the interrupt controller (int) can be programmed to issue a pci interrupt to the host on the occurrence of various events. please refer to section 3.3.1, "interrupt controller," on page 28 for more information.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 14 smsc lan9420/lan9420i datasheet 1.7.2 pll and power management lan9420/lan9420i interfaces with a 25mhz crystal osci llator from which all internal clocks, with the exception of pci clock, are generated. the intern al clocks are all generated by the pll and power management blocks. various power savings modes exis ts that allow for the clocks to be shut down. these modes are defined by the power stat e of the pci function. please refer to section 3.7, "power management," on page 74 for more information. 1.7.3 eeprom controller lan9420/lan9420i provides support for an op tional eeprom via the eepr om controller. please refer to section 3.3.5, "eeprom co ntroller (epc)," on page 31 for more information. 1.7.4 gpio/led controller the 3-bit gpio and 2-bit gpo (multiplexed on the led and eeprom pins) interface is managed by the gpio/led controller. it is accessible via the system control and status registers (scsr). the gpio signals can function as inputs, push-pull outputs and open drain outputs. the gpios can also be configured to trigger interrupts with programmable polarity. the gpos are outputs only and have no means of generating interrupts. please refer to section 4.2.5, "general purpose input/output configuration register (gpio_cfg)," on page 93 for more information. 1.7.5 general purpose timer the general purpose timer has no dedicat ed function within lan9420/lan9420i and may be programmed to issue a timed interrupt. please refer to section 3.3.3, "general purpose timer (gpt)," on page 30 for more information. 1.7.6 free run counter the free run counter has no dedicated function within lan9420/lan9420i and may be used by the software drivers as a ti mebase. please refer to section 3.3.4, "free-run counter (frc)," on page 31 for more information. 1.8 control and status registers (csr) lan9420/lan9420i?s functions are controlled and m onitored by the host via the control and status registers (csr). this register space includes re gisters that control and monitor the dma controller (dma control and status registers - dcsr), the mac (mac control and status registers - mcsr), the phy (accessed indirectly thr ough the mac via the mii_access a nd mii_data registers), and the elements of the system control block via the syst em control and status registers (scsr). the csr may be accessed be via i/o or memory operations. big or little endian access is also configurable.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 15 revision 1.6 (07-18-11) datasheet chapter 2 pin description and configuration figure 2.1 lan9420/lan9420i 128-vtqfp (top view) smsc lan9420/lan9420i 128-vtqfp top view 97 nc ad15 nc par ncbe1 vdd33io nserr nperr vss ndevsel nstop nirdy ntrdy vss vdd33io nframe vss ad16 ncbe2 ad18 ad17 vss vdd33io ad20 ad19 ad22 ad21 vdd33io ad23 idsel vss ncbe3 nc eecs eeclk/gpo4 eedio/gpo3 nc vdd33io nc ad0 vss ad2 ad1 ad4 ad3 vdd18core vss vss vdd33io ad6 ad5 ncbe0 ad7 vdd33io ad8 ad9 vss ad11 ad10 ad13 ad12 vss vdd33io ad14 gpio1/nled2 vdd33io gpio2/nled3 vdd33io vss vdd33io vdd33io vdd18core vdd18core vss vss vdd33io vss pcinrst nint ngnt pciclk npme nreq vdd33io vss ad30 ad31 ad28 ad29 vss ad27 ad26 vdd33io ad24 ad25 nc 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc nc nc nc nc gpio0/nled1 vauxdet pwrgood xi xo vss vdd18pll vdd18tx automdix_en nc nc nc vdd33bias vss exres vss vdd33a tpi+ nc tpi- vdd33a vss tpo+ tpo- vss nc nc note: when hp auto-mdix is activated, the tpo+/- pins function as tpi+/- and vice-versa.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 16 smsc lan9420/lan9420i datasheet 2.1 pin list table 2.1 pci bus interface pins num pins name symbol buffer type description 1 pci clock in pciclk is pci clock in: 0 to 33mhz pci clock input. 1 pci frame nframe ipci/ opci pci cycle frame 32 pci address and data bus ad[31:0] ipci/ opci pci address and data bus 1 pci reset pcinrst is pci reset 4pci bus command and byte enables ncbe[3:0] ipci/ opci pci bus command and byte enables 1 pci initiator ready nirdy ipci/ opci pci initiator ready 1pci target ready ntrdy ipci/ opci pci target ready 1pci stop nstop ipci/ opci pci stop 1 pci device select ndevsel ipci/ opci pci device select 1 pci parity par ipci/ opci pci parity 1pci parity error nperr ipci/ opci pci parity error 1 pci system error nserr ipci/ opci pci system error 1 pci interrupt nint opci pci interrupt note: this pin is an open drain output. 1 pci idsel idsel ipci pci idsel 1 pci request nreq opci pci request note: this pin is a tri-state output. 1pci grant ngnt ipci pci grant 1 pci power management event npme opci pci power management event note: this pin is an open drain output. 1 power good pwrgood is (pd) pci bus power good: this pin is used to sense the presence of pci bus power during the d3 power management state. note: this pin is pulled low through an internal pull- down resistor 1v aux detection vauxdet is (pd) pci auxiliary voltage sense: this pin is used to sense the presence of a 3.3v auxiliary supply in order to define the pme support available. note: this pin is pulled low through an internal pull- down resistor
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 17 revision 1.6 (07-18-11) datasheet note 2.1 this pin is used for factory testing and is latched on power up. this pin is pulled high through an internal resistor and must not be pulled low externally. this pin must be augmented with an external resistor when conne cted to a load. the value of the resistor must be such that the pin reaches its valid level before de-assertion of pcinrst following power up. the ?is? input buffer type is enabled only during power up. the ?is? input buffer type is disabled at all other times. table 2.2 eeprom num pins name symbol buffer type description 1 eeprom data eedio is/o8 eeprom data: this bi-directional pin can be connected to an optional serial eeprom dio. gpo3 gpo3 o8 general purpose output 3: this pin can also function as a general purpose output. the eecs pin is deasserted so as to never unintentionally access the serial eeprom. tx_en tx_en o8 tx_en signal monitor: this pin can also be configured to monitor the tx_en signal on the internal mii port. the eecs pin is deasserted so as to never unintentionally access the serial eeprom. tx_clk tx_clk o8 tx_clk signal monitor: this pin can also be configured to monitor the tx_clk signal on the internal mii port. the eecs pin is deasserted so as to never unintentionally access the serial eeprom. 1 eeprom chip select eecs o8 serial eeprom chip select . 1 eeprom clock eeclk is/o8 (pu) note 2.1 eeprom clock: serial eeprom clock pin gpo4 gpo4 o8 general purpose output 4: this pin can also function as a general purpose output. the eecs pin is deasserted so as to never unintentionally access the serial eeprom. rx_dv rx_dv o8 rx_dv signal monitor: this pin can also be configured to monitor the rx_dv signal on the internal mii port. the eecs pin is deasserted so as to never unintentionally access the serial eeprom. rx_clk rx_clk o8 rx_clk signal monitor: this pin can also be configured to monitor the rx_clk signal on the internal mii port. the eecs pin is deasserted so as to never unintentionally acce ss the serial eeprom.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 18 smsc lan9420/lan9420i datasheet table 2.3 gpio and led pins num pins name symbol buffer type description 1 general purpose i/o data 0 gpio0 is/o12/ od12 general purpose i/o data 0: this general-purpose pin is fully programmable as either push-pull output, open-drain output or input by writing the gpio_cfg configuration register in the scsr. gpio pins are schmitt-triggered inputs. nled1 (speed indicator) nled1 od12 nled1 (speed indicator): this pin can also function as the ethernet speed indicator led and is driven low when the operating speed is 100m bs, during auto-negotiation, and when the cable is disconnected. this pin is driven high only during 10mbs operation. 1 general purpose i/o data 1 gpio1 is/o12/ od12 general purpose i/o data 1: this general-purpose pin is fully programmable as either push-pull output, open-drain output or input by writing the gpio_cfg configuration register in the scsr. gpio pins are schmitt-triggered inputs. nled2 (link & activity indicator) nled2 od12 nled2 (link & activity indicator): this pin can also function as the ethernet link and activity indicator led and is driven low (led on) when lan9420/lan9420i detects a valid link. this pin is pulsed high (led off) for 80ms whenever transmit or receive activity is detected. this pin is then driven low again for a minimum of 80ms, after which time it will repeat the process if tx or rx activity is detected. effectively, led2 is activated solid for a link. when transmit or rece ive activity is sensed, led2 will flash as an activity indicator. 1 general purpose i/o data 2 gpio2 is/o12/ od12 general purpose i/o data 2: this general-purpose pin is fully programmable as either push-pull output, open-drain output or input by writing the gpio_cfg configuration register in the scsr. gpio pins are schmitt-triggered inputs. nled3 (full- duplex indicator) nled3 od12 nled3 (full-duplex indicator): this pin can also function as the ethernet full- duplex indicator led and is driven low when the link is operating in full-duplex mode. table 2.4 configuration pins num pins name symbol buffer type description 1 automdix enable automdix_en is (pu) automdix enable: enables auto-mdix. pull high or leave unconnected to enable auto-mdix, pull low to disable auto-mdix.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 19 revision 1.6 (07-18-11) datasheet table 2.5 pll and ethernet phy pins num pins name symbol buffer type description 1 crystal input xi iclk crystal input: external 25mhz crystal input. this pin can also be driven by a single-ended clock oscillator. when this method is used, xo should be left unconnected. 1 crystal output xo oclk crystal output: external 25mhz crystal output. 1 ethernet tx data out negative tpo- aio ethernet transmit data out negative: the transmit data outputs may be swapped internally with receive data inputs when auto-mdix is enabled. 1 ethernet tx data out positive tpo+ aio ethernet transmit data out positive: the transmit data outputs may be swapped internally with receive data inputs when auto-mdix is enabled. 1 ethernet rx data in negative tpi- aio ethernet receive data in negative: the receive data inputs may be swapped internally with transmit data outputs when auto-mdix is enabled. 1 ethernet rx data in positive tpi+ aio ethernet receive data in positive: the receive data inputs may be swapped internally with transmit data outputs when auto-mdix is enabled. 1 external phy bias resistor exres ai external phy bias resistor: used for the internal phy bias circuits. connect to an external 12.4k 1.0% resistor to ground.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 20 smsc lan9420/lan9420i datasheet table 2.6 power and ground pins num pins name symbol buffer type description 2 +3.3v analog power supply vdd33a p +3.3v analog power supply refer to the lan9420/lan9420i application note for connection information. 1 +1.8v pll power supply vdd18pll p +1.8v pll power supply: this pin must be connected to vdd18core for proper operation. refer to the lan9420/lan9420i application note for additional connection information. 1 +1.8v tx power supply vdd18tx p +1.8v transmitte r power supply: this pin must be connected to vdd18core for proper operation. refer to the lan9420/lan9420i application note for additional connection information. 1 +3.3v master bias power supply vdd33bias p +3.3v master bias power supply refer to the lan9420/lan9420i application note for additional connection information. 15 +3.3v i/o power vdd33io p +3.3v power supply for i/o pins and internal regulator refer to the lan9420/lan9420i application note for additional connection information. 21 ground vss p common ground for i/o pins, core, and analog circuitry 3 +1.8v core power vdd18core p digital core +1.8v power supply output from internal regulator refer to the lan9420/lan9420i application note for additional connection information. table 2.7 no-connect pins num pins name symbol buffer type description 17 no connect nc - no connect: these pins must be left floating for normal device operation.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 21 revision 1.6 (07-18-11) datasheet table 2.8 128-vtqfp package pin assignments pin num pin name pin num pin name pin num pin name pin num pin name 1 gpio1/nled2 33 ncbe3 65 ad14 97 nc 2 gpio2/nled3 34 idsel 66 vss 98 nc 3 vdd33io 35 vss 67 vdd33io 99 vss 4 vss 36 vdd33io 68 ad13 100 tpo- 5 vdd33io 37 ad23 69 ad12 101 tpo+ 6 vdd33io 38 ad22 70 ad11 102 vss 7 vdd33io 39 ad21 71 ad10 103 vdd33a 8 vdd18core 40 ad20 72 ad9 104 tpi- 9 vdd18core 41 ad19 73 vss 105 nc 10 vss 42 vss 74 vdd33io 106 tpi+ 11 vss 43 vdd33io 75 ad8 107 vdd33a 12 vss 44ad1876ncbe0108vss 13vdd33io45ad1777 ad7109exres 14 nint 46 ad16 78 ad6 110 vss 15 pcinrst 47 ncbe2 79 ad5 111 vdd33bias 16 pciclk 48 nframe 80 vss 112 nc 17 ngnt 49 vss 81 vdd33io 113 nc 18 nreq 50 vss 82 vdd18core 114 nc 19 npme 51 vdd33io 83 vss 115 automdix_en 20 vss 52 nirdy 84 ad4 116 vdd18tx 21 vdd33io 53 ntrdy 85 ad3 117 vdd18pll 22 ad31 54 ndevsel 86 ad2 118 vss 23 ad30 55 nstop 87 ad1 119 xo 24 ad29 56 nperr 88 ad0 120 xi 25 ad28 57 vss 89 vss 121 pwrgood 26 ad27 58 vdd33io 90 vdd33io 122 vauxdet 27 vss 59 nserr 91 nc 123 gpio0/nled1 28 vdd33io 60 par 92 eedio/gpo3 124 nc 29 ad26 61 ncbe1 93 nc 125 nc 30 ad25 62 ad15 94 eecs 126 nc 31 ad24 63 nc 95 eeclk/gpo4 127 nc 32 nc 64 nc 96 nc 128 nc
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 22 smsc lan9420/lan9420i datasheet 2.2 buffer types buffer type description is schmitt-triggered input o8 output with 8ma sink and 8ma source current o12 output with 12ma sink and 12ma source current od12 open-drain output with 12ma sink current ipci pci compliant input opci pci compliant output pu 50ua (typical) internal pull-up. unless otherwise noted in the pin description, internal pull-ups are always enabled. note: internal pull-up resistors prevent unconnec ted inputs from floating. do not rely on internal resistors to drive signals extern al to lan9420/lan9420i. when connected to a load that must be pulled high, an external resistor must be added. pd 50ua (typical) internal pull-down. unless other wise noted in the pin description, internal pull- downs are always enabled. note: internal pull-down resistors prevent unconnec ted inputs from floating. do not rely on internal resistors to drive signals external to lan9420/lan9420i. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional iclk crystal oscillator input oclk crystal oscillator output p power and ground pin
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 23 revision 1.6 (07-18-11) datasheet chapter 3 functional description 3.1 functional overview the lan9420/lan9420i ethernet controller consists of five major functional blocks. these blocks are: ? pci bridge (pcib) ? system control block (scb) ? dma controller (dmac) ? 10/100 ethernet mac ? 10/100 ethernet phy the following sections discuss the features of each block. a block diagram of lan9420/lan9420i is shown in figure 1.2 lan9420/lan9420i internal block diagram on page 11 . 3.2 pci bridge (pcib) the pci bridge (pcib) facilitates lan9420/lan9420i?s operation on a pci bus as a device. it has the following features: pci master interface: this interface connects lan9420/la n9420i to the pci bus when it is functioning as a pci master. it is used by the dma engines to directly access the pci host?s memory. pci target interface: this interface connects lan9420/lan9420i to the pci bus when it is functioning as a pci target. it provides access to pci confi guration space control and status register (config csr), and access to the control and status regist ers (csr) via i/o or non-prefetchable (np) memory accesses. in addition, big/little endian su pport for the registers may be selected. pci power management support: lan9420/lan9420i supports pci bus power management interface specification rev. 1.1. refer to section 3.7, "power management," on page 74 for more information. interrupt gating logic: this logic controls assertion of the nint signal to the host system. pci configuration space control and status registers (config csr): the host system controls and monitors the lan9420/lan9420i dev ice using registers in this space.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 24 smsc lan9420/lan9420i datasheet 3.2.1 pci bridge (p cib) block diagram figure 3.1 pci bridge block diagram pci pci bridge (pcib) pci configuration space csr pci target pme gating interrupt gating pm signal (from pm) i r q ( f r o m i n t ) to/from csr blocks npme nint pm related signals (to/from pm) pci master to/from dmac arbiter
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 25 revision 1.6 (07-18-11) datasheet 3.2.2 pci interface environments the pcib supports only device operation. it functions as a simple bridge, permitting lan9420/lan9420i to act as a master/target pci device on the pci bus. the host performs pci arbitration and is responsible for initializing co nfiguration space for al l devices on the bus. figure 3.2 illustrates device operation. 3.2.3 pci master interface the pci master interface is used by the dma engine s to directly access the pci host?s memory. it is used by the tx and rx dma controllers to acce ss host descriptor ring elements and host dma buffers. no address translation occurs, as these enti ties are contained within the host, which allocates them within the flat pci address space. 3.2.3.1 pci master transaction errors in the event of an error during a descriptor read or during a transmit data read, the dma controller will generate a master bus error interrupt (mberr_int). when an mberr_int is asserted, all subsequent transactions from the dmac will be aborted. in order to cleanly recover fr om this condition, a software reset or h/w reset must be performed. a software reset is accomplished by setting the srst bit of the bus_mode register. note: it is guaranteed that the mberr_int will be reported on the fram e upon which the error occurred as follows: - errors on descriptor reads will be aborted immediately. - errors on tx data will be reported either u pon the data or the close descriptor (if the error occurs on the last data transfer). - dma rx data and descriptor write operations are posted and will ther efore not generate the mberr_int. figure 3.2 device operation pci component pci component host system pci bus pci component lan9420 pcib
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 26 smsc lan9420/lan9420i datasheet 3.2.4 pci target interface the pci target interface implements the address spaces listed in table 3.1 . the pci configuration space is used to identify pci devices, configure memory ranges, and manage interrupts. the host initializes and configures the pci device during a plug-and-play process. the pci target interface supports 32-bit slave accesses only. non 32-bit pci target reads to lan9420/lan9420i will result in a full 32-bit read . non 32-bit pci target writes to lan9420/lan9420i will be silently discarded. 3.2.4.1 pci configurat ion space registers pci configuration space registers include the stan dard pci header registers and pcib extensions to implement power management cont rol/status registers. see section 4.6, "pci configuration space csr (config csr)," on page 150 for further details. these register s exist in the configuration space. 3.2.4.2 control and status registers (csr) the pci target interface allows pci bus master s to directly access the lan9420/lan9420i control and status registers via memory or i/o operations. each set of operations has an associated address range that defines it as follows: ? the non-prefetchable (np) address range is mapped in bar3. no data prefetch is performed when serving pci transactions targeting this address range. ? the i/o address range is mapped in bar4. 3.2.4.2.1 csr endianness the non-prefetchable address range contains a double mapping of the csr. these mappings allow the registers to be accessed in little endian or big endian order. figure 3.3, "csr double endian mapping" illustrates the mapping. ba is the bas e address, as specified by bar3. table 3.1 pci address spaces space size resource configuration 256 bytes pci standard and pcib-specific registers bar0...bar2 reserved bar3 1 kb control and status registers (non-prefetchable area) bar4 256b control and status registers (i/o area) bar5 reserved expansion rom - reserved
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 27 revision 1.6 (07-18-11) datasheet . 3.2.4.2.2 i/o mapping of csr the i/o bar (bar4) is double mapped over the cs r space with the non-prefetchable area. the csr big endian space is disabled, as the host processors (intel x86) that use the i/o bar are little endian. note: a comparison of figure 3.3 with figure 3.4 indicates only the first 256 bytes of csr little endian space is addressable via the i/o bar. . 3.2.4.3 pci target interface transaction errors if the host system atte mpts an unsupported cycle type when accessing the csr via the pci target interface, a slave transaction error will result and the pci target interface will generate a slave bus error interrupt (sberr_int), if enabled. csr may only be read or written as dword quantities and any other type of access is unsupported and will re sult in the assertion of sberr_int. non-dword reads will return a dword while non- dword writes are silently discar ded. in order to cleanly recover from this condition, a software reset or h/w rese t must be performed. a softwa re reset is accomplished by setting the srst bit of the bus_mode register. 3.2.4.4 pci discard timer when the pci master performs a read of lan9420/lan9420i, the pci bridge will fetch the data and acknowledge the pci transfer when data is avai lable. if the pci master malfunctions and does complete the transaction within 32768 pci clocks, lan9420/lan9420i will flush the data to prevent a potential bus lock-up. 3.2.5 interrupt gating logic one set of interrupts exists: pci host interrupt s (pci interrupts from lan9420/lan9420i to the pci host). pci host interrupts result from the assert ion of the internal irq signal from the interrupt controller. refer to section 3.3.1, "interrupt controller," on page 28 for sources of this interrupt. figure 3.5 illustrates how interrupts are sourced by th e interrupt controller to the pcib and are propagated to the host. the interrupt is passed on to the host only when the host has enabled it by setting bit 10 in the pci device command register. the host may obtain interrupt status by reading figure 3.3 csr double endian mapping figure 3.4 i/o bar mapping csr - big endian (512 bytes) ba (bar3) csr - little endian (512 bytes) ba + 1fch ba + 200h ba + 3fch ba (bar4) csr - little endian ( 256 bytes) ba + 0fch i/o bar and non- prefetchable memory are double mapped to the csr space
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 28 smsc lan9420/lan9420i datasheet bit 3 of the pci device status register. the pci device status register and pci device command register are standard registers in pci configuration space. please refer to section 4.6, "pci configuration space csr (config csr)," on page 150 for details. 3.3 system control block (scb) the system control block includes an interrupt cont roller, wake detection logic, a general-purpose timer, a free-run counter and system control and st atus registers. interrupt controller: the interrupt controller can be programmed to interrupt the host system applications on the occu rrence of various events. the interrupt is routed to the host system via the pcib. wake detection logic: this logic detects the occurrence of an enabled wake event and asserts the pci npme signal, if enabled. general purpose timer (gpt): the general purpose timer can be configured to generate a system interrupt upon timeout. free-run counter (frc): a 32-bit free-running counter with a 160 ns resolution. eeprom controller (epc): an optional, external, serial eeprom may be used to store the default values for the mac address, pci subsystem id, and pci subsystem vendor id. in addition, it may also be used for general data storage. the eeprom controller provides lan9420/lan9420i access to the eeprom and permits the host to read, write and erase its contents. system control and status registers (scsr): these registers control sys tem functions that are not specific to the dmac, mac or phy. 3.3.1 interrupt controller the interrupt controller handles the routing of all internal interrupt source s. interrupts enter the controller from various modules within lan9420/lan9420i. the interrupt controller drives the interrupt request (irq) output to the pci brid ge. the interrupt controller is capable of generating pci interrupts on detection of the following internal events: ? dmac interrupt request (dmac_int) ? phy interrupt request (phy_int) figure 3.5 interrupt generation interrupt controller pcib bit 10 pci device command register rw irq bit 3 pci device status register nint (to host)
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 29 revision 1.6 (07-18-11) datasheet ? general-purpose timer interrupt (gpt_int) ? general purpose input/outp ut interrupt (gpiox_int) ? software interrupt (sw_int) ? master bus error interrupt (mberr_int) ? slave bus error interrupt (sberr_int) ? wake event detection (wake_int) a block diagram of the interrupt controller is shown in figure 3.6 . . the interrupt controller control and status register are contained within the system control and status registers (scsr) block. the interrupt status regi ster (int_sts) reflects the current state of the interrupt sources prior to qual ification with their associated enables. the sw_int, mberr_int, sberr_int, gpiox_int, and gpt_int are latched, and are cleared through the scsr block upon a figure 3.6 interrupt controller block diagram phy interrupt gpio0 interrupt gpio0_int_en (int_ctl register) rw gpio0_int (int_sts register) 0 to 1 detect sw_int_en (int_ctl register) rw sw_int (int_sts register) phy_int (int_sts register) ro dmac interrupt dmac_int (int_sts register) gpio1 interrupt gpio1_int_en (int_ctl register) rw gpio1_int (int_sts register) gpio2 interrupt gpio2_int_en (int_ctl register) rw gpio2_int (int_sts register) ro irq_int (int_cfg register) ro deassertion timer wake event interrupt wake_int_en (int_ctl register) rw ro wake_int (int_sts register) int_deas[7:0] (int_cfg register) rw ro int_deas_sts (int_cfg register) int_deas_clr (int_cfg register) rw irq_en (int_ctl register) rw irq (pcib) interrupt controller gp timer interrupt rw gpt_int (int_sts register) master bus error interrupt mberr_int_en (int_ctl register) rw slave bus error interrupt sberr_int_en (int_ctl register) rw mberr_int (int_sts register) sberr_int (int_sts register) gpt_int_en (int_ctl register) phy_int_en (int_ctl register) rw
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 30 smsc lan9420/lan9420i datasheet write of '1' to the corresponding status bit in the int_sts register. the remaining interrupts are cleared from the source csr. the interrupt controller receiv es the wake event detection in terrupt (wake_int) from the wake detection logic. if enabled, the wake detection logi c is able to generate an interrupt to the pci bridge on detection of a mac wakeup event (wakeup frame or magic packet), or on an ethernet link status change (energy detect). note: lan9420/lan9420i can optionally generate a pci in terrupt in addition to assertion of npme on detection of a power management event. gene ration of a pci interrupt is not the typical usage. unlike the other interrupt sources, the software in terrupt (sw_int) is asserted on a 0-to-1 transition of its enable bit (sw_int_en). the dmac interrupt is enabled in the dma controller. all other interrupts are enabled through the int_en register. setting an enable bit high enables the corresponding interrupt as a source of the irq. the interrupt controller contains an interrupt de-as sertion timer. this timer guarantees a minimum interrupt de-assertion period for the irq. the de- assertion timer has a resolution of 10us and is programmable through the int_cfg scsr (refer to section 4.2.4, "interrupt configuration register (int_cfg)," on page 92 ). a setting of all zeros disables t he de-assertion timer. the state of the interrupt de-assertion time r is reflected by the interrupt de-a ssertion timer status bit (int_deas_sts) bit in the irq_cfg register. when this bit is set, the de-assertion timer is currently in a de-assertion interval, and, with the except ion of the wake_int, all pen ding interrupts are blocked. note: the interrupt de-assertion timer does not affect wake_int. this interrupt event is able to assert irq regardless of the st ate of the de-assertion timer. the irq_int status bit in the int_cfg register refl ects the aggregate status of all interrupt sources. if this status bit is set, one or more enabled inte rrupts are active. the irq_int status bit is not affected by the de-assertion timer. the irq output is enabled/disabled by the irq_en en able bit in the int_ctl register. when this bit is cleared, with the exception of wake_int, all in terrupts to the pci bridge are disabled. when set, interrupts to the pci bridge are enabled. note: the irq_en does not affect wake_int. this inte rrupt event is able to assert irq regardless of the state of irq_en. 3.3.2 wake event detection logic lan9420/lan9420i supports the ability to generate wake interrupts on detection of a magic packet, wakeup frame or ethernet link st atus change (energy detect). when enabled to do so, the wake event detection logic generates an interrupt to the interrupt controller. refer to section 3.7.6, "detecting power management events," on page 81 for more information on the wake event interrupt. wakeup frame detection must be enabled in the ma c before detection can occur. likewise, the energy detect interrupt must be enabled in the phy before this interrupt can be used. 3.3.3 general purpose timer (gpt) the general purpose timer is a programmable devic e that can be used to generate periodic system interrupts. the resolution of this timer is 100us. the gp timer loads the gpt_cnt register with the value in the gpt_load field and begins counting when the timer_en bit is asserted (1). on a ch ip-level reset, or when the timer_en bit changes from asserted (1) to de-asserted (0), the gpt_ load field is initialized to ffffh. the gpt_cnt register is also initialized to ffffh on a reset. software can write the pre-load value into the gpt_load field at any time (e.g., before or afte r the timer_en bit is asserted). the gpt enable bit timer_en is located in the gpt_cfg register.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 31 revision 1.6 (07-18-11) datasheet once enabled, the gpt counts down either until it reaches 0000h, or until a new pre-load value is written to the gpt_load field. at 0000h, the counter wraps around to ffffh, asserts the gpt interrupt status bit (gpt_int) and the gpt interr upt (if the gpt_int_en bit is set), and continues counting. gpt_int is a sticky bit (r/wc), once the gpt_int bit is asserted, it can only be cleared by writing a '1' to the bit. the gpt_int hardware interrupt can only be asserted if the gpt_int_en bit is set. 3.3.4 free-run counter (frc) the frc is a simple 32-bit up counter. the frc coun ts at fixed rate of 6.25mhz (160ns resolution). when the frc reaches a value of ffff_ffffh, it wraps around to 0000_0000h and continues counting. the frc is operational in all power states. the frc has no fixed function in lan9420/lan9420i and is ideal for use by drivers as a timebase. the current frc count is readable in free_run scsr. please refer to section 4.2.10, "free run co unter (free_run)," on page 99 for more information on this register. 3.3.5 eeprom controller (epc) lan9420/lan9420i may use an optional, external, eeprom to store the default values for the mac address, pci subsystem id, and pci subsystem vendor id. th e pci subsystem id and pci subsystem vendor id are used by the pci bridge (pcib). the mac ad dress is used as the default ethernet mac address and is loaded into the mac?s addrh and addrl registers. if a properly configured eeprom is not detected, it is the respon sibility of the host lan driver to set the ieee addresses. after a system-level reset occurs, lan9420/lan9420i will load the default values from a properly configured eeprom. lan9420/lan9420i will not accept pci target trans actions until this process is completed. the lan9420/lan94 20i eeprom controller also a llows the host system to read, write and erase the contents of the serial eeprom . the eeprom controller suppor ts most ?93c46? type eeproms configured for 128 x 8-bit operation. 3.3.5.1 eeprom format table 3.2 illustrates the format in which da ta is stored inside of the eeprom. table 3.2 eeprom format eeprom byte address eeprom contents 0 0xa5 1 mac address [7:0] 2 mac address [15:8] 3 mac address [23:16] 4 mac address [32:24] 5 mac address [39:33] 6 mac address [47:40] 7 subsystem device id [7:0] 8 subsystem device id [15:8]
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 32 smsc lan9420/lan9420i datasheet note: eeprom byte addresses past 0ah can be used to store data for any purpose. the signature value of 0xa5 is stored at address 0. a different signature value indicates to the eeprom controller that no eeprom or an un-progra mmed eeprom is attached to lan9420/lan9420i. in this case, following default values are used for the subsystem device id (ssid), subsystem vendor id (ssvid), and the mac address. 3.3.5.2 mac address, subsystem id, and subsystem vendor id auto-load on a system-level reset, the eeprom controller atte mpts to read the first byte of data from the eeprom (address 00h). if the value a5h is read from the first address, then the eeprom controller will assume that an external eeprom is presen t. the eeprom controller will then access the next eeprom byte and send it to the mac address register byte 0 (addrl[7:0]). this process will be repeated for the next five bytes of the mac addre ss, thus fully programming the 48-bit mac address. the subsystem id and subsystem vendor id are si milarly extracted from the eeprom and are used to set the value of the analogous pci header registers contained within the pcib. once all eleven bytes have been programmed, the ?eeprom loaded? bi t is set in the e2p_cmd register. a detailed explanation of the eeprom byte ordering wit h respect to the mac address is given in section 4.4.3, "mac address low register (addrl)," on page 125 . if an 0xa5h is not read from the first address, th e eeprom controller will end in itialization. the default values, as specified in ta b l e 3 . 3 , will then be assumed by the associated registers. it is then the responsibility of the host lan driver software to set the ieee address by writing to the mac?s addrh and addrl registers. 3.3.5.3 eeprom ho st operations after the eeprom controller has finished reading (or attempting to read) the eeprom after a system- level reset, the host is free to perform other eeprom operations . eeprom operations are performed using the eeprom command (e2p_cmd) and eeprom data (e2p_data) registers. section 4.2.11, "eeprom command register (e2p_cmd)," on page 100 provides an explanatio n of the supported eeprom operations. if the eeprom operation is the ?write location? (write) or ?write all? (wral) commands, the host must first write the desired data into the e2p_data register. the host must then issue the write or wral command using the e2p_cmd register by setting the epc_cmd field appropriately. if the operation is a write, the epc_addr field in e2p_cmd must also be set to the desired location. the command is executed when the host sets the epc_bsy bit high. the completion of the operation is indicated when the epc_bsy bit is cleared. 9 subsystem vend or id [7:0] 0ah subsystem vend or id [15:8] table 3.3 eeprom variable defaults variable default subsystem id [15:0] 0x9420 subsystem vendor id [15:0] 0x1055 mac address [47:0] 0xffff_ffff_ffff table 3.2 eeprom format (continued) eeprom byte address eeprom contents
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 33 revision 1.6 (07-18-11) datasheet if the eeprom operation is the ?read location? (r ead) operation, the host must issue the read command using the e2p_cmd register with the epc_a ddr set to the desired location. the command is executed when the host sets the epc_bsy bit high. the completion of the operation is indicated when the epc_bsy bit is cleared, at which time the data from the eeprom may be read from the e2p_data register. other eeprom operations are pe rformed by writing the appropriate command to the e2p_cmd register. the command is executed when the host sets the epc_bsy bi t high. the completion of the operation is indicated when the epc _bsy bit is cleared. in all cases, the host must wait for epc_bsy to clear before modifying the e2p_cmd register. note: the eeprom device powers-up in the erase/write disabled state. to modify the contents of the eeprom, the host must fi rst issue the ewen command. if an operation is attempted, and an eeprom device does not respond within 30ms, lan9420/lan9420i will timeout, and the epc time-out bit (epc_to) in the e2p_cmd register will be set. figure 3.7 illustrates the host accesse s required to perform an eeprom read or write operation. the host can disable the eeprom interface through the gpio_cfg register. when the interface is disabled, the eedio and eclk signals can be used as general-purpose outputs, or they may be used to monitor internal mii signals. figure 3.7 eeprom ac cess flow diagram idle write data register write command register read command register idle write command register read command register read data register busy bit = 0 busy bit = 0 eeprom write eeprom read
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 34 smsc lan9420/lan9420i datasheet 3.3.5.3.1 supported eeprom operations the eeprom controller supports the following eeprom operations under host control via the e2p_cmd register. the operations are commonly supported by ?93c46? eeprom devices. a description and functional timing diagram is provided below for each operation. please refer to the e2p_cmd register description in section 4.2.11, "eeprom command register (e2p_cmd)," on page 100 for e2p_cmd field settings for each command. erase (erase location): if erase/write operations are enabled in the eeprom, this command will erase the location selected by the epc address fi eld (epc_addr). the epc_to bit is set if the eeprom does not respond within 30ms. eral (erase all): if erase/write operations are enabled in the eeprom, this command will initiate a bulk erase of the entire eeprom .the epc_to bit is set if the eeprom does not respond within 30ms. figure 3.8 eeprom erase cycle figure 3.9 eeprom eral cycle 1 eeclk eedio (input) eedio (output) eecs 11 a6 a0 t csl 0 eeclk eedio (input) eedio (output) eecs 10 10 t csl
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 35 revision 1.6 (07-18-11) datasheet ewds (erase/write disable): after issued, the eeprom will ignore erase and write commands. to re-enable erase/write operatio ns issue the ewen command. ewen (erase/write enable): enables the eeprom for erase and write operat ions. the eeprom will allow erase and write operations until the ?era se/write disable? command is sent, or until power is cycled. note: the eeprom device will power-up in the erase/ write-disabled state. any erase or write operations will fail until an eras e/write enable command is issued. figure 3.10 eeprom ewds cycle figure 3.11 eeprom ewen cycle 0 eeclk eedio (input) eedio (output) eecs 10 00 t csl 0 eeclk eedio (input) eedio (output) eecs 10 11 t csl
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 36 smsc lan9420/lan9420i datasheet read (read location): this command will cause a read of the eeprom location pointed to by epc address (epc_addr). the result of the read is available in the e2p_data register. write (write location): if erase/write operatio ns are enabled in the eeprom, this command will cause the contents of the e2p_data register to be writ ten to the eeprom loca tion selected by the epc address field (epc_addr). the epc_to bit is set if the eeprom does not respond within 30ms. figure 3.12 eeprom read cycle figure 3.13 eeprom write cycle 1 10 a6 eecs eeclk eedio (output) a0 d7 d0 eedio (input) t csl 0 eeclk eedio (input) eedio (output) eecs 11 a6 a0 d7 d0 t csl
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 37 revision 1.6 (07-18-11) datasheet wral (write all): if erase/write operations are enabled in the eeprom, this command will cause the contents of the e2p_data register to be written to every eepr om memory location. the epc_to bit is set if the eeprom does not respond within 30ms. table 3.4, "required eeclk cycles" , shown below, shows the number of eeclk cycles required for each eeprom operation. 3.3.5.3.2 host initiated m ac address, ssid, ssvid reload the host can initiate a reload of the mac addre ss, ssid, and ssvid from the eeprom by issuing the reload command via the e2p command (e2p_cmd ) register. if the firs t byte read from the eeprom is not a5h, it is assume d that the eeprom is not presen t, or not programmed, and the reload operation will fail. the ?eeprom loaded ? bit indicates a successf ul reload of the mac address, ssid, and ssvid. 3.3.5.3.3 eeprom command and data registers refer to section 4.2.11, "eeprom command register (e2p_cmd)," on page 100 and section 4.2.12, "eeprom data register (e2p_data)," on page 103 for a detailed description of these registers. supported eeprom operat ions are described in these sections. 3.3.5.3.4 eeprom timing refer to section 5.8, "eeprom timing," on page 166 for detailed eeprom ti ming specifications. figure 3.14 eeprom wral cycle table 3.4 required eeclk cycles operation required eeclk cycles erase 10 eral 10 ewds 10 ewen 10 read 18 write 18 wral 18 0 eeclk eedio (input) eedio (output) eecs 1 d7 d0 0 01 t csl
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 38 smsc lan9420/lan9420i datasheet 3.3.6 system control and status registers (scsr) please refer to section 4.2, "system control and st atus registers (scsr)," on page 87 for a complete description of the scsr. 3.4 dma controller (dmac) the dma controller is designed to transfer data from and to the mac rx and tx data paths. similar to the mac, it contains separate tx and rx data paths that are controlled by a single arbiter. the dma controller includes the following features: ? generic 32-bit dma with single-chann el transmit and receive engines ? optimized for packet-oriented dma transfers with frame delimiters ? supports dual-buffer and linked-list descriptor chaining ? descriptor architecture a llows large blocks of data transfer with minimum host intervention - each descriptor can transfer up to 2kb of data ? comprehensive status reporting for no rmal operation and transfers with errors ? supports programmable interrupt options for different operational conditions ? supports start/stop modes of operation ? selectable round-robin or fixed priority arbitration between receive and transmit engines the dma controller consists of independent transmit (tx) and receive (rx) engines and a control and status register space (dcsr). the transmit engine transfers data from host memory through the pci bridge (pcib) to the mac, while the receive engi ne transfers data from the mac, through the pcib to host memory. the dmac utilizes descriptors to effi ciently move data from source to destination with minimal host intervention. descriptors are 4-dword (16-byte) aligned data structures in host memory that inform the dmac of the location of data bu ffers in host memory and also provide a mechanism for communicating status to the host on comp letion of dma transactions. the dmac has been designed for packet-oriented data transfer, such as frames in ethernet. the dmac can be programmed to assert an interrupt for situations such as fr ame transmit or receive transfer completed, and other normal, as well as error conditions that are described in the dmac control and status registers (dcsr) section. note: descriptors should not cross cache line boundaries if cache memory is used. 3.4.1 dma controller architecture the dma controller has four main hardware com ponents: tx dma engine, rx dma engine, the dma arbiter, and the dcsr. ? tx dma engine - the transmit dma engine fetches transmit descriptors from host memory and handles data transfers from host memory to the mac destination port. ? rx dma engine - the receive dma engine fetches receive descriptors from host memory and handles data transfers from the mac source port to destination buffers in host memory. ? dma arbiter - the dma arbiter controls access to host memory. it can be configured to support round robin or fixed priority arbitration. ? dcsr - the dma control and status register block im plements register bits that control and monitor the operation of the dma subsystem.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 39 revision 1.6 (07-18-11) datasheet 3.4.2 data descriptors and buffers the dmac and the driver communicate through two data structures: ? dma control and status regist ers (dcsr), as described in section 4.3, "dmac control and status registers (dcsr)," on page 104 . ? descriptor lists and data buffe rs, described in this chapter. the dmac transfers rx data frames to the rx buffers in host memory and transmits data from tx buffers in the host memory. descripto rs that reside in host memory contain pointers to these buffers. there are two dma descriptor lists; one for receive operations and one for transmit operations. the base address of each list is written into the rx_base_addr and tx _base_addr registers, respectively. a descriptor list is forward linked (eithe r implicitly or explicitly ). descriptors are usually placed in the physical memory in an incrementin g and a contiguous addressing scheme. however, the last descriptor may point back to the first entry to create a ring structur e. explicit chaining of descriptors is accomplished by setting the second address chained flag in both receive and transmit descriptors (rch - rdes1[24] and tch - tdes1[24]). each de scriptor's list resides in host memory. each descriptor can point to a maximum of two buffers. this enables the use of two physically addressed, as well as non-contiguous memory buffers. data buffers reside in the host memory space. an ethernet frame can be fragmented across multiple data buffers, but a data buffer cannot contain more than one ethernet frame. data chaining refers to ethernet frames that span multiple data buffers. data buffers contain only data used in the ethernet frame. the buffer status is maintained in the desc riptor. in a ring structure, each descriptor can point to up to two data buffers with the restriction that both buffers contain data fo r the same ethernet frame. in a chain structure, each descriptor points to a single data buffer and to the next descriptor in the chain. the dmac will skip to the next frame buffer when end of frame is detected. data chaining can be enabled or disabled. the ring and chain ty pe descriptor structures are illustrated in figure 3.15 . note: descriptors of zero buffer length are not supported at the initial and final descriptors of a chain.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 40 smsc lan9420/lan9420i datasheet figure 3.15 ring and chain descriptor structures descriptor 0 buffer 1 buffer 2 descriptor 1 buffer 1 buffer 2 descriptor n buffer 1 buffer 2 ring structure: descriptor 0 buffer 1 descriptor 1 buffer 1 next descriptor chain structure:
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 41 revision 1.6 (07-18-11) datasheet 3.4.2.1 receive descriptors the receive descriptors must be 4-dword (16-byte ) aligned. except for th e case where descriptor address chaining is disabled (rch=0), there are no a lignment restrictions on receive buffer addresses. providing two buffers, two byte-count buffers, and two address pointers in each descriptor facilitates compatibility with various type s of memory-mana gement schemes. figure 3.16 shows the receive descriptor. receive descriptor 0 (rdes0) rdes0 contains the received frame status, the fram e length, and the descripto r ownership information. figure 3.16 receive descriptor table 3.5 rdes0 bit fields bits description 31 own - own bit when set, indicates that the descriptor block and associated buffer(s) are owned by the dma controller. when reset, in dicates that the descriptor block a nd associated buffer(s) are owned by the host system. host actions: checks this bit to determi ne ownership of the descr iptor block and associated buffer(s). the host sets this bit to pass owne rship to the dmac. the host does not modify a descriptor block or access its associated buffer(s) until this bit is cleared by dmac or until the dmac is in stopped state, whichever comes first. dmac actions: reads this bit to determine ownership of the descriptor block and its associated buffer(s). the dmac clears this bit either wh en it completes the fram e reception or when the buffers that are associated with this descriptor are full. by clearing this bit, the dmac closes the descriptor block and passes ownership to the host. if the dmac fetches a descriptor with the own bit cleared, the dmac state machine enters the suspended state. 30 ff - filter fail indicates that the current frame failed the receive address filter ing. this bit can only be set when receive all (rxall) is set in the mac control regi ster (mac_cr). this bit is only valid when the last descriptor (ls) bit is set and the received frame is greater than or equal to 64 bytes in length. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. rdes1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rdes2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ow fl reserved rdes0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rdes3 ff es de le rf mf fs ls tl cs ft rw me db ce r re rc res rbs2 rbs1 buffer 1 address pointer buffer 2 address pointer r
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 42 smsc lan9420/lan9420i datasheet 29:16 fl - frame length indicates the length in bytes, including the crc, of the received frame that was transferred to host memory. this field is set only after the last descriptor (ls) bit is set and the descriptor error (de) is reset. host actions: reads this field to determine frame length. dmac actions: initializes this field to define frame length. 15 es - error summary indicates the logical or of the following rdes0 bits: rdes0[1] - crc error rdes0[6] - collision seen rdes0[7] - frame too long rdes0[11] - runt frame rdes0[14] - descriptor error host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 14 de - descriptor error when set, indicates a frame truncation caused by a frame that does not fit within the current descriptor buffers, and that the dma controller does not own the next descriptor. the frame is truncated. this field is set only after the last descriptor (ls) bit is set. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 13 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads and cleared on writes. 12 le - length error when set, this bit indicates that the actual le ngth does not match with t he length/type field of the incoming frame. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 11 rf - runt frame when set, this bit indicates that frame was pr ematurely terminated before the collision window (64 bytes). runt frames are passed on to the host memory only if the pass bad frames bit (pass_bad) in the mac control register (mac_cr) is set. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 10 mf - multicast frame when set, this bit indicates that t he received frame has a multicast address. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 9 fs - first descriptor when set, indicates that this descriptor contains the first buffer of a frame. if the size of the first buffer is 0, the second buffer contains the beginning of the frame. if the size of the second buffer is also 0, the second descriptor contains the beginning of the frame. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 8 ls - last descriptor when set, indicates that the buffers pointed to by this descriptor are the last buffers of the frame. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. table 3.5 rdes0 bit fields (continued) bits description
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 43 revision 1.6 (07-18-11) datasheet 7 tl - frame too long when set, indicates the frame length exceeds maximum ethernet-specified size of 1518 bytes (or 1522 bytes when vlan tagging is enabled). this bit is valid only when last descriptor (ls) is set. frame too long is only a frame length indi cation and does not cause any frame truncation. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 6 cs - collision seen when set, this bit indicates that the frame has seen a collision after the collision window. this indicates that a late collision has occurred. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 5 ft - frame type when set, indicates that the frame is an ethernet -type frame (frame length field is greater than or equal to 1536 bytes). when clear, indicates that the frame is an ieee 802.3 frame. this bit is not valid for runt frames of less than 14 bytes. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 4 rw ? receive watchdog when set, indicates that the receive watchdog timer expired while receiving the current packet with length greater than 2048 bytes through 2560 bytes. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 3 me - mii error when set, this bit indicates that a receive er ror was detected during frame reception (rx_er asserted on internal mii bus). host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 2 db - dribbling bit when set, indicates that the frame contained a noninteger multiple of 8 bits. this error is reported only if the number of dribbling bits in the last byte is 4 in mii operating mode, or at least 3 in 10 mb/s serial operating mode. this bit is not valid if collision seen (cs - rdes0[6]) is set. if set, and the crc error (ce - rdes0[1]) is reset, then the packet is valid. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 1 ce - crc error when set, indicates that a cyclic redundancy ch eck (crc) error occurred on the received frame. this bit is also set when the mii error signal is asserted during the reception of a receive packet even though the crc may be correct. this bit is not valid if one of the following conditions exist: ? the received frame is a runt frame ? a collision occurred while t he packet was being received ? a watchdog timeout occurred while the packet was being received host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 0 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads and cleared on writes. table 3.5 rdes0 bit fields (continued) bits description
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 44 smsc lan9420/lan9420i datasheet receive descriptor 1 (rdes1) receive descriptor 2 (rdes2) table 3.6 rdes1 bit fields bits description 31:26 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads. dmac does not write to rdes1. 25 rer - receive end of ring when set, indicates that the dmac reached the fi nal descriptor. upon servicing this descriptor, the dmac returns to the base address of the dma descriptor list pointed to by the receive list base address register (rx_base_addr) . host actions: initializes this bit. dmac actions: reads this bit to determine if this is the final descriptor in the ring. 24 rch - second ad dress chained when set, indicates that the second address in the descriptor is the ne xt descriptor address, rather than the second buffer address. when rch is set, rbs2 (rdes1[21:11]) must be all zeros. rch is ignored if rer (rdes1[25]) is set. host actions: initializes this bit. dmac actions: reads this bit to determine if second address is next descriptor address. 23:22 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads. dmac does not write to rdes1. 21:11 rbs2 - receive buffer 2 size indicates the size, in bytes, of the second data buffer. the buffer size must be a multiple of 4. this field is not valid if rch (rdes1[24]) is set. host actions: initializes this field. dmac actions: reads this field to determine the allocated size of associated data buffer. 10:0 rbs1 - receive buffer 1 size indicates the size, in bytes, of the first data buffer. the buffer size must be a multiple of 4. in the case the buffer size is not a multiple of 4, the resulting behavior is undefined. if this field is 0, the dma controller ignores this buffer and uses buffer2. (this field cannot be zero if the descriptor chaining is used ? second ad dress chained (rch - rdes1[24]) is set). host actions: initializes this field. dmac actions: reads this field to determine the allocated size of associated data buffer. table 3.7 rdes2 bit fields bits description 31:0 buffer 1 address pointer indicates the address of buffer 1 in the host memory. there are no limitations on the buffer address alignment. host actions: initializes this field. dmac actions: reads this field upon opening a new dma descriptor to obtain the buffer address.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 45 revision 1.6 (07-18-11) datasheet receive descriptor 3 (rdes3) 3.4.2.2 transmit descriptors the descriptors must be 4-dword (16-byte) aligned, while there are no alignment restrictions on transmit buffer addresses. providing two buffers, two byte-count buffers, and two address pointers in each descriptor facili tates compatibility with various types of memo ry-management schemes. figure 3.17 shows the transmit descriptor format. table 3.8 rdes3 bit fields bits description 31:0 buffer 2 address pointer (next descriptor address) the rch (second address chained) bit (rdes1[24]) determines the usage of this field as follows: rch is zero : this field contains the pointer to the addr ess of buffer 2 in host memory. the buffer must be dword (32-bit) aligned (rdes3[1:0] = 00b). in the case where the buffer is not dword aligned, the resulting behavior is undefined. rch is one : descriptor chaining is in use and this field contains the pointer to the next descriptor in host memory. the descriptor must be 4-dwo rd (16-byte) aligned (rdes3[3:0] = 0000b). in the case where the buffer is not 4-dword a ligned, the resulting behavior is undefined. note: if rer (rdes1[25]) is set, rch is ignored and this field is treated as a pointer to buffer 2 as in the ? rch is zero ? case above. host actions: initializes this field. dmac actions: reads this field upon opening a new dma descriptor to obtain the buffer address. figure 3.17 transmit descriptor tdes1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tdes2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ow tdes0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tdes3 buffer 1 addr ess pointer buffer 2 addr ess pointer reserved es res lc nc lt ec hf cc ed ue de ic ls fs r ac te tc dp r tbs2 tbs1 ck
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 46 smsc lan9420/lan9420i datasheet transmit descriptor 0 (tdes0) tdes0 contains the transmitted frame status and the descriptor ownership information. table 3.9 tdes0 bit fields bits description 31 own - own bit when set, indicates that the descriptor block and associated buffer(s) are owned by the dma controller. when reset, in dicates that the descriptor block and associated buffer(s) are owned by the host system. host actions: checks this bit to determine ownership of the descri ptor block and associated buffer(s). the host sets this bit to pass owner ship to the dmac. the host does not modify a descriptor block or access its asso ciated buffer(s) until this bit is cleared by dmac or until the dmac is in stopped state, whichever comes first. the ownership bit of th e first descriptor of the frame should be set after all subsequent descripto rs belonging to the same frame have been set. this avoids a possible race condition between the dma controller fetching a descriptor and the host setting an ownership bit. dmac actions: reads this bit to determine ownership of the descriptor block and its associated buffer(s). the dmac clears this bit either when it completes the frame transmission or when the buffers that are associated with this descriptor are empty. by clearin g this bit, the dmac closes the descriptor block and passes ownership to the host . if the dmac fetches a descriptor with the own bit cleared, the dmac state machine enters the suspended state. 30:16 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads and cleared on writes. 15 es - error summary indicates the logical or of the following tdes0 bits: tdes0[2] ? excessive deferral tdes0[8] ? excessive collisions tdes0[9] ? late collision tdes0[10] ? no carrier tdes0[11] ? loss of carrier host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 14:12 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads and cleared on writes. 11 lc - loss of carrier when set, indicates loss of carrier during transmission. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 10 nc - no carrier when set, indicates that the carrier signal from the transceiver was not present during transmission. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 9 lt - late collision when set, indicates that the frame transmission was aborted due to collision occurring after the collision window of 64 bytes. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 47 revision 1.6 (07-18-11) datasheet transmit descriptor 1 (tdes1) 8 ec - excessive collision when set, indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 7 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads and cleared on writes. 6:3 cc - collision count this 4-bit counter indicates the number of collisions that occurred before the frame was transmitted. not valid when the excessive collisions bit (ec - tdes0[8]) is also set. host actions: reads this field to determine collision count. dmac actions: initializes this field to define collision count. 2 ed - excessive deferral if the deferred bit is set in the control register, the setting of the excessive deferral bit indicates that the transmission has ended be cause of deferral of over 24, 288-bit times during transmission. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. 1 reserved 0 de - deferred when set, indicates that the dma controller had to defer while ready to transmit a frame because the carrier was asserted. host actions: checks this bit to determine status. dmac actions: sets/clears this bit to define status. table 3.10 tdes1 bit fields bits description 31 ic - interrupt on completion when set, the dma controller sets transmit interrupt (ti - dmac_status[0]) after the present frame has been transmitted. this field is valid only when last segment (ls - tdes1[30]) is set. host actions: initializes this bit. dmac actions: reads this bit to determine whether ioc should be asserted. 30 ls - last segment when set, indicates that the buffer c ontains the last segment of a frame. host actions: initializes this bit. dmac actions: reads this bit to determine whether t he buffer contains the last segment of a frame. table 3.9 tdes0 bit fields (continued) bits description
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 48 smsc lan9420/lan9420i datasheet 29 fs - first segment when set, indicates that the buffer c ontains the first segment of a frame. host actions: initializes this bit. dmac actions: reads this bit to determine whether t he buffer contains the first segment of a frame. 28 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads. dmac does not write to tdes1. 27 ck - tx checksum enable if this bit is set in conjunction with the first segment bit (fs) in tdes1 and the tx checksum offload engine enable bit (tx_coe_en) in the checksum offload engine control register (coe_cr), the tx checksum offload engine (txcoe) will calculat e an l3 checksum for the associated frame. the 16-bit checksum is insert ed in the transmitted data as specified in section 3.5.6, "transmit checksum offload engine (txcoe)," on page 63 . host actions: initializes this bit. dmac actions: reads this bit to determine whether txcoe should be enabled. 26 ac - add crc disable when set, the dma controller does not append the c rc to the end of the transmitted frame. this field is valid only when first segment (fs - tdes1[29]) is set. host actions: initializes this bit. dmac actions: reads this bit to determine whether crc should be appended to the end of the transmitted frame. 25 ter - transmit end of ring when set, indicates that the dmac reached the final descriptor. upon servicing this descriptor, the dmac returns to the base address of the dma descriptor list pointed by the transmit list base address register (tx_base_addr) . host actions: initializes this bit. dmac actions: reads this bit to determine if this is the final descriptor in the ring. 24 tch - second address chained when set, indicates that the second address in the descriptor is the next descriptor address, rather than the second buffer address. when this bit is se t, the tbs2 (tdes1[21:11]) must be all zeros. tch is ignored if ter (tdes1[25]) is set. host actions: initializes this bit. dmac actions: reads this bit to determine if second address is next descriptor address. 23 dpd - disable padding when set, the dma controller does not automatically add a padding field to a packet shorter than 64 bytes. when cleared, the dma controller automatically adds a padding field and also a crc field to a packet shorter than 64 bytes. the crc field is added despite the state of the add crc disable (ac - tdes1[26]) flag. this is valid only when the first segment (fs - tdes1[29]) is set. host actions: initializes this bit. dmac actions: reads this bit to determine if padding is enabled. 22 reserved host actions: cleared on writes and ignored on reads. dmac actions: ignored on reads. dmac does not write to tdes1. 21:11 tbs2 - transmit buffer 2 size indicates the size, in bytes, of the second data buffer. this field is not valid if tch (tdes1[24]) is set. host actions: initializes this field. dmac actions: reads this field to determine the allocated size of associated data buffer. table 3.10 tdes1 bit fields (continued) bits description
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 49 revision 1.6 (07-18-11) datasheet transmit descriptor 2 (tdes2) transmit descriptor 3 (tdes3) 10:0 tbs1 - transmit buffer 1 size indicates the size, in bytes, of the first data buffer . if this field is 0, the dma controller ignores this buffer and uses buffer2. host actions: initializes this field. dmac actions: reads this field to determine the allocated size of associated data buffer. table 3.11 tdes2 bit fields bits description 31:0 buffer 1 address pointer this is the physical address of buffer 1. there are no limitations on the buffer address alignment. host actions: initializes this field. dmac actions: reads this field upon opening a new dma descriptor to obtain the buffer address. table 3.12 tdes3 bit fields bits description 31:0 buffer 2 address pointer (next descriptor address) the tch (second address chained) bit (tdes1[24]) determines the usage of this field as follows: tch is zero : this field contains the pointer to the address of buffer 2 in host memory. there are no limitations on buffer address alignment. tch is one : descriptor chaining is in use and this field contains the pointer to the next descriptor in host memory. the descriptor must be 4-dword (16-byte) aligned (tdes3[3:0] = 0000b). in the case where the buffer is not 4-dword aligned, the resulting behavior is undefined. note: if ter (tdes1[25]) is set, tch is ignored and this field is treated as a pointer to buffer 2 as in the ? tch is zero ? case above. host actions: initializes this field. dmac actions: reads this field upon opening a new dma descriptor to obtain the buffer address. table 3.10 tdes1 bit fields (continued) bits description
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 50 smsc lan9420/lan9420i datasheet 3.4.3 initialization the following sequence explains the initialization steps for the dma controller and activation of the receive and transmit paths: 1. configure the bus_mode register. 2. mask unnecessary interrupts by writ ing to the dmac_intr_ena register. 3. software driver writes to descriptor base address registers rx_base_addr and tx_base_addr after the rx and tx descriptor lists are created. 4. write dmac_control to set bits 13 (st) and 1 (sr) to start the tx and rx dma. the tx and rx engines enter the running state and attempt to acquire descriptors from the respective descriptor lists. the receive and transmit engines begin processing receive and transmit operations. 5. set bit 2 (rxen) of mac_cr to turn the receiver on. 6. set bit 3 (txen) of mac_cr to turn the transmitter on. note: the tx and rx processes and paths are inde pendent of each other and can be started or stopped independently of one another. however, the control sequence required to activate the rx path must be followed explicitly. the rx dmac should be activated before the mac?s receiver. failure to do so may lead to unpredictable results and untoward operation. 3.4.4 transmit operation transmission proceeds as follows: 1. the host system sets up the transmit descripto r (tdes0-3) and sets t he own bit (tdes0[31]). 2. once set to the running state, the dma controller reads the host memory buffer to collect the first descriptor. the starting address of the first desc riptor is read from the tx_base_addr register. 3. data transfer begins, and contin ues until the last dword of the fr ame is transferred. a frame may traverse multiple descriptors. fr ames must be delimited by the first segment (fs - tdes1[29]) and last segment (ls - td es1[30]) respectively. 4. when the frame transmission is completed, status is written into tdes0 with the own bit reset to 0. if the dmac detects a descriptor flag that is ow ned by the host, or if an error condition occurs, the transmit engine enters into the suspended state and both (tu) transmit buffer unavailable and (nis) normal interrupt summary bits are set. tran smit interrupt (ti) is set after completing transmission of a frame that has an interrupt, and on completion the last descriptor (tdes0[30]) is set. a new frame transmission will move the dma from the suspended state. 3.4.5 receive operation the general sequence of events for rec eption of a frame is as follows: 1. the host system sets up the re ceive descriptors rdes0-3 and sets the own bit ( rdes0[31]). the host system polls the own bit and, once it recognizes a descriptor for itself, it can begin working on the descriptor. 2. once set to the running state, the dma controller reads the host memory buffer to collect the first descriptor. the starting address of the first descriptor is read from the rx_base_addr register. 3. data transfer begins, and contin ues until the last dword of the fr ame is transferred. a frame may traverse multiple descriptors. the dma controller delimits the frames by setting the first segment (rdes0[9]) and last segment (rdes0[8]) respecti vely. as a buffer is filled, or when the last segment is transferred to the host memory buffer, the descriptor of that buffer is closed (own bit is cleared). 4. when a frame transfer is completed, the status field in rdes0 of the last descriptor is updated and the own bit reset to 0, and the receive interrupt (ri) is then set. the receive engine continues
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 51 revision 1.6 (07-18-11) datasheet to fetch the next descriptor and repeat the pr ocess unless it encounters a descriptor marked as being owned by the host system. if this occurs, the receive buffer unavailable bit (ru) is set and the receive engine enters the suspended state. if a new frame arrives while the receive engine is in the suspended state, the dma controller re-fetches the current descriptor. if the descriptor is now owned by the dmac, the receive process continues. if the descriptor is still owned by the host system, the frame is discarded and dmac re-enter s the suspend state. this process is repeated for each received frame. 5. the reception of a new frame will move the rx engine from the suspend state. note: oversized rx packets must not cross from one buffer to another unless either the starting address of the 2nd buffer is dword aligned, or the oversized packet is to be discarded. 3.4.6 receive descriptor acquisition the receive engine always attempts to acquire an extra descriptor in the anticipation of an incoming frame. descriptor acquisition is attempted if any of the following conditions are satisfied: ? when the (sr) start/stop receive bit (bit 1 of dmac_control) sets immediately after being placed in the running state ? when the memory buffer ends before the frame ends for the current transfer ? when the controller completes the reception of a fr ame and the current receive descriptor has been closed ? when the receive process is suspended because of a host-owned buffer (rdes0[31]=0) and a new frame is being received ? when receive poll demand is issued 3.4.7 suspend state behavior the following sections detail the suspend state behavior of the transmit and receive engines. 3.4.7.1 transmit engine the transmit engine enters the suspended stat e when either of thes e conditions occurs: ? the dma controller detects a descr iptor owned by the host system (tdes0[31]=0). to resume, the driver must give the descriptor ownership to the dma controller and then issue a poll demand command. ? a dma transmission was aborted due to a local error. in both of these cases the abnormal interrupt su mmary (ais bit in the dm ac_status register) and the transmit interrupt (ti bit in the dmac_status register) are set and the appropriate status bit in tdes0 is set. the position in the transmit list is retained. the retained position is that of the descriptor following the descriptor that was last closed. note: the dma controller does not automatically poll th e transmit descriptor list. the driver must explicitly issue a transmit poll demand after rectifying the suspension cause. 3.4.7.2 receive engine the receive engine enters the suspended state when a re ceive buffer is unavailable. if a frame arrives when the receiver is in the suspended state, the re ceive engine re-fetches the descriptor and, if now owned by the dma controller, reenters the running state and starts frame reception. receive polling resumes from the last list position. the dma c ontroller generates a receive buffer unavailable interrupt (ru bit in the dmac_status register) on ly once - when entering the suspended state from the running state. in the suspended state, if a new frame is received and a descriptor is still not available, the frame is discarded. only in the suspended state does the controller respond to a receive
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 52 smsc lan9420/lan9420i datasheet poll demand (for example, a buffer is available be fore the next incoming frame) and enter the running state. 3.4.8 stopping transmission and reception the receive and transmit processes and paths are independent of each other. one does not need to be stopped as a result of stoppi ng the other. however, the sequence of operations required to stop elements in the receive path must be explicitly fo llowed, in order to preclude unexpected results and untoward operation. in order to stop the transmission, the tx dmac should be stopped before the mac?s transmitter (clear bit 13 (st) of dmac_control to stop tx dma, then clear bit 3 (txen) of mac_cr to turn the transmitter off). in order to stop reception, the mac?s receiver shou ld be stopped prior to stopping the rx dmac (clear bit 2 (rxen) of mac_cr to turn the receiver off, then clear bit 1 (sr) of dmac_control to stop rx dma). performing these steps in the reve rse order will result in rx dma not stopping (dmac_status will continue to show the receiv e process state (rs) as running and receive process stopped (rps) does not assert). 3.4.9 tx buffer fragmentation rules transmit buffers must adhere to the following rules: ? each buffer can start and end on any arbitrary byte alignment ? the first buffer of any transmit packet can be any length ? middle buffers (i.e., those with first segment = la st segment = 0) must be greater than, or equal to 4 bytes in length ? the final buffer of any transmit packet can be any length additionally, the mil operates in store-and-forward mode and has specific rules with respect to fragmented packets. the total space consumed in th e tx fifo (mil) must be limited to no more than 2kb - 3 dwords (2,036 bytes total). any transmit pa cket that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to lan9420/lan9420i. one approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2, 036 bytes. another approach is to check the number of buffers against a worst-case limit of 86 (see explanation below). 3.4.9.1 calculating worst-ca se tx fifo (mil) usage the actual space consumed by a buffer in the mil tx fifo consists of any partial dword offsets in the first/last dword of the buffer, plus all of the whole dwords in between. the worst-case overhead for a tx buffer is 6 bytes, which assumes that it started on the high byte of a dword and ended on the low byte of a dword. a tx packet consisting of 86 such fragments would have an overhead of 516 bytes (6 * 86) which, when added to a 1514-byte max-size transmit packet (1516 bytes, rounded up to the next whole dword), would give a total space consumption of 2,032 bytes, leaving 4 bytes to spare; this is the basi s for the "86 fragment" rule mentioned above. 3.4.10 dmac interrupts as described in earlier sections, there are nume rous events that cause a dmac interrupt. the dmac_status register contains all the bits that might cause an interrupt. the dmac_intr_ena register contains an enable bit for each of the events that can cause a dmac interrupt. the dmac interrupt to the interrupt controller is asserted if any of the enabled interrupt conditions are satisfied. there are two groups of interrupts: normal and abnormal (as outlined in dmac_status). interrupts are cleared by writing a logic 1 to the bit. when all the enabled interrupts within a group are cleared,
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 53 revision 1.6 (07-18-11) datasheet the corresponding summary bit is cleared. when both the summary bits are cleared, the dmac interrupt is de-asserted. interrupts are not queued and if a second interrupt event occurs before the driver has responded to the first interrupt, no additional interrupts will be gen erated. for example, receive interrupt (ri bit in the dmac_status register) indicates that one or more frames was transferred to a host memory buffer. the driver must scan all descriptors, from t he last recorded position to the first one owned by the dma controller. an interrupt is generated only once for simultaneous, multiple events. the driver must scan the dmac_status register for the interrupt cause. th e interrupt is not generated again, unless a new interrupting event occurs after the driver has cl eared the appropriate dmac_status bit. for example, the controller generates a receive interrupt (ri) and the driver begins reading dmac_status. next, a receive buffer unavailable (ru) occurs. the driv er clears the receive interrupt. dma_intr gets de- asserted for at least one cycle and then asserted again for the rx buffer unavailable interrupt. 3.4.11 dmac control and status registers (dcsr) please refer section 4.3, "dmac control and status registers (dcsr)," on page 104 to for a complete description of the dcsr. 3.5 10/100 ethernet mac the ethernet media access controller (mac ) provides the following features: ? compliant with the ieee 802. 3 and 802.3u specifications ? supports 10-mbps and 100-mbps data transfer rates ? transmit and receive message data encapsulation ? framing (frame boundary delimitation, frame synchronization) ? error detection (physical medium transmission errors) ? media access management ? medium allocation (collision detectio n, except in full-duplex operation) ? contention resolution (collision handling, except in full-duplex operation) ? decoding of control frames (pause command) and disabling the transmitter ? generation of control frames ? internal mii interface for communication with the embedded phy ? supports virtual local area network (vlan) operations ? supports both full- and half-duplex operations ? support of csma/cd protocol for half-duplex mode ? supports flow control for full-duplex operation ? wake detection logic, which detects wakeup frames and magic packets ? collision detection and auto retransmissi on on collisions in half-duplex mode ? preamble generation and removal ? automatic 32-bit crc generation and checking ? options to insert pad/crc32 on transmit ? options to set auto matic pad stripping in receive packets ? checksum offload engine for calculation of layer 3 transmit and receive checksum
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 54 smsc lan9420/lan9420i datasheet the mac block includes a mac interface layer (mil). the mil provides a fifo interface between the dmac and the mac. the mil pr ovides the following features: ? provides a bridge between the dma controller and ethernet mac ? separate paths for transmit and receive operations ? separate 2kb fifos (one for transmit and one for receive operations) ? receive: sends only filtered packets to dmac ? transmit: supports store and forward mechanism ? transmit: frame data held in mil fifo until the mac retransmits the packets without collision the mac incorporates the essential protocol requirements for operating an ethernet/ieee 802.3- compliant node and provides an interface between the host system and the internal ethernet phy. the mac can operate in either 100-mbps or 10-mbps mode. the mac operates in both half-duplex and full- duplex modes. when operating in half-duplex mode, the mac complies fully with section 4 of iso/iec 8802-3 (ansi/ieee standard) and ansi/ieee 802.3 standards. when operating in full-duplex mode, the mac complies with ieee 802.3x full-duplex operation standard. the mac provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. these features incl ude the ability to disable retries after a collision, dynamic fcs (frame check sequence) generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic retransmission and detection of collision frames, as well as an l3 checksum offload engine for transmit and receive operations. the mac can sustain transmission or reception of minimally-sized ba ck-to-back packets at full line speed with an inter-packet gap (ipg) of 9.6 micr oseconds for 10 mbps and 0.96 microseconds for 100 mbps. the transmit and receive data paths are separate within the mac, allowing the highest performance, especially in full duplex mode. the mac includes a control and status register block (mcsr) through which the mac can be configured and monitored by the host. the mcsr ar e accessible from the ho st system via the target interface of the pcib. on the backend, the mac interfaces with the 10/100 phy through an mii (media independent interface) port which is internal to lan9420/lan9420i. the mcsr also provide a mechanism for accessing the phy?s internal registers through th e internal smi (serial management interface) bus. 3.5.1 flow control the mac supports full-duplex flow control using the pause operation and control frame. 3.5.1.1 full-duplex flow control the pause operation inhibits data transmission of dat a frames for a specified period of time. a pause operation consists of a frame containing the global ly assigned multicast address (01-80-c2-00-00-01), the pause opcode, and a parameter indicating the quantum of slot time (512 bit times) to inhibit data transmissions. the pause parameter may range from 0 to 65,535 slot times. the ethernet mac logic, on receiving a frame with the re served multicast address and paus e opcode, inhibits data frame transmissions for the length of time indicated. if a pause request is re ceived while a transmission is in progress, then the pause will take effect after the transmission is complete. control frames are received and processed by the mac and are passed on. the mac also transmits control frames (pause comma nd) under software control. the software driver requests the mac to transmit a c ontrol frame, and gives the value of the pause time to be used in the control frame, through the mac?s flow regist er. the mac constructs a control frame with the
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 55 revision 1.6 (07-18-11) datasheet appropriate values set in all the different fields (a s defined in the 802.3x s pecification) and transmits the frame (via the phy). the transmission of the co ntrol frame is not affected by the current state of the pause timer value that is set because of a recently received control frame. refer to section 4.4.8, "flow control register (flow)," on page 130 for more information on enabling flow control in the mac. 3.5.2 virtual local area network (vlan) support virtual local area networks or vlans, as defined within the ieee 802.3 standard, provide network administrators one means of group ing nodes within a larger netwo rk into broadcast domains. to implement a vlan, four extra bytes are added to the basic ethernet packet. as shown in figure 3.18 vlan frame on page 55 , the four bytes are inserted after the source address field and before the type/length field. the first two bytes of the vlan tag identify the tag, and by convention are set to the value 8100h. the last two bytes identify the s pecific vlan associated with the packet; they also provide a priority field. the mac supports vlan-tagged packets. the mac pr ovides two registers which are used to identify vlan-tagged packets. one register should normally be set to the conventional vlan id of 8100h. the other register provides a way of identifying vlan frames tagged with a proprietary (not 8100h) identifier. if a packet arrives bearing either of these tags in the two bytes succeeding the source address field, the controller will recognize the packet as a vlan-tagged packet. in this case, the controller increases the maximum allowed packet size from 1518 to 1522 bytes (normally the controller filters packets larger than 1518 bytes). this allo ws the packet to be received, and then processed by the application, or to be transmitted on the network. . figure 3.18 vlan frame preamble (7 bytes) sof (1 byte) dest. addr. (6 bytes) source addr. (6 bytes) type (2 bytes) data (46 - 1500 bytes) fcs (4 bytes) ethernet frame (1518 bytes) preamble (7 bytes) sof (1 byte) dest. addr. (6 bytes) source addr. (6 bytes) type (2 bytes) data (46 - 1500 bytes) fcs (4 bytes) ethernet frame with vlan tag (1522 bytes) tpid (2 bytes) type (2 bytes) tpid (2 bytes) user priority (3 bits) cfi (1 bit) vlan id (12 bits) tag control information (tci) tag protocol d: \x81-00 indicates frame's priority canonical address format indicator vid: 12 bits defining the vlan to which the frame belongs
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 56 smsc lan9420/lan9420i datasheet 3.5.3 address filtering functional description the ethernet address fields of an et hernet packet, consists of two 6-byte fields: one for the destination address and one for the source address. the first bi t of the destination address signifies whether it is a physical address or a multicast address. the address check logic filters the frame based on the ethernet receive filter mode that has been enabled. filter modes are specified based on the state of the control bits in table 3.13, "address filtering modes" , which shows the various filtering modes us ed by the mac. these bits are defined in more detail in section 4.4.1, "mac control register (mac_cr)," on page 120 . if the frame fails the filt er, the mac does not receive the packet. the host has the option of accepting or ignoring the packet. 3.5.3.1 perfect filtering this filtering mode passes only in coming frames whose destination address field exactly matches the value programmed into the mac address high register (refer to section 4.4.2, "mac address high register (addrh)," on page 124 ) and the mac address low register (refer to section 4.4.3, "mac address low register (addrl)," on page 125 ). the mac address is form ed by the concatenation of the above two registers in the mcsr. 3.5.3.2 hash only filtering mode this type of filtering checks for incoming receive packets with either multicast or physical destination addresses, and executes an imperfect addr ess filtering against the hash table. during imperfect hash filtering, the destination address in the incoming frame is passed through the crc logic and the upper six bits of the crc register are used to index the contents of the hash table. the hash table is formed by concatenating the register?s multicast hash table high (refer to section 4.4.4, "multicast hash table hi gh register (hashh)," on page 126 ) and multicast hash table low (refer to section 4.4.5, "multicast hash tabl e low register (hashl)," on page 127 ) in the mcsr to form a 64-bit hash table. the most signifi cant bit of the crc determines t he register to be used (high/low), while the other five bits determine the bit within the register. a value of 00000 selects bit 0 of the table 3.13 address filtering modes mcpas prms invfilt hfil t hpfilt description 0 0 0 0 0 mac address perfect filtering only for all addresses. 0 0 0 0 1 mac address perfect filtering for physical address and hash filtering for multicast addresses 0 0 0 1 1 hash filtering for physical and multicast addresses 0 0 1 0 0 inverse filtering x 1 0 x x promiscuous 1 0 0 0 x pass all multicast frames. frames with physical addresses are perfect-filtered 1 0 0 1 1 pass all multicast frames. frames with physical addresses are hash- filtered
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 57 revision 1.6 (07-18-11) datasheet multicast hash table low register and a value of 11 111 selects bit 31 of the multicast hash table high register. 3.5.3.3 hash perfect filtering in hash perfect filtering, if the received frame is a physical address, the packet filter block perfect-filters the incoming frame?s destination field with the valu e programmed into the mac address high register (refer to section 4.4.2, "mac address hig h register (addrh)," on page 124 ) and the mac address low register (refer to section 4.4.3, "mac address lo w register (addrl)," on page 125 ). if the incoming frame is a multicast frame, however, the packet filter functi on performs an imperfect address filtering against the hash table. the imperfect filtering against the hash table is the same imperfect filter ing process described in section 3.5.3.2 . 3.5.3.4 inverse filtering during inverse filtering, the packet filter block accepts incoming frames wit h a destination address not matching the perfect address (i.e., the value progr ammed into the mac address high register and the mac address low register in the crc block) and re jects frames with destination addresses matching the perfect address. for all filtering modes, when mcpas is set, all mu lticast frames are accept ed. when the prms bit is set, all frames are accepted regardless of their des tination address. this includes all broadcast frames as well. 3.5.4 wakeup frame detection setting the wakeup frame enable bit (wake_en) in the ?wucsr?wakeup control and status register?, places the mac in the wakeup frame dete ction mode. in this mode, normal data reception is disabled, and detection logic within the mac exam ines receive data for the pre-programmed wakeup frame patterns. upon detection of a wake event, t he mac will assert the wake event interrupt to the interrupt controller. in turn, the interrupt controll er can be programmed to assert its interrupt (irq) to the pcib. in reduced power modes, the irq interr upt can be used to generate a wakeup event using the npme signal, which, if enabled to do so, will return the system to its normal operational state (s0 state). the irq interrupt can also be used to generate an interrupt to the host, via the nint signal. upon detection, the wakeup frame received bit (wufr) in the wucsr is set. when the host system clears the wuen bit, the mac will resume normal receive operation. before putting the mac into the wakeup frame detecti on state, the host application must provide the detection logic with a list of sample frames and th eir corresponding byte masks. this information is written into the wakeup frame filter register (wuff). please refer to section 4.4.11, "wakeup frame filter (wuff)," on page 133 for additional information on this register. the mac supports four programmable filters that su pport many different receive packet patterns. if remote wakeup mode is enabled, the remote wakeup function receives all frames addressed to the mac. it then checks each frame against the enabl ed filter and recognizes the frame as a remote wakeup frame if it passes the wakeup frame filter register?s address filtering and crc value match. in order to determine which bytes of the frames should be checked by the crc module, the mac uses a programmable byte mask and a programmable pattern offset for each of the four supported filters. the pattern?s offset defines the location of the firs t byte that should be checke d in the frame. the byte mask is a 31-bit field that specif ies whether or not each of the 31 contiguous bytes within the frame, beginning in the pattern offset, should be checked. if bit j in the byte mask is set, the detection logic checks byte offset + j in the frame. in order to load the wakeup frame filter register , the lan driver software must perform eight writes to the wakeup frame filter register (wuff). ta b l e 3 . 1 4 shows the wakeup frame filter register?s structure.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 58 smsc lan9420/lan9420i datasheet note 3.1 wakeup frame detection can be performed when lan9420/lan9420i is in any power state. wakeup frame detection is enabled when the wuen bit is set. note: when wake-up frame detection is enabled via the wuen bit of the wakeup control and status register (wucsr) , a broadcast wake-up frame will wake -up the device despite the state of the disable broadcast (bcast) bit in the mac control register (mac_cr) . the filter i byte mask defines which incoming fram e bytes filter i will examine to determine whether or not this is a wakeup frame. ta b l e 3 . 1 5 , describes the byte mask?s bit fields. the filter i command register controls filter i operation. ta b l e 3 . 1 6 shows the filter i command register. the filter i offset register defi nes the offset in the frame?s desti nation address field from which the frames are examined by filter i. ta b l e 3 . 1 7 describes the filter i offset bit fields. table 3.14 wakeup frame filter register structure filter 0 byte mask filter 1 byte mask filter 2 byte mask filter 3 byte mask reserved filter 3 command reserved filter 2 command reserved filter 1 command reserved filter 0 command filter 3 offset filter 2 offset filter 1offset filter 0 offset filter 1 crc-16 filter 0 crc-16 filter 3 crc-16 filter 2 crc-16 table 3.15 filter i byte mask bit definitions filter i byte mask description bits description 31 reserved 30:0 byte mask: if bit j of the byte mask is set, the crc machine processes byte pattern-offset + j of the incoming frame. otherwise, byte pattern-offset + j is ignored. table 3.16 filter i command bit definitions filter i commands bits description 3 address type: defines the destination address type of the pattern. when bit is set, the pattern applies only to multicast frames. when bit is cl eared, the pattern applies only to unicast frames. 2:1 reserved 0 enable filter: when bit is set, filter i is enabled, otherwise, filter i is disabled.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 59 revision 1.6 (07-18-11) datasheet the filter i crc-16 register cont ains the crc-16 result of the fr ame that should pass filter i. table 3.18 describes the filter i crc-16 bit fields. table 3.19 indicates the cases that produce a wake when the wakeup frame enable (wake_en) bit of the wakeup control and status register (wucsr) is set. all other cases do not generate a wake. note 3.2 as determined by bit 0 of filter i command. note 3.3 crc matches filter i crc-16 field. note 3.4 as determined by bit 9 of wucsr. note 3.5 as determined by bit 2 of filter i command. note: x indicates ?don?t care?. table 3.17 filter i offset bit definitions filter i offset description bits description 7:0 pattern offset: the offset of the first byte in the frame on which crc is checked for wakeup frame recognition. the mac checks the first offset byte of the frame for crc and checks to determine whether the frame is a wakeup frame. offset 0 is the first byte of the incoming frame's destination address. table 3.18 filter i crc -16 bit definitions filter i crc-16 description bits description 15:0 pattern crc-16: this field contains the 16-bit crc value from the pattern and the byte mask programmed to the wakeup filter register functi on. this value is compared against the crc calculated on the incoming frame, and a matc h indicates the reception of a wakeup frame. table 3.19 wakeup generation cases filter enabled ( note 3.2 ) crc match ( note 3.3 ) global unicast enabled ( note 3.4 ) pass regular receive filter address type ( note 3.5 ) broad- cast frame multi- cast frame unicast frame yes yes x x x yes no no yes yes yes x x no no yes yes yes x yes multicast (=1) no yes no yes yes x yes unicast (=0) no no yes
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 60 smsc lan9420/lan9420i datasheet 3.5.4.1 magic packet detection setting the magic packet enable bit (mpen) in the section 4.4.12, "wakeup control and status register (wucsr)," on page 134 , places the mac in the ?magic pa cket? detection mode. in this mode, normal data reception is disabled, and detection logic within the mac examines receive data for a magic packet. the mac can be programmed to assert the wake event interrupt to the interrupt controller on detection. upon detection, the magi c packet received bit (mpr) in the wucsr is set. when the host clears the mpen bit, normal re ceive operation will resume. please refer to section 4.4.12, "wakeup control and status register (wucsr)," on page 134 for additional information on this register in magic packet mode, logic within the mac constant ly monitors each frame addressed to the node for a specific magic packet pattern. it checks only packets with the mac?s address or a broadcast address to meet the magic packet requirement. the mac checks each received frame for the pattern 48?hff_ff_ff_ff_ff_ff after the destination and source address field. then the mac inspects the frame for 16 repetit ions of the mac address without any breaks or interruptions. in case of a break in the 16 address repetitions, the mac scans for the 48'hff_ff_ff_ff_ff_ff pattern again in the incoming frame. the 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. the device will also accept a multicast frame, as l ong as it detects the 16 duplications of the mac address. if the mac address of a node is 00h 11h 22h 33h 44h 55h, then the mac scans for the following data sequence in an ethernet frame: destination address source ad dress ?????ff ff ff ff ff ff 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 ?crc it should be noted that magic packet detectio n can be performed when lan9420/lan9420i is in any power management state. 3.5.5 receive checksum offload engine (rxcoe) the receive checksum offload engine (rxcoe) provides assistance to the host by calculating a 16- bit checksum for a received ethernet frame. the rxcoe readil y supports the following ieee802.3 frame formats: ? type ii ethernet frames ? snap encapsulated frames ? support for up to 2, 802.1q vlan tags the resulting checksum value can also be modified by software to support other frame formats. the rxcoe has two modes of oper ation. in mode 0, the rxcoe calculates the checksum between the first 14 bytes of the ethernet frame and the fcs. this is illustrated in figure 3.19 .
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 61 revision 1.6 (07-18-11) datasheet in mode 1, the rxcoe supports vlan tags and a snap header. in this mode the rxcoe calculates the checksum at the start of l3 packet. the vlan1 tag register is used by the rxcoe to indicate what protocol type is to be used to indicate the exis tence of a vlan tag. this value is typically 8100h. example frame configurations: figure 3.19 rxcoe checksum calculation figure 3.20 type ii ethernet frame figure 3.21 ethernet frame with vlan tag dst src t y p e frame data f c s calculate checksum dst src p r o t 0 1 2 3 l3 packet f c s calculate checksum dst src 8 1 0 0 v i d 0 1 2 3 t y p e 4 l3 packet f c s calculate checksum
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 62 smsc lan9420/lan9420i datasheet the rxcoe supports a maximum of two vlan tags. if there are more than two vlan tags, the vlan protocol identifier for the third tag is treated as an ethernet type field. the checksum calculation will begin immediately after the type field. figure 3.22 ethernet frame with length field and snap header figure 3.23 ethernet frame with vlan tag and snap header figure 3.24 ethernet frame with multiple vlan tags and snap header dst src l3 packet f c s s n a p 0 s n a p 1 l e n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 3 4 5 calculate checksum dst src 8 1 0 0 v i d l3 packet f c s s n a p 0 s n a p 1 3 l e n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 4 5 6 calculate checksum dst src 8 1 0 0 v i d l3 packet f c s s n a p 0 s n a p 1 5 l e n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 6 7 8 calculate checksum 8 1 0 0 v i d 4
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 63 revision 1.6 (07-18-11) datasheet the rxcoe resides in the rx path within the ma c. as the rxcoe receives an ethernet frame it calculates the 16-bit checksum. the rxcoe passes the ethernet frame to the dmac with the checksum appended to the end of the frame. the rx coe inserts the checksum immediately after the last byte of the ethernet frame. the frame length field (fl) of receive descriptor 0 (rdes0) indicates that the frame size is increased by two bytes to accommodate the checksum. setting the rx_coe_en bit in the checksum offload engine control register (coe_cr) enables the rxcoe, while the rx_coe_mode bit selects the op erating mode. when the rxcoe is disabled, the received data is simply passed through the rxcoe unmodified. note: software applications must stop the receiver an d flush the rx data path before changing the state of the rx_coe_en or rx_coe_mode bits. note: when the rxcoe is enabled, automatic pad st ripping must be disabled (padstr bit of the mac control register (mac_cr) ) and vice versa. these functions cannot be enabled simultaneously. 3.5.5.1 rx checksum calculation the checksum is calculated 16 bits at a time. in t he case of an odd sized fram e, an extra byte of zero is used to pad up to 16 bits. consider the following packet: da, sa, type, b0, b1, b2 ? bn, fcs let [a, b] = a*256 + b; if the packet has an even number of octets then checksum = [b1, b0] + c0 + [b3, b2] + c1 + ? + [bn, bn-1] + cn-1 where c0, c1, ... cn-1 are the carry out results of the intermediate sums. if the packet has an odd number of octets then checksum = [b1, b0] + c0 + [b3, b2] + c1 + ? + [0, bn] + cn-1 3.5.6 transmit checksum of fload engine (txcoe) the transmit checksum offload engi ne (txcoe) provides assistance to the host by calculating a 16- bit checksum, typically for tcp, for a transmit ethernet frame. the txcoe calculates the checksum and inserts the results back into the data stream as it is transferred to the mac. when bit 27 of tdes1 (ck bit) is set in conjunction with bit 29 of tdes1 (fs bit) and bit 16 of the coe_cr register (tx_coe_en), the txcoe will perform a checksum calculation on the associated packet. when these three bits ar e set, a 32-bit tx checksum pream ble must be pre- pended to the beginning of the tx packet (refer to table 3.20 ). the tx checksum preamb le instructs the txcoe on the handling of the associated packe t. bits 11:0 of the tx checksu m preamble define the byte offset at which the data checksum calculation will begin. th e checksum calculation will begin at this offset and will continue until the end of the packet. the data checksum calculation must not begin in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. when the calculation is complete, the checksum will be inserted into the packet at the byte offset defined by bits 27:16 of the tx checksum preamble. the tx checksum cannot be inserted in th e mac header (first 14 bytes) or in the last 4 bytes of the tx packet. if the tx packet already includes a partial checksum calculation (perhaps inserted by an upper layer protocol), this checksum can be included in the har dware checksum calculati on by setting the txcssp field in the tx checksum preamble to include t he partial checksum. the partial checksum can be replaced by the completed checksum calculation by setting the txcsloc pointer to point to the location of the partial checksum.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 64 smsc lan9420/lan9420i datasheet note: the txcoe_mode may only be changed if the tx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the dma is disabled and the mil is empty. note: the tx checksum preamble must be dword-aligned. 3.5.6.1 tx checksum calculation the tx checksum calculation is performed using t he same operation as the rx checksum, with the exception that the calculation star ts as indicated by the preamble, and the transmitted checksum is the one?s-compliment of the final calculation. note: when the tx checksum offload feature is invoked, if the calculated checksum is 0000h, it is left unaltered. udp checksums are optional under ipv4, and a zero ch ecksum calculated by the tx checksum offload feature will erroneously indicate to the re ceiver that no checksum was calculated, however, the packet will typically not be rejected by the receiver. under ipv6, however, according to rfc 24 60, the udp checksum is not optional. a calculated checksum that yields a result of zero must be changed to ffffh for insertion into the udp header. ipv6 receivers discard udp packets c ontaining a zero checksum. thus, this feature must not be used for udp checksum calculation under ipv6. 3.5.7 mac control and st atus registers (mcsr) please refer to section 4.4, "mac control and status registers (mcsr)," on page 119 for a complete description of the mcsr. 3.6 10/100 ethernet phy lan9420/lan9420i integrates an ieee 802.3 physical layer for twisted pair et hernet app lications (phy). the phy can be configured for either 100 mbps (100base-tx) or 10 mbps (10base-t) ethernet operation. the phy block includes: ? support for auto-negotiation ? automatic polarity detection and correction ? hp auto-mdix table 3.20 tx checksum preamble bits description 31:28 reserved 27:16 txcsloc - tx checksum location this field specifies the byte offset where the tx checksum will be inserted in the tx packet. the checksum will replace two bytes of data starting at this offset. note: the tx checksum cannot be inse rted in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. 15:12 reserved 11:0 txcssp - tx checksum start pointer this field indicates start offset, in bytes, where the checksum calculation will begin in the associated tx packet. note: the data checksum calculation must not begin in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 65 revision 1.6 (07-18-11) datasheet ? energy detect ? duplex, link activity and speed indicator leds ? minimal external components are required for the utilization of the integrated phy functionally, the phy can be divided into the following sections: ? 100base-tx transmit and receive ? 10base-t transmit and receive ? internal mii interface to the ethernet media access controller (mac) ? auto-negotiation to automatically dete rmine the best speed and duplex possible ? management control to read status r egisters and write control registers figure 3.25 100base-tx data path 3.6.1 100base-tx transmit the data path of the 100base-tx is shown in figure 3.25 . each major block is explained below. 3.6.1.1 4b/5b encoding the transmit data passes from the mii block to th e 4b/5b encoder. this block encodes the data from 4-bit nibbles to 5-bit symbols (known as ?code-groups?) according to ta b l e 3 . 2 1 . each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control information or are not valid. the first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through f. the remaining code-groups are given le tter designations with slashes on either side. for example, an idle code-group is /i/, a tr ansmit error code-group is /h/, etc. the encoding process may be bypassed by clearing bit 6 of register 31. when the encoding is bypassed, the 5 th transmit data bit is equivalent to tx_er. mac tx driver mlt-3 converter nrzi converter 4b/5b encoder magnetics cat-5 rj45 100m pll internal mii 25 mhz by 4 bits tx_clk 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 mlt-3 scrambler and piso 125 mbps serial mii 25mhz by 4 bits
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 66 smsc lan9420/lan9420i datasheet table 3.21 4b/5b code table code group sym receiver interpretation transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 i idle sent after /t/r until tx_en 11000 j first nibble of ssd, translated to ?0101? following idle, else rx_er sent for rising tx_en 10001 k second nibble of ssd, translated to ?0101? following j, else rx_er sent for rising tx_en 01101 t first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of rx_er sent for falling tx_en 00111 r second nibble of esd, causes de- assertion of crs if following /t/, else assertion of rx_er sent for falling tx_en 00100 h transmit error symbol sent for rising tx_er 00110 v invalid, rx_er if during rx_dv invalid 11001 v invalid, rx_er if during rx_dv invalid 00000 v invalid, rx_er if during rx_dv invalid 00001 v invalid, rx_er if during rx_dv invalid 00010 v invalid, rx_er if during rx_dv invalid 00011 v invalid, rx_er if during rx_dv invalid
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 67 revision 1.6 (07-18-11) datasheet 3.6.1.2 scrambling repeated data patterns (especially the idle code-grou p) can have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessive emi fr om being radiated by the physical wiring. the scrambler also performs the parallel in serial out conversion (piso) of the data. 3.6.1.3 nrzi and mlt3 encoding the scrambler block passes the 5-bit wide parallel data to the nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is encoded to mlt-3. mlt3 is a tri-level code where a change in the logic level represents a code bit ?1? and the logic output remaining at the same level represents a code bit ?0?. 3.6.1.4 100m transmit driver the mlt3 data is then passed to the analog transmitte r, which launches the differential mlt-3 signal, on outputs tpo+ and tpo-, to the twisted pair m edia via a 1:1 ratio isolation transformer. the 10base-t and 100base-tx signals pa ss through the same transformer so that common ?magnetics? can be used for both. the transmitter drives into the 100 impedance of the cat-5 cable. cable termination and impedance matchi ng require external components. 3.6.1.5 100m phase lock loop (pll) the 100m pll locks onto reference clock and genera tes the 125mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 00101 v invalid, rx_er if during rx_dv invalid 01000 v invalid, rx_er if during rx_dv invalid 01100 v invalid, rx_er if during rx_dv invalid 10000 v invalid, rx_er if during rx_dv invalid table 3.21 4b/5b code table (continued) code group sym receiver interpretation transmitter interpretation
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 68 smsc lan9420/lan9420i datasheet figure 3.26 receive data path 3.6.2 100base-tx receive the receive data path is shown in figure 3.26 . detailed descriptions follow. 3.6.2.1 100m receive input the mlt-3 from the cable is fed into the phy (on inputs tpi+ and tpi-) via a 1:1 ratio transformer. the adc samples the incoming differential signal at a rate of 125m samples per second. using a 64- level quanitizer it generates 6 digital bits to repr esent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such t hat the full dynamic range of the adc can be used. 3.6.2.2 equalizer, baseline wander correction and clock and data recovery the 6 bits from the adc are fed into the dsp bl ock. the equalizer in the dsp section compensates for phase and amplitude distortion caused by the ph ysical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-quality cat-5 cable between 1m and 150m. if the dc content of the signal is such that the low-frequency comp onents fall below the low frequency pole of the isolation transformer, then the dro op characteristics of t he transformer will become significant and baseline wander (blw) on the receiv ed signal will result. to prevent corruption of the received data, the phy corrects for blw and c an receive the ansi x3.263-1995 fddi tp-pmd defined ?killer packet? with no bit errors. the 100m pll generates multiple phas es of the 125mhz clock. a mult iplexer, controlled by the timing unit of the dsp, selects the optimum phase for sa mpling the data. this is used as the received recovered clock. this clock is used to ex tract the serial data from the received signal. 3.6.2.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered levels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 100m pll internal mii 25mhz by 4 bits rx_clk 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii 25mhz by 4 bits
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 69 revision 1.6 (07-18-11) datasheet 3.6.2.4 descrambling the descrambler performs an inverse function to t he scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. during reception of idle (/i/) symbols. the descrambler synchron izes its descrambler key to the incoming stream. once synchronizati on is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization with the remote phy by searching for idle symbols within a window of 4000 bytes (40us). th is window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802. 3 standard, can be received with no interference. if no idle- symbols are detected within this time-period, rece ive operation is aborted and the descrambler re-starts the synchronization process. the descrambler can be bypassed by setting bit 0 of register 31. 3.6.2.5 alignment the de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /j/k/ start-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 3.6.2.6 5b/4b decoding the 5-bit code-groups are translated into 4-bit data nibbles according to the 4b/5b table. the ssd, /j/k/, is translated to ?0101 0101? as the first 2 nibbles of the mac preamble. reception of the ssd causes the phy to assert the internal rx_dv signal , indicating that valid data is available on the internal rxd bus. successive valid code-groups are tran slated to data nibbles. reception of either the end of stream delimiter (esd) consisting of the /t /r/ symbols, or at least two /i/ symbols causes the phy to de-assert the internal carrier sense and rx_dv. these symbols are not translated into data. 3.6.2.7 receiver errors during a frame, unexpected code-groups are consid ered receive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbo l pair. when a receive error occurs, the internal mii?s rx_er signal is asserted and arbitrary data is driven onto the internal receive data bus (rxd) to the mac. should an error be detected during the time that the /j/k/ delimiter is being decoded (bad ssd error), rx_er is asserted and the value 1110b is driven onto the internal receive data bus (rxd) to the mac. note that the internal mii?s data va lid signal (rx_dv) is not yet asserted when the bad ssd occurs. 3.6.3 10base-t transmit data to be transmitted comes from the mac. t he 10base-t transmitter rece ives 4-bit nibbles from the internal mii at a rate of 2.5mhz and conver ts them to a 10mbps serial data stream. the data stream is then manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. the 10m transmitter uses the following blocks: ? mii (digital) ? tx 10m (digital) ? 10m transmitter (analog) ? 10m pll (analog)
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 70 smsc lan9420/lan9420i datasheet 3.6.3.1 10m transmit data across the internal mii bus the mac controller drives the transmit data onto the internal txd bus. when the controller has driven tx_en high to indicate valid data, the data is latched by the mii block on the rising edge of tx_clk. the data is in the form of 4-bit wide 2.5mhz data. 3.6.3.2 manchester encoding the 4-bit wide data is sent to the tx10m block. th e nibbles are converted to a 10mbps serial nrzi data stream. the 10m pll locks onto the external cl ock or internal oscillator and produces a 20mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (internal tx_en is low), the tx10m block outp uts normal link pulses (nlps) to maintain communications with the remote link partner. 3.6.3.3 10m transmit drivers the manchester encoded data is sent to the anal og transmitter where it is shaped and filtered before being driven out as a differential signal across the tpo+ and tpo- outputs. 3.6.4 10base-t receive the 10base-t receiver gets the manchester-encoded analog signal from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller across the internal mii at a rate of 2.5mhz. this 10m receiver uses the following blocks: ? filter and squelch (analog) ? 10m pll (analog) ? rx 10m (digital) ? mii (digital) 3.6.4.1 10m receive input and squelch the manchester signal from the cable is fed into the phy (on inputs tpi+ and tpi-) via 1:1 ratio magnetics. it is first filtered to reduce any out-of-band noise. it then passes through a squelch circuit. the squelch is a set of amplitude and timi ng comparators that norma lly reject differential voltage levels below 300mv and detect and re cognize differential voltages above 585mv. 3.6.4.2 manchester decoding the output of the squelch goes to the rx10m block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the polarity is reversed (local tpi+ is connected to tpi- of the remote partner and vice versa), then this is identified and corrected. the reversed condition is indicated by the flag ?xpol?, bit 4 in register 27. the 10m pll is locked onto the received manchester signal and from this, generates the received 20mhz clock. using this clock, the manchester encoded data is extracted and conver ted to a 10mhz nrzi dat a stream. it is then converted from serial to 4-bit wide parallel data. the rx10m block also dete cts valid 10base-t idle signals - normal link pulses (nlps) - to maintain the link. 3.6.4.3 jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condit ion, that results in holding the internal tx_en input for a long period. special logic is used to detect the jabber state and abort the transmission to
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 71 revision 1.6 (07-18-11) datasheet the line, within 45ms. once tx_en is de-asserted, th e logic resets the jabber condition. bit 1 of the basic status register indicates that a jabber condition was detected. 3.6.5 auto-negotiation the purpose of the auto-negotiation function is to automatically configure the phy to the optimum link parameters based on the capabilities of its li nk partner. auto-negotiation is a mechanism for exchanging configuration information between two lin k-partners and automatically selecting the highest performance mode of operation supported by both si des. auto-negotiation is fully defined in clause 28 of the ieee 802.3 specification. once auto-negotiation has completed, information ab out the resolved link can be passed back to the controller via the internal serial management interf ace (smi). the results of the negotiation process are reflected in the speed indication bits in regist er 31, as well as the auto negotiation link partner ability register (register 5). the auto-negotiation protocol is a purely physical layer activity and proceeds independently of the mac controller. the advertised capabilities of the phy are stored in register 4 of the sm i registers. the default advertised by the phy is determined by user-defined on-chip signal options. the following blocks are activated during an auto-negotiation session: ? auto-negotiation (digital) ? 100m adc (analog) ? 100m pll (analog) ? 100m equalizer/blw/clock recovery (dsp) ? 10m squelch (analog) ? 10m pll (analog) ? 10m transmitter (analog) when enabled, auto-negotiation is started by t he occurrence of one of the following events: ? chip-level reset ? software reset ? link status down ? setting register 0, bit 9 high (auto-negotiation restart) on detection of one of these event s, the phy begins auto-negotiation by transmitting bursts of fast link pulses (flp). these are bur sts of link pulses from the 10m transmitter. they are shaped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-number ed pulses, which are always present, frame the flp burst. the 16 even-numbered pulses, which may be present or absent, cont ain the data word being transmitted. presence of a data pulse repres ents a ?1?, while absence represents a ?0?. the data transmitted by an flp burst is known as a ?link code word.? these are defined fully in ieee 802.3 clause 28. in summary, the phy advertises 8 02.3 compliance in its selector field (the first 5 bits of the link code word). it advertises its technology abi lity according to the bits set in register 4 of the smi registers. there are 4 possible matches of the technology ab ilities. in the order of priority these are: ? 100m full-duplex (highest priority) ? 100m half-duplex ? 10m full-duplex ? 10m half-duplex
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 72 smsc lan9420/lan9420i datasheet if the full capabilities of the phy are advertised (100 m, full-duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 1 00m as the highest performance mode. if the link partner is capable of half and full-duplex modes, th en auto-negotiation selects full-duplex as the highest performance operation. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. writing register 4 bits [8:5] allows software control of the capabilities advertised by the phy. writing register 4 does not automatically re -start auto-negotiation. register 0, bit 9 must be set before the new abilities will be advertised. auto-negotiation can also be disabled via software by clearing register 0, bit 12. lan9420/lan9420i does not support ?next page" capability. 3.6.6 parallel detection if lan9420/lan9420i is connected to a device lacking the ability to auto-negotiate (i.e. no flps are detected), it is able to determi ne the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case the link is pres umed to be half-duplex per the ieee standard. this ability is known as ?parallel detection?. this featur e ensures inter operability with legacy link partners. if a link is formed via parallel detection, then bit 0 in register 6 is cleared to indicate that the link partner is not capable of auto-n egotiation. the ethernet mac has access to this information via the management interface. if a fault occurs during pa rallel detection, bit 4 of register 6 is set. register 5 is used to store the link partner abilit y information, which is coded in the received flps. if the link partner is not auto-negotiation capable, then register 5 is updated after completion of parallel detection to reflect the speed capability of the link partner. 3.6.6.1 re-starting auto-negotiation auto-negotiation can be re-started at any time by sett ing register 0, bit 9. auto-negotiation will also re- start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto- negotiation resumes in an attempt to determine the new link configuration. if the management entity re-starts auto-negotiation by writing to bit 9 of the control register, lan9420/lan9420i will respond by stopping all tr ansmission/receiving operations. once the break_link_timer is done, in the auto-negotiation state-machine (approximately 1200ms) the auto- negotiation will re-start. the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. 3.6.6.2 disabling auto-negotiation auto-negotiation can be disabled by setting regist er 0, bit 12 to zero. the device will then force its speed of operation to reflect the information in regist er 0, bit 13 (speed) and register 0, bit 8 (duplex). the speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled. 3.6.6.3 half vs. full-duplex half-duplex operation relies on the csma/cd (carrier sense multiple access / collision detect) protocol to handle network traffic and collisions. in this mode, the carrier sense signal, crs, responds to both transmit and receive activity. in this mode, if data is received while the phy is transmitting, a collision results. in full-duplex mode, the phy is able to transmit and receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd pr otocol does not apply and collision detection is disabled.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 73 revision 1.6 (07-18-11) datasheet 3.6.7 hp auto-mdix hp auto-mdix facilitates the use of cat-3 (10 base-t) or cat-5 (100 base-t) media utp interconnect cable without considerat ion of interface wiring scheme. if a user plugs in either a direct connect lan cable, or a cross-ov er patch cable, as shown in figure 3.27 on page 73 , the lan9420/lan9420i auto-mdix phy is capable of configuring the tpo+/tpo- and tpi+/tpi- twisted pair pins for correct transceiver operation. the internal logic of the device detects the tx and rx pins of the connecting device. since the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. the auto-mdix function can be disabled through an internal register 27.15, or the external automdix_en configuration strap. when auto-mdix mode is disabled (27.15 = 1), the tx and rx pins can be configured as desired usi ng the mdix state (27.13) control bit. 3.6.8 phy power-down modes there are 2 power-down modes for the phy as discussed in the following sections. 3.6.8.1 general power-down this power-down is controlled by register 0, bit 11. in this mo de the phy, except the management interface, is powered-down and stays in that condition as long as ph y register bit 0.11 is high. when bit 0.11 is cleared, the phy powers up and is automatically reset. please refer to section 4.5.1, "basic control register," on page 137 for additional information on this register. note: for maximum power savings, auto-negotiation should be disabled before enabling the general power-down mode. figure 3.27 direct cable connection vs. cross-over cable connection 1 2 3 4 5 6 7 8 tpo+ tpo- tpi+ not used not used tpi- not used not used 1 2 3 4 5 6 7 8 tpo+ tpo- tpi+ not used not used tpi- not used not used direct connect cable rj-45 8-pin straight-through for 10base-t/100base-tx signaling 1 2 3 4 5 6 7 8 tpo+ tpo- tpi+ not used not used tpi- not used not used 1 2 3 4 5 6 7 8 tpo+ tpo- tpi+ not used not used tpi- not used not used cross-over cable rj-45 8-pin cross-over for 10base-t/100base-tx signaling
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 74 smsc lan9420/lan9420i datasheet 3.6.8.2 energy detect power-down this power-down mode is activated by setting t he phy register bit 17.13 to 1. please refer to section 4.5.8, "mode control/status," on page 144 for additional information on this register. in this mode when no energy is present on the line, the phy is powered down, with the e xception of the management interface, the squelch circuit and the energyon logic. the energyon logic is used to detect the presence of valid energy from 100base-tx, 10base-t, or auto-negotiation signals in this mode, when the energyon signal is low, the phy is powered-down, and nothing is transmitted. when energy is received - link pulses or packets - the internal energyon signal is asserted, and the phy powers-up. it automatically rese ts itself into the state it had prior to power-down, and asserts the int7 bit of the phy interrupt source flag register. if the en ergyon interrupt is enabled, this event will cause a phy interrupt to the interrupt controller and the power management event detection logic. the first and possibly the second packet to activate energyon may be lost. when 17.13 is low, energy detect power-down is disabled. 3.6.9 phy resets in addition to a chip-level reset, the phy supports two software-initiated resets. these are discussed in the following sections. 3.6.9.1 phy soft reset via pmt_ctrl bit 10 (phy_rst) the phy soft reset is initiated by writing a ?1? to bit 10 of the pmt_ctrl register (phy_rst). this self-clearing bit will return to ?0? after approximately 100 s, at which time the phy reset is complete. 3.6.9.2 phy soft reset via phy basic c ontrol register bit 15 (phy reg. 0.15) the phy reg. 0.15 soft reset is in itiated by writing a ?1? to bit 15 of the phy?s basic control register. this self-clearing bit will return to ?0? after approximately 256 s, at which time the phy reset is complete. the bcr reset initializes the logic within the phy, with the exception of register bits marked as nasr (not affected by software reset). 3.6.10 required ethernet magnetics the magnetics selected for use with lan9420/lan9420i should be an auto-mdix style magnetic available from several vendors. the user is urged to review smsc application note 8.13 "suggested magnetics" for the latest qualified and suggested magnetics. vendors and part numbers are provided in this application note. 3.6.11 phy registers please refer to section 4.5, "phy registers," on page 136 for a complete description of the phy registers. 3.7 power management 3.7.1 overview lan9420/lan9420i supports the mandatory d0, d3 hot and d3 cold power states. lan9420/lan9420i can signal a wake event detection by asserting the npme pin. the npme signal can be generated in all states, including (optionally) the d3 cold state. lan9420/lan9420i can assert the npme signal upon detection of various power management events, such as an ethernet ?wake on lan?, or upon detection of an ethernet link status change.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 75 revision 1.6 (07-18-11) datasheet as a result of the npme assert ion by the device, the pci host can reconfigure the power management state. this mechanism is used, for example, when lan9420/lan9420i is in low power mode and must be restored to a functional state, as a result of the detection of ?wake on lan? event. the host can respond to the subsequent npme assertion by changing the power management state (pm_state) bits in the pci power management control and status register (pci_pmcsr) to restore lan9420/lan9420i to the d0 state. as a single function device, lan9420/lan9420i implements a pci power management capabilities register (pci_pmc) and a pci power management control and status register (pci_pmcsr) , which are mapped into the pci configuration space at addresses 78h and 7ch, respectively. the 3.3vaux power supply current draw (aux_current) field of the pci_pmc register is dependant on the setting of the external vauxdet pin. the data_scale and data_select fields of the pci_pmcsr register will always return zero, as t he data register is not implemented. lan9420/lan9420i complies with revision 1.1 of the pci bus power management interface specification , v2.0 of the network device class specification and revision 3.0 of the advanced configuration and power interface specification (acpi specification). refer to section 5.3, "power consumption," on page 157 for power consumption in the various power management states. 3.7.2 related external signals and power supplies the following external signals are prov ided in support of pci power management: ? npme: lan9420/lan9420i can assert this signal upon detection of an enabled power management event. note: the npme signal requires external isolation if the system supports wake from b3 and the lan9420/lan9420i?s vauxdet=0 (i.e., the system is powered, but lan9420/lan9420i is not) ? vauxdet: this signal enables lan9420/lan9420i ?s ability to detect power management events and assert npme from the d3 cold state (wake from d3 cold ). when tied to the pci system?s 3.3vaux power supply, wake from d3 cold is enabled. when tied to ground, wake from d3 cold is disabled. ? pwrgood: if vauxdet is low (wake from d3 cold is disabled) pwrgood must be tied to +3.3v power. if vauxdet is connected to 3.3vaux (wake from d3 cold is enabled), lan9420/lan9420i uses pwrgood to determine the state of the system?s +3.3v power supply. when vauxdet is high, the device is isolated from the pci bus when pwrgood is deasserted and will ignore all pci transactions, including pciclk and pcinrst. lan9420/lan9420i requires the follow ing external 3.3v power supplies: ? vdd33io, vdd33a, vdd33bias the connection of the device?s 3.3v power pins va ries depending on the requirement for support of wake from d3 cold . if wake from d3 cold is enabled (vauxdet is connected to 3.3vaux), the 3.3v power pins must be connected to the pci syst em?s 3.3vaux power supply. if wake from d3 cold is disabled, (vauxdet is connected to vss), the 3. 3v power pins must be connected to the system?s +3.3v power. please refer to chapter 2, "pin description and configuration," on page 15 for more information on the lan9420/lan9420i power supplies. note: the lan9420/lan9420i device also requires 1.8v, but this is supplied by an internal regulator and connection does not vary. since the 1.8v supply is derived from vdd33io, there is no need to discuss it separately. 3.7.3 device clocking lan9420/lan9420i requires a fixed-frequency 25mhz cl ock source. this is typically provided by attaching a 25mhz crystal to the xi and xo pins. the clock can optionally be provided by driving the
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 76 smsc lan9420/lan9420i datasheet xi input pin with a single-ended 25mhz clock source. if a single-ended source is selected, the clock input must run continuously for normal device operation. internally, lan9420/lan9420i generates its required clocks with a phase-locked loop (pll). the lan9420/lan9420i reduces its power consumption in the d3 state by disabling its internal pll and derivative clocks. the 25mhz cl ock remains operational in all states where power is applied. please refer to section 5.9, "clock circuit," on page 167 for more information on clock requirements. 3.7.4 power states this section describes the operation of lan9420/la n9420i in each device power state (?d? states) as well as the events required to cause state transi tions. lan9420/lan9420i?s behavior is dependant on the device?s vauxdet pin (the device? s ability to detect wake events in d3 cold ). specific behaviors are discussed in the sections that follow. device power states and associated state transitions are illustrated in figure 3.28 below. note that figure 3.28 includes the system?s mechanical off (g3) power state for illust rative purposes. this is the g3 state as defined by the acpi s pecification. in this state all power (+3.3v and 3.3vaux) is off. some power state transitions may place the phy in the general power-down state as noted in the sections that foll ow. please refer to section 3.6.8.1, "general power-down," on page 73 for more information on this mode of operation. 3.7.4.1 g3 state (mechanical off) g3 is not a device power state, but is discussed here for illustrative purposes. in the g3 state all pci power is off. in this state all device context is lost. 3.7.4.1.1 power manage ment events in g3 lan9420/lan9420i does not detect power management events in the g3 state. 3.7.4.1.2 exiting the g3 state when the system leaves the g3 state, the device will behave as follows. state transitions are illustrated in figure 3.28 on page 76 . figure 3.28 lan9420/lan9 420i device power states d0 u d0 a d3 hot d3 cold t2 t4 t7 g3 vaux off t1 t 5 , t 8 t3 t6 t9 t12 t10 t11
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 77 revision 1.6 (07-18-11) datasheet ? g3 to d3 cold (t6): this transition occurs when vauxde t is connected to the pci 3.3vaux power supply and all power is off (pcinrst=x, pm_state=x, vauxdet=0, pwrgood=0) and then 3.3vaux is applied (pcinrst=0, pm_sta te=x, vauxdet=0 to 1, pwrgood=0). lan9420/lan9420i detects the application of au xiliary power and asserts its internal power-on reset (por). por resets the pme enable (pme_en) bit of the pci power management control and status register (pci_pmcsr) and sets the power management state (pm_state) field of the pci power management control and status register (pci_pmcsr) to the ?d3? state. the internal phy is held in the general-power down state and the device is powered by the pci 3.3vaux supply. the device will remain in the d3 cold state until pci power is applied. 3.7.4.2 d0 unintialized state (d0 u ) in this state all internal clocks are enabled, but the device has not been initialized by the pci host. the device cannot receive or tran smit ethernet data. depending on the reason for the transition into d0 u , the phy may have been reset and may be in the general power-down state. these conditions are noted in the discussions that follow. in d0 u the device will respond to all pci accesses. while in this state, the power management state (pm_state) field of the pci power management control and status register (pci_pmcsr) will indicate a setting of 00b (d0 state). 3.7.4.2.1 exiting the d0 u state the device will exit the d0 u state under the following conditions. state transitions are illustrated in figure 3.28 on page 76 . ? d0 u to d3 hot (t1): this transition occurs when the ho st system selects the ?d3? state in the power management state (pm_state) field of the pci power management control and status register (pci_pmcsr) . pci main and auxiliary power (if used) remain on (pcinrst=1, pm_state=00b to 11b, vauxdet=x, pwrgood=1). ? d0 u to d0 a (t2): this transition occurs when the device is in the d0 u uninitialized state and is then configured by the pci host. (pcinrst=1 , pm_state=00b, vaux det=x, pwrgood=1). ? d0 u to d3 cold (t10): this transition occurs when all power supplies are operational and the power management state (pm_state) field of the pci power management control and status register (pci_pmcsr) is set to ?d0?, but the device has not yet been initialized, and then pci power is turned off and 3.3vaux is still operational (pcinrst=1, pm_state=00b, vauxdet=1, pwrgood=1 to 0). the internal phy is reset and is placed in the general power-down mode on this transition. note that if vauxdet=0, the device is being powered from the pci +3.3v supply and will turn off (g3) when pci power is removed. ? d0 u to g3 (t12): this transition occurs when all power supplies are turned off (pcinrst=x, pm_state=xxb, vauxdet=1 to 0, pwrgood=1 to 0). for ex ample, total power failure. 3.7.4.3 d0 active state (d0 a ) in this state all internal clocks are operational and th e device is able to receive and transmit ethernet data. this is the normal operational state of the device. in d0 a the device will respond to all pci accesses. while in this state, the power management state (pm_state) field of the pci power management control and status register (pci_pmcsr) will indicate a setting of 00b (d0 state). 3.7.4.3.1 power management events in d0 a if configured to do so, the device is capable of detecting mac (wol, magic packet) and phy (link status change) wake events and is capable of asserting a pci interrupt (nint) or npme as a result of detection. refer to section section 3.7.6, "detecting powe r management events," on page 81 for more information.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 78 smsc lan9420/lan9420i datasheet 3.7.4.3.2 exiting the d0 a state the device will exit the d0 a state under the following conditions. state transitions are illustrated in figure 3.28 on page 76 . ? d0 a to d3 hot (t3): this transition occurs when, during normal device operatio n, the host system selects the ?d3? state in the power management state (pm_state) field of the pci power management control and stat us register (pci_pmcsr) . (pcinrst=1, pm_s tate=00b to 11b, vauxdet=x, pwrgood=1). if the pme enable (pme_en) bit in the pci power management control and status register (pci_pmcsr) is cleared, the internal phy is reset and is placed in the general power-down mode on this transition. if pme enable (pme_en) is set, it is assumed that the device will be required to detect ethernet power management events and the phy is not reset or placed in general power-down mode. ? d0 a to d0 u (t7): this transition occurs when pcinrst is asserted while in the d0 a state (pcinrst=1 to 0, pm_state=00b, vauxdet=x, pwrgood=1). ? d0 a to d3 cold (t11): this transition occurs when all power supplies are operational and the device has been initialized and the power management state (pm_state) field of the pci power management control and stat us register (pci_pmcsr) is set to ?d0?, and then pci power is turned off and 3.3vaux is still operational (pcinrst=1, pm_state=00b, vauxdet=1, pwrgood=1 to 0).the internal phy is reset and is placed in the general power-down mode on this transition. note that if vauxdet=0, the device is being powered from the pci +3.3v supply and will turn off (g3) when pci power is removed. ? d0 a to g3 (t12): this transition occurs when all power supplies are turned off (pcinrst=x, pm_state=xxb, vauxdet=1 to 0, pwrgood=1 to 0). for ex ample, total power failure. 3.7.4.4 the d3 hot state in this state the pci power is on, but normal ether net receive and transmit operation is disabled. in d3 hot power is reduced by disabling the inte rnal pll and derivati ve clocks. if the pme enable (pme_en) bit in the pci power management control and status register (pci_pmcsr) is cleared, power is also conserved by placing the internal phy into general power-down mode on transition to this state. in d3 hot pci configuration accesses are permitted, but the device will not respond to pci memory or i/o accesses. while in this state, the power management state (pm_state) field of the pci power management control and stat us register (pci_pmcsr) will indicate a setting of 11b (d3 state). 3.7.4.4.1 power management events in d3 hot if configured to do so, the device is capable of detecting mac (wol, magic packet) and phy (link status change) wake events and is capable of assertin g npme as a result of detection. refer to section section 3.7.6, "detecting power management events," on page 81 for more information. 3.7.4.4.2 exiting the d3 hot state the device will exit the d3 hot state under the following conditions. state transitions are illustrated in figure 3.28 on page 76 . ? d3 hot to d3 cold (t4): this transition occurs after the device has been placed in the d3 hot state by the host system and then pci power is turned off, bu t pci 3.3vaux remains operational (pcinrst=x, pm_state=11b, vauxdet=1, pwrgoo d=1 to 0). in this state the device is powered by the pci 3.3vaux supply. ? d3 hot to d0 u (t5): this transition occurs when the device is in the d3 hot state and host system selects the ?d0? state in the power management state (pm_state) field of the pci power management control and stat us register (pci_pmcsr) (pcinrst=1, pm_state=11b to 00b, vauxdet=x, pwrgood=1). a d3 tr ansition reset (d3rst) occurs during this transition. refer to section 3.7.5, "resets," on page 79 to for more information on this reset.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 79 revision 1.6 (07-18-11) datasheet ? d3 hot to d0 u (t8): this transition occurs when pcinrst is asserted while in the d3 hot state (pcinrst=1 to 0, pm_state=11b, vauxdet=x, pwrgood=1). refer to section 3.7.5, "resets," on page 79 to for more inform ation on this reset. ? d3 hot to g3 (t12): this transition occurs when all power supplies are turned off (pcinrst=x, pm_state=xxb, vauxdet=1 to 0, pwrgood=1 to 0). for ex ample, total power failure. 3.7.4.5 the d3 cold state lan9420/lan9420i?s behavior in this state is dependant on the status of vauxdet. when vauxdet=0, lan9420/lan9420i is powered from the system?s +3.3v supply; wake from d3 cold is disabled and the pci +3.3v power supply is off. since vauxdet=0, the device is powered from the system?s +3.3v power supply and lan942 0/lan9420i loses all power and context (to lan9420/lan9420i, this appears identical to the g3 state). when vauxdet=1, lan9420/lan9420i is powered fr om the auxiliary power supply and the auxiliary 3.3vaux supply remains operational. the device is isolated from the pci bus and ignores all pci accesses, as well as pcinrst. if the pme enable (pme_en) bit in the pci power management control and status register (pci_pmcsr) is set, it is assumed that the device is config ured to detect a wake event from d3 cold . in this state the pci 3.3vaux power is on, but normal ethernet receive and transmit operation is disabled. in d3 cold power is reduced by disabling the internal pll and derivative clocks. 3.7.4.5.1 power management events in d3 cold if configured to do so, the device is capable of detecting mac (wol, magic packet) and phy (link status change) wake events and is capable of assert ing npme as a result of detection. in order to generate npme in the d3 cold state, lan9420/lan9420i must be powered from the 3.3vaux power supply. 3.7.4.5.2 exiting the d3 cold state the device will exit the d3 cold state under the following conditions. state transitions are illustrated in figure 3.28 on page 76 . ? d3 cold to d0 u (t9): this transition occurs when the +3.3 v power supply is turned on. if vauxdet = 1, this means that the 3.3vaux supply was ac tive and pci power is now turned on (pcinrst=1 to 0, pm_state=11b, vauxdet=1, pwrgood=0 to 1) . in this case the enti re device is reset, with the exception of the pci pme context, which is preserved. the internal phy is reset and is configured for all capable operation with auto negotiation enabled. ? if vauxdet = 0, the device is se eing power for the first time and the internal power-on reset (por) is asserted (pcinrst=1 to 0, pm_state=x, vauxdet=0, pwrgood=0 to 1). all logic and registers are reset and the internal phy is configur ed for all capable operation with auto negotiation enabled. ? d3 cold to g3 (t12): this transition occurs when all power supplies are turned off (pcinrst=x, pm_state=xxb, vauxdet=1 to 0, pwrgood=1 to 0). for ex ample, total power failure. 3.7.5 resets the lan9420/lan9420i device employs the following resets: ? power-on reset (por): this reset is asserted on initial application of device power. if the device is powered from the pci auxiliary power supply, th is reset is asserted for approximately 21ms after 3.3vaux has reached its operational level. if the device is not powered from the auxiliary supply, this reset is asserted for approximately 21ms after the main pci 3.3v supply has reached its operational level. ? pcinrst: this is the active-low re set input from the pci bus. in the d0 u or d0 a states, the device is reset when pcinrst is low. in the d3 hot or d3 cold states, the device is reset on the deassertion (low-to-high transition) of pcinrst. ? d3 transition reset (d3rst): this reset occurs when transitioning from the d3 hot to d0 u states.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 80 smsc lan9420/lan9420i datasheet ? software reset (srst): this reset is initiated by setting the software reset (srst) bit in the bus mode register (bus_mode) . software reset does not clear control register bits marked as nasr. ? phy reset via pmt_ctrl (p hy_rst): this reset is asserted by setting the phy reset (phy_rst) in the power management control register (pmt_ctrl) . refer to section section 3.6.9.1, "phy soft reset via pmt_ctrl bit 10 (phy_rst)," on page 74 for more information. ? phy soft reset (phy_srst): this reset is asserted by writing a ?1? to bit 15 of the phy?s basic control register. refer to section section 3.6.9.2, "phy soft rese t via phy basic control register bit 15 (phy reg. 0.15)," on page 74 for more information. the reset map in ta b l e 3 . 2 2 shows the conditions under which various modules within lan9420/lan9420i are reset. note 3.6 pme logic is reset by pcinrst if lan9420/lan9420i is not configured to support d3 cold wake; pme logic is not reset by pcinrst if lan9420/lan9420i is configured to support d3 cold wake. note 3.7 software reset does not clear control register bits marked as nasr. note 3.8 if phy was reset on entry to the d3 hot , it will be reset when exiting the d3 hot . if the phy was not reset on entry to the d3 hot , it will not be reset when exiting d3 hot . note 3.9 the subsystem vendor id (ssvid) subsystem device id (ssid) registers (optionally loaded from the eeprom) are not reset during this transition. note 3.10 phy register bits designated as nasr are not initialized by setting the phy soft reset bit in the phy?s basic control register . note 3.11 phy reset conditions and mode settings are discussed in section 3.7.5.1, "phy resets," on page 80 3.7.5.1 phy resets in addition to the phy_rst, phy_srst and pcinrst noted in ta b l e 3 . 2 2 , the phy may also be reset on specific state transitions depending on the state of the vauxdet signal and pme enable (pme_en) bit in the pci power management control and status register (pci_pmcsr) . resets may leave the phy in normal operating mode (all-capable with auto-negotiation enabled) or in the general power-down mode. specific phy reset conditions and the state of the phy following reset, are table 3.22 reset map block por pcinrst d3rst srst phy_rst phy_srst pci pme logic x note 3.6 phy ( note 3.11 ) xx note 3.8 xx ( note 3.10 ) eeprom load x x pci configuration registers (except pme registers) xx x ( note 3.9 ) mac x x x x tx/rx dmacs x x x x scsr x x x x ( note 3.7 )
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 81 revision 1.6 (07-18-11) datasheet detailed in table 3.23 below. the state transitions noted in this table refer to those specified in section 3.7.4, "power states," on page 76 . 3.7.6 detecting power management events lan9420/lan9420i supports the ability to generate pc i wake events using npme on detection of a magic packet, wakeup frame or ethernet link status change (energy detect). a simplified diagram of the wake event detection logic is shown in figure 3.29 . two control bits are implemented in the pm t_ctrl scsr: wake-on-lan enable (wol_en) and energy detect enable (ed_en). depending on the state of these control bits, the logic will generate an internal wake event interrupt when the mac detects a wakeup event (wakeup frame or magic packet), or a phy interrupt is asserted (energy detect). two wakeup status (wups) are implemented in the scsr space. these bits are set depe nding on the corresponding wake event. (see section 4.2.9, "power management control register (pmt_ctrl)," on page 98 for further information) wakeup frame detection must be enabled in the ma c before detection can occur. likewise, the energy detect interrupt must be enabled in the phy bef ore this interrupt can be used as a wake event. if lan9420/lan9420i is properly configured, the internal wake event interrupt will cause the assertion of the npme signal on detection of a wake event. when the device is in the d0 a state, wake event detection can al so trigger the assertion of a pci interrupt (nint). upon detection of the wake event, the wake logic sets the wake event interrupt table 3.23 phy resets condition vauxdet pme_en mode t9 0 x normal t6 1 x general power-down t1, t3 x 0 general power-down t10, t11 1 0 general power-down t5 (d3rst) x 0 normal figure 3.29 wake event detection block diagram mac wakeup event wol_en (pmt_ctrl register) rw wups[1] (pmt_ctrl register) phy interrupt ed_en (pmt_ctrl register) rw wups[0] (pmt_ctrl register) pme_status (pci_pmcsr register) pme_en (pci_pmcsr register) rw npme (pci bus) wake_int (interrupt controller)
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 82 smsc lan9420/lan9420i datasheet (wake_int) status bit in the interrupt status register (int_sts) . if so enabled, setting this status bit will cause the assertion of nint. 3.7.6.1 enabling wakeup frame wake events the host system must perform the following steps to enable lan9420/lan9420i to assert a pci wake event (npme) on detecti on of a wakeup frame. 1. all transmit and receive operations must be halted: a. all pending ethernet tx and rx operations must be completed, and then the dma controller and mac must be halted. b. the software application must wait for all pending dma transactions to complete. upon completion, no further transactions are permitted. 2. the mac must be configured to detect the de sired wake event. this process is explained in section 3.5.4, "wakeup frame detection," on page 57 . 3. bit 1 of the wakeup status (wups[1]) in the power management control register (pmt_ctrl) must be cleared since a set bit will cause the immediate assertion of wake event when wol_en is set. the wups[1] bit will not clear if the internal mac wakeup event is asserted. 4. set the wake-on-lan wakeup enable (wol_en) bit in the power management control register (pmt_ctrl) . 5. set the pme enable (pme_en) bit in the pci power management control and status register (pci_pmcsr) . note that pme_en must be se t before entering the d3 state. if this bit is not set, the internal phy will be reset and placed in the general power-down state and the device will not be able to detect wakeup frames. 6. to place the device in the d3 state, set the power management state (pm_state) field of the pci power management control and st atus register (pci_pmcsr) to 11b (?d3? state). the device will enter d3 hot . device behavior in this state is described in section 3.7.4.4, "t he d3hot state," on page 78 . on detection of an enabled wakeup frame, the de vice will assert the npme signal. the npme signal will remain asserted until the pme enable (pme_en) and/or the pme status (pme_status) bits are cleared by the host. note: if waking from a reduced-power state causes t he assertion of a device reset, bit 4 of the power management control register (pmt_ctrl) register (wups[1]) will be cleared. 3.7.7 enabling link status cha nge (energy detect) wake events the host system must perform the following steps to enable lan9420/lan9420i to assert a pci wake event (npme) on detection of an ethernet link status change. 1. all transmit and receive operations must be halted: a. all pending ethernet tx and rx operations must be completed, and then the dma controller and mac must be halted. b. the software application must wait for all pending dma transactions to complete. upon completion, no further transactions are permitted. 2. the energyon event must be enabled as a phy interrupt source. this is done by setting bit 7 in the phy?s interrupt mask register. 3. the phy must be enabled for the energy detect power down mode. this is done by setting the edpwrdown bit in the phy?s mode control/status register. enabling the energy detect power- down mode places the phy in a reduced power st ate. in this mode of operation the phy is not capable of receiving or transmitting ethernet data. in this state the phy will assert its internal interrupt if it detects et hernet activity. refer to section 3.6.8.2, "energy detect power-down," on page 74 for more information.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 83 revision 1.6 (07-18-11) datasheet 4. bit 0 of the wakeup status (wups[0]) in the power management control register (pmt_ctrl) must be cleared since a set bit will cause the immediate assertion of wake event when ed_en is set. the wups[0] bit will not clear if the internal phy interrupt is asserted. 5. set the energy-detect wakeup enable (ed_en) bit in the power management control register (pmt_ctrl) . 6. set the pme enable (pme_en) bit in the pci power management control and status register (pci_pmcsr) . note that pme_en must be se t before entering the d3 state. if this bit is not set, the internal phy will be reset and placed in the general power-down state and the device will not be able to detect an ethe rnet link status change. 7. if the device is to be placed in the d3 state, set the power management state (pm_state) field of the pci power management control and status register (pci_pmcsr) to 11b (?d3? state). the device will enter d3 hot . device behavior in this state is described in section 3.7.4.4, "the d3hot state," on page 78 . on detection of ethernet activity (energy), the device will assert the npme signal. the npme signal will remain asserted until the pme enable (pme_en) and/or the pme status (pme_status) bits are cleared by the host.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 84 smsc lan9420/lan9420i datasheet chapter 4 register descriptions the registers are partitioned into five groups. the first group is the sy stem control and status registers (scsr). the second group is the dm a control and status registers (dcsr). these registers are located within the dmac and are used to control dma-specific functions. the third group is the mac control and status registers (mcsr). thes e registers handle all control and status directly related to mac function and are located within the mac. the fourth group are the phy control registers. these registers reside within the phy, and are accessed indirectly through mcsr within the mac. the fifth set of registers is the pci configuration space csr (config csr) registers. each group is described separately within this section. figure 4.1 illustrates the memory map for the first three register groups. the base address (ba) of the map is determined by bar3/bar4, contained within the standard pci header registers of the config csr. see table 4.10, ?standard pci header registers supported,? on page 151 for details. in the case of bar3, ba may be either the address of the lower (for little endian access) or upper (for big endian access) 512 byte segment of the 1kb memspace. see figure 3.3 csr double endian mapping on page 27 for details.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 85 revision 1.6 (07-18-11) datasheet figure 4.1 lan9420/lan9420i csr memory map mac control and status registers (m csr's) ba + 7ch ba + 80h reserved (do not use) ba + 54h ba + b0h ba reserved (do not use) ba + 1fch ba + 58h dmac control and status registers (dcsr's) system control and status registers (scsr's) ba + b4h reserved (do not use) ba + bch ba + c0h ba + 0fch ba + 100h note: bar3 ? mem space is 1kb bar4 ? i/o space is 256b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 86 smsc lan9420/lan9420i datasheet 4.1 register nomenclature table 4.1 describes the register bit attri butes used throughout this section. register attribute examples: ? r/w: can be written. will return current setting on a read. ? r/wc: will return current setting on a read. writing a one clears the bit. table 4.1 register bit types register bit type notation register bit description r read: a register or bit with this attribute can be read. w write: a register or bit with this attribute can be written. ro read only: read only. writes have no effect. wo write only: if a register or bit is write-only, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect rc read to clear: contents is cleared after the read. writes have no effect. ll latch low: this mode is used by the ethernet ph y registers. bits with this attribute will stay low until the bit is read. after a read, the bit will remain low, but will change to high if the condition that caused the bit to go low is removed. if the bit has not been read the bit will remain low regardle ss of if its cause has been removed. lh latch high: this mode is used by the ethernet ph y registers. bits with this attribute will stay high until the bit is read. after a read, the bit will remain high, but will change to low if the condition that caused the bit to go high is removed. if the bit has not been read the bit will remain high regardless of if its cause has been removed. sc self-clearing: contents is self-cleared after the being set. writes of zero have no effect. contents can be read. nasr not affected by software reset. the state of nasr bits does not change on asser- tion of a software reset. reserved reserved field: certain bits within registers are listed as ?reserved?. unless stated otherwise, these bits mu st be written with zero for fu ture compatibility. the val- ues of these bits are not guaranteed when read. reserved address: certain addresses with the device are listed as ?reserved?. unless otherwise noted, do not read fr om or write to reserved addresses.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 87 revision 1.6 (07-18-11) datasheet 4.2 system control and status registers (scsr) table 4.2, "system control and status register addresses" lists the registers contained in this section. table 4.2 system control and status register addresses offset symbol register name 00c0h id_rev id and block revision 00c4h int_ctl interrupt control register 00c8h int_sts interrupt status register 00cch int_cfg interrupt configuration register 00d0h gpio_cfg general pu rpose io configuration 00d4h gpt_cfg general purpose timer configuration 00d8h gpt_cnt general purpose timer current count 00dch bus_cfg system bus configuration register 00e0h pmt_ctrl power management control 00e4h ? 00f0h reserved reserved for future use 00f4h free_run free run counter 00f8h e2p_cmd eeprom command register 00fch e2p_data eeprom data register the registers located at 0100h - 01fch are visible via the memory map, but are reserved and must not be accessed. the registers located at 0100h - 01fch are not visible or accessible via io. 0100h ? 01fch reserved reserved for future use
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 88 smsc lan9420/lan9420i datasheet 4.2.1 id and re vision (id_rev) this register contains the device id and block revision. note 4.1 default value is dependent on device revision. offset: 00c0h size: 32 bits bits description type default 31:16 chip id. this 16-bit field is used to identify the device model. ro 9420h 15:0 block revision. this 16-bit field is used to identify the revision of the ethernet subsystem. ro note 4.1
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 89 revision 1.6 (07-18-11) datasheet 4.2.2 interrupt control register (int_ctl) interrupts are enabled/disabled through this register. refer to section 3.3.1, "inte rrupt controller," on page 28 for more information on the interrupt controller. note: the dmac interrupt (dmac_int) is enabled through the dcsr. offset: 00c4h size: 32 bits bits description type default 31:16 reserved ro - 15 software interrupt enable (sw_int_en) on a transition from low to high, this register bit triggers the software interrupt. r/w 0b 14 reserved ro - 13 master bus error interrup t enable (mberr_int_en) when set high, the master bus error is enabled to generate an interrupt. r/w 0b 12 slave bus error interrupt enable (sberr_int_en) when set high, the slave bus error is enabled to generate an interrupt. r/w 0b 11:7 reserved ro - 6:4 gpio [2:0] (gpiox_int_en) when set high the gpiox are enabled as interrupt sources. r/w 000b 3 gp timer interrupt enable (gpt_int_en) when set high the general purpose timer is enabled as an interrupt source. r/w 0b 2 phy interrupt enable (phy_int_en) when set high, the phy interrupt is enabled as an interrupt source. r/w 0b 1 wake event interrupt enable (wake_int_en) when set high, wake event detection is enabled as an interrupt source. r/w 0b 0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 90 smsc lan9420/lan9420i datasheet 4.2.3 interrupt status register (int_sts) this register contains the curren t status of the generat ed interrupts. some of these interrupts are also cleared through this register. offset: 00c8h size: 32 bits bits description type default 31:16 reserved ro - 15 software interrupt (sw_int) this bit latches high upon the sw_int_en bit toggling from a 0 to 1. the interrupt is cleared by writing a ?1?. writing ?0? has no effect. r/wc 0b 14 reserved ro - 13 master bus error interrupt (mberr_int) when set, indicates dma controller has detected an error during descriptor read, or during a transmit data read operation. the interrupt is cleared by writing a ?1? to this bit. writing a ?0? has no effect. to guarantee a clean recovery from a mberr_int condition, a software reset must be performed by setting the software reset (srst) bit of the bus mode register (bus_mode) . alternatively, the condition may be cleared by a hardware reset. r/wc 0b 12 slave bus error interrupt (sberr_int) when set, indicates that the pci ta rget interface has detected an error when the host attempted to access the lan9420/lan9420i csr. the interrupt is cleared by writing a ?1? to this bit. writing a ?0? has no effect. to guarantee a clean recovery from a sberr_int condition, a software reset must be performed by setting the software reset (srst) bit of the bus mode register (bus_mode) . alternatively, the condition may be cleared by a hardware reset r/wc 0b 11:7 reserved ro - 6:4 gpio [2:0] (gpiox_int) interrupts are generated from the gp io?s. these interrupts are configured through the gpio_cfg register. refer to 4.2.5, "general purpose input/output configuration re gister (gpio_cfg)," on page 93 for more information. these interrupts are cleared by writing a ?1? to the corresponding bits. writing ?0? has no effect. r/wc 000b 3 gp timer (gpt_int) this interrupt is issued when the general purpose timer wraps from maximum count to zero. this interrupt is cleared by writing a ?1? to this bit. writing ?0? has no effect. r/wc 0b 2 phy interrupt (phy_int) indicates assertion of t he phy interrupt. the phy interrupt is cleared by clearing the interrupt source in the phy interrupt status register. refer to section 4.5.11, "interrupt source flag," on page 147 for more information on this interrupt. writing to this bit has no effect. ro 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 91 revision 1.6 (07-18-11) datasheet 1 wake event interru pt (wake_int) indicates a valid mac wakeup event (wakeup frame or magic packet) or phy interrupt (energy-detect) has been received. the particular source of the interrupt can be determined by the wups field of the power management control register (pmt_ctrl) . both wups bits must be cleared in order to clear wake_int. writing to the wake_int bit has no effect. ro 0b 0 dmac interrupt (dmac_int) this interrupt is generated by the dma controller. this bit is read-only. the dma interrupt is cleared by clearing the interrupt source in the dmac_status dcsr. writing to this bit has no effect. ro 0b bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 92 smsc lan9420/lan9420i datasheet 4.2.4 interrupt configurat ion register (int_cfg) this register configures and moni tors the interrupt (irq) signal. control of the de-assertion interval for the irq is also included. the de-assertion interval is the minimum time the irq will remain de-asserted after it has been asserted and cleared. after this time period has elapsed, the irq will be asserted if the interrupt is acti ve. this interval begins counting when interrupt sources have been clear ed from the asserted state. refer to section 3.3.1, "interrupt controller," on page 28 for more information on the interrupt controller. offset: 00cch size: 32 bits bits description type default 31:20 reserved ro - 19 master interrupt (irq_int) this read-only bit indicates the state of the irq line. when set high, one of the enabled interrupts is currently active. this bit will respond to the associated interrupts regardless of the irq_en field. this bit is not affected by the setting of the int_deas field. ro 0b 18 irq enable (irq_en) when cleared, the irq output to the pcib is disabled and will be permanently de-asserted. when set, the irq output functions normally. r/w 0b 17:10 reserved ro - 9 interrupt de-assertion inte rval clear (int_deas_clr) writing a one to this register clears the de-assertion counter in the interrupt controller, thus causing a new de-asse rtion interval to begin (regardless of whether or not the interrupt controller is currently in an active de-assertion interval). r/w/sc 0b 8 interrupt de-assertion status (int_deas_sts) when set, this bit indicate s that the int_deas is cu rrently in a de-assertion interval, and any interrupts (as indicated by the irq_int and int_en bits) will not be delivered to the irq. when cleared, the int_deas is currently not in a de-assertion interval, and enabled interrupts will be delivered to the irq. ro 0b 7:0 interrupt de-assertion interval (int_deas) this field determines the interrupt de-assertion interval for the irq in multiples of 10 microseconds. writing zeros to this field disables the int_deas interval and resets the interval counter. any pending interrup ts are then issued. if a new, non-zero value is written to the int_deas fiel d, any subsequent interrupts will obey the new setting. note: the interrupt de-assertion interval does not apply to the wake interrupt. r/w 00h
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 93 revision 1.6 (07-18-11) datasheet 4.2.5 general purpose input/output configuration regi ster (gpio_cfg) this register configures the gpio and led functions. offset: 00d0h size: 32 bits bits description type default 31 reserved ro - 30:28 led[3:1] enable (ledx_en) a ?1? sets the associated pin as an led output. when cleared low, the pin functions as a gpio signal. bits are assigned as follows: led1/gpio0 - bit 28 led2/gpio1 - bit 29 led3/gpio2 - bit 30 r/w 000b 27 reserved ro - 26:24 gpio interrupt polarity 0-2 (gpio_int_pol) when set high, a high logic level on the corresponding gpio pin will set the corresponding int_sts register bit. when cleared low, a low logic level on the corresponding gpio pin will set the corresponding int_sts register bit. gpio interrupts must also be enabled in gpiox_int_en in the int_en register. bits are assigned as follows: gpio0 - bit 24 gpio1 - bit 25 gpio2 - bit 26 note: gpio inputs must be active for greater than 80ns to be recognized as interrupt inputs. r/w 000b 23 reserved ro - 22:20 eeprom enable (eepr_en) the value of this field determines the function of the external eedio and eeclk. please refer to table 4.3, ?eeprom enable bi t definitions,? on page 94 for the eeprom enable bit function definitions. note: the host must not change the function of the eedio and eeclk pins when an eeprom read or writ e cycle is in progress. do not use reserved setting. r/w 000b 19 reserved ro - 18:16 gpio buffer type 0-2 (gpiobufn) when set, the output buffer for the corresponding gpio signal is configured as a push/pull driver. when cleared, the corresponding gpio set configured as an open-drain driver. bits are assigned as follows: gpio0 ? bit 16 gpio1 ? bit 17 gpio2 ? bit 18 r/w 000b 15:11 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 94 smsc lan9420/lan9420i datasheet note 4.2 default value is dependent on the state of the gpio pin. 10:8 gpio direction 0-2 (gpdirn) when set, enables the corresponding gpio as an output. when cleared the gpio is enabled as an input. bits are assigned as follows: gpio0 ? bit 8 gpio1 ? bit 9 gpio2 ? bit 10 r/w 000b 7:5 reserved ro - 4:3 gpo data 3-4 (gpodn) the value written is reflected on gpon. bits are assigned as follows: gpo3 ? bit 3 gpo4 ? bit 4 r/w 00b 2:0 gpio data 0-2 (gpiodn) when enabled as an output, the value written is reflected on gpion. when read, gpion reflects the current state of the corresponding gpio pin. bits are assigned as follows: gpio0 ? bit 0 gpio1 ? bit 1 gpio2 ? bit 2 r/w note 4.2 table 4.3 eeprom enab le bit definitions [22] [21] [20] eedio function eeclk function 0 0 0 eedio eeclk 0 0 1 gpo3 gpo4 0 1 0 reserved 0 1 1 gpo3 rx_dv 1 0 0 reserved 1 0 1 tx_en gpo4 1 1 0 tx_en rx_dv 1 1 1 tx_clk rx_clk bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 95 revision 1.6 (07-18-11) datasheet 4.2.6 general purpose timer conf iguration register (gpt_cfg) this register configures the general purpose timer (gpt). the gpt can be configured to generate interrupts at intervals defined in this register. refer to section 3.3.3, "general purpose timer (gpt)," on page 30 for more information on the general purpose timer. offset: 00d4h size: 32 bits bits description type default 31:30 reserved ro - 29 general purpose timer enable (timer_en) when a one is written to this bit the gpt is put into the run state. when cleared, the gpt is halted. on the 1-to-0 transition of this bit the gpt_load field will be preset to ffffh. r/w 0b 28:16 reserved ro - 15:0 general purpose timer pre-load (gpt_load) this value is pre-loaded into the gpt. see section 3.3.3, "general purpose timer (gpt)," on page 30 for more details. r/w ffffh
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 96 smsc lan9420/lan9420i datasheet 4.2.7 general purpose timer curre nt count register (gpt_cnt) this register reflects the current value of the general purpose timer. offset: 00d8h size: 32 bits bits description type default 31:16 reserved ro - 15:0 general purpose timer cu rrent count (gpt_cnt) this 16-bit field reflects the current value of the gpt. ro ffffh
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 97 revision 1.6 (07-18-11) datasheet 4.2.8 bus master bridge conf iguration register (bus_cfg) this register determines the bus arbitration c haracteristics for the rx and tx dma engines. offset: 00dch size: 32 bits bits description type default 31:28 reserved ro - 27 reserved r/w 0b 26:25 rx/tx arbitration priority select (csr_rxtxweight) this field selects the arbitration prio rity ratio for receive and transmit dma operations. this field has no effect unless the bar bit in the bus_mode dcsr is cleared. setting priority ratio (rx:tx) ------------------------------------------------ 00b 1:1 01b 2:1 10b 3:1 11b 4:1 r/w 00b 24:0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 98 smsc lan9420/lan9420i datasheet 4.2.9 power management c ontrol register (pmt_ctrl) this register controls the wake even t detection features. this register also controls the scsr soft reset to the phy. note: if waking from a reduced-power state causes the assertion of a device reset, this register will be cleared. offset: 00e0h size: 32 bits bits description type default 31:11 reserved ro - 10 phy reset (phy_rst) writing a ?1? to this bit resets the phy. the internal logic automatically holds the phy reset for a minimum of 100us. when the phy is released from reset, this bit is automatically cleared. all writes to this bit are ignored while this bit is high. sc 0b 9 wake-on-lan wakeup enable (wol_en) when set, the mac wake detect signal is enabled as a wake event and will set the pme_status in the pci_pmcsr. the mac wake detect signal can be programmed for assertion upon detection of a wakeup frame or magic packet. r/w 0b 8 energy-detect wakeup enable (ed_en) when set, the phy interrupt signal is enabled as a wake event and will set the pme_status bit in the pci_pm csr. the phy interrupt can be programmed for assertion upon detection of a link status change (energy detect) event. r/w 0b 7:5 reserved ro - 4:3 wakeup status (wups) this field indicates the cause of the la st wake event. this field is cleared by writing ?1? to the currently set bit(s). wups is encoded as follows: 00b ? no wakeup event detected x1b ? phy interrupt (energy-detect) 1xb ? mac wakeup event (wakeup frame or magic packet) note: if waking from a reduced-power st ate causes the assertion of a device reset, the wakeup status bits will be cleared. r/wc 00b 2:0 reserved ro 000b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 99 revision 1.6 (07-18-11) datasheet 4.2.10 free run counter (free_run) this register reflects the value of the free-running (6. 25mhz) counter (frc). offset: 00f4h size: 32 bits bits description type default 31:0 free running counter (fr_cnt) this field reflects the value of a fr ee-running 32-bit counter. at reset, the counter starts at zero and is increm ented for every 160ns cycle. when the maximum count has been reached the counter will rollover. refer to section 3.3.4, "free-run counter (frc)," on page 31 for more information on the frc. ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 100 smsc lan9420/lan9420i datasheet 4.2.11 eeprom command register (e2p_cmd) this register is used to control the read and write operations with the serial eeprom. offset: 00f8h size: 32 bits bits description type default 31 epc busy (epc_bsy) when a 1 is written into this bit, the operation specified in the epc command field is performed at the specified eeprom address. this bit will remain set until the operation is complete. in the ca se of a read this means that the host can read valid data from the e2p data register. the e2p_cmd and e2p_data registers should not be modified until this bit is cleared. in the case where a write is attempted and an eeprom is not present, the epc busy remains busy until the epc time-out occurs. at that time the busy bit is cleared. note: epc busy will be high immediately following power-up or reset. after the eeprom co ntroller has finished re ading (or attempting to read) the mac addr ess and ssvid/ssid from the eeprom, the epc busy bit is cleared. sc 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 101 revision 1.6 (07-18-11) datasheet 30-28 epc command (epc_cmd) this field is used to issue command s to the eeprom co ntroller. the epc will execute commands when the epc busy bit is set. a new command must not be issued until the previous command completes. this field is encoded as follows: [30:28] = 000; read (read location): this command will cause a read of the eeprom location pointed to by epc address. the result of the read is available in the e2p_data register. [30:28] = 001; ewds (erase/write disable): after issued, the eeprom will ignore erase and write commands. to re-enable eras e/write operations issue the ewen command. [30:28] = 010; ewen (erase/write enable): enables the eeprom for erase and write operations. the eeprom will allow eras e and write operat ions until the erase/write disable command is sent, or until power is cycled. note: the eeprom device will power-up in the erase/wr ite-disabled state. any erase or write operat ions will fail until an erase/write enable command is issued. [30:28] = 011; write (write location): if erase/write operations are enabled in the eeprom, this command will cause the c ontents of the e2p_data register to be written to the eeprom locati on selected by the epc address field. [30:28] = 100; wral (write all): if erase/write operations are enabled in the eeprom, this command will cause the contents of th e e2p_data register to be written to every eeprom memory location. [30:28] = 101; erase (erase location): if erase/write operations are enabled in the eeprom, this command will erase t he location selected by the epc address field. [30:28] = 110; eral (erase all): if erase/write operations are enabled in the eeprom, this command will initiate a bulk erase of the entire eeprom. [30:28] = 111; reload (eeprom reload): instructs the eeprom controller to reload the mac address and ssvid/ssid from the eeprom. if a value of 0xa5 is not found in the first addr ess of the eeprom, the eepr om is assumed to be unprogrammed and eeprom reload operation will fail. the ?eeprom loaded? bit indicates a successful load of the mac address and ssvid/ssid. r/w 000b 27:10 reserved ro - 9 epc time-out (epc_to) if an eeprom operation is performed, and there is no response from the eeprom within 30ms, the eep rom controller will tim eout and retu rn to its idle state. this bit is set when a time -out occurs indicating that the last operation was unsuccessful. note: if the eedio signal pin is externally pulled-high, epc commands will not time out if the eeprom device is missing. in this case the epc busy bit will be cleared as soon as the command sequence is complete. it should also be noted that the erase, eral, write and wral commands are the only epc commands that will time- out if an eeprom device is not present -and- the eedio signal is pulled low. r/wc 0b bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 102 smsc lan9420/lan9420i datasheet 8 eeprom loaded when set, this bit indica tes that a valid eeprom wa s found, and that the mac address and ssvid/ssid programming have completed normally. this bit is set after a successful load of the mac address and ssvid/ssid after power-up, or after a reload command has completed. r/wc 0b 7:0 epc address (epc_addr) the 8-bit value in this field is used by the eeprom controller to address the specific memory loca tion in the serial eeprom. this is a byte aligned address. r/w 00h bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 103 revision 1.6 (07-18-11) datasheet 4.2.12 eeprom data register (e2p_data) this register is used in conjunction with the e2p_cmd register to perform read and write operations with the serial eeprom. note 4.3 following reset, the de fault value of the eeprom data refl ects the last value read by the eeprom controller during auto-lo ading, or the last value read during an attempt to auto- load the eeprom contents. offset: 00fch size: 32 bits bits description type default 31:8 reserved ro - 7:0 eeprom data value read from or written to the eeprom. r/w note 4.3
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 104 smsc lan9420/lan9420i datasheet 4.3 dmac control and st atus registers (dcsr) table 4.4 lists the registers contained in this section. table 4.4 dmac control and st atus register (dcsr) map offset symbol register name 0000h bus_mode bus mode register 0004h tx_poll_demand transmit poll demand register 0008h rx_poll_demand receive poll demand register 000ch rx_ base_addr receive li st base address register 0010h tx_base_addr transmit li st base address register 0014h dmac_status dma controller status register 0018h dmac_control dma controller control (operation mode) register 001ch dmac_intr_ena dma controller interrupt enable register 0020h miss_frame_cnt r missed frame counter (rx only) 0024h ? 004ch reserved reserved for future expansion 0050h cur_tx_buf_addr current transmit buffer address 0054h cur_rx_buf_addr current receive buffer address 0058h ? 007ch reserved reserved for future expansion
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 105 revision 1.6 (07-18-11) datasheet 4.3.1 bus mode register (bus_mode) this register establishes the bus operating modes for the dmac. offset: 0000h size: 32 bits bits description type default 31:21 reserved ro - 20 descriptor byte ordering (dbo) when set, the device operates in big-endian mode for descriptors. in big- endian mode descriptor byte lanes 0-3 and 1-2 are swapped. csr bit positions within each byte are not changed. this bit should be cleared to ?0? for normal operation. r/w 0b 19:14 reserved ro - 13:8 programmable burst length (pbl) indicates the maximum number of dwords to be transferred in one dma transaction. this will be the maximum value that is used in a single block read/write. the dmac will always a ttempt to burst transfer the length specified in the pbl each time it starts a burst transfer. pbl can be programmed with permissible va lues of 1, 2, 4, 8, 16 and 32. any other value will result in undefined behavior. note: pci bursts are always 16 cycles, r egardless of the value in this field. r/w 001000b 7 big-endian/little-endian (ble) specifies the byte ordering for data buffers. when set, the dmac operates in big-endian mode when accessing data buffers in host memory. in big- endian mode buffer byte lanes 0-3 and 1-2 are swapped. this bit should be cleared to ?0? for normal operation. r/w 0b 6:2 descriptor skip length (dsl) specifies the number of dwords to skip between two unchained descriptors. r/w 00000b 1 bus arbitration (bar) when this bit is set the rx dma op erations are given priority while guarantying tx at least one grant in between consecutive rx packets. when cleared, the arbitration ratio is dictated by the bus_cfg[26:25] field. r/w 0b 0 software reset (srst) when this bit is set, the dmac and mac are reset. this is a self-clearing bit. note: it will take up to 120ns for the srst to complete r/w/sc 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 106 smsc lan9420/lan9420i datasheet 4.3.2 transmit poll demand register (tx_poll_demand) this register enables the tx dma engine to check for new descriptors. offset: 0004h size: 32 bits bits description type default 31:0 transmit poll demand (tpd) when written with any value, the dmac will check for frames to be transmitted. if no descriptor is availabl e, the transmit process returns to the suspended state and bit 2 of the dmac _status register (transmit buffer unavailable - tu) is not asserted. a write to this register is only effective if the transmit process is in the suspended state. a read of this register will timeout and invalid data will be returned. wo -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 107 revision 1.6 (07-18-11) datasheet 4.3.3 receive poll demand re gister (rx_poll_demand) this register enables the rx dmac to check for new descriptors. offset: 0008h size: 32 bits bits description type default 31:0 receive poll demand (rpd) when written with any value, the dmac will check for receive descriptors. if no descriptors are available, the re ceive process returns to the suspended state and bit 7 of the dmac_status r egister (receive buffer unavailable - ru) is not set. a write to this register is only effective if the receive process is in the suspended state. a read of this register will timeout and invalid data will be returned. wo -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 108 smsc lan9420/lan9420i datasheet 4.3.4 receive list base address register (rx_base_addr) this register specifies the start address of th e receive buffer list. rx _base_addr must be 4-dword (16 byte) aligned (e.g. reserved address bits 3:0 must be 0). offset: 000ch size: 32 bits bits description type default 31:4 start of receive list (srl) this field points to the start of the receive buffer descriptor list. the descriptor list resides in the host memory. writing this register is only valid when the rx dma engine is in the stopped state. when stopped, this register must be written before the start command is given. r/w 28?h0 3:0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 109 revision 1.6 (07-18-11) datasheet 4.3.5 transmit list base a ddress register (tx_base_addr) this register specifies the start address of the tr ansmit buffer list. tx_base_addr must be 4-dword (16 byte) aligned (e.g. reserved address bits 3:0 must be 0). offset: 0010h size: 32 bits bits description type default 31:4 start of transmit list (stl) this field points to the start of the transmit buffer descriptor list. the descriptor list resides in the host memory. writing this register is only valid when the tx dma engine is in the stopped state. when stopped, this register must be written before the start command is given. r/w 28?h0 3:0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 110 smsc lan9420/lan9420i datasheet 4.3.6 dma controller status register (dmac_status) this register contains all of the st atus bits that the dmac reports to the host system. most of the fields in this register will cause an interrupt. status can be checked as part of an interrupt service routine, or by polling. dmac interrupts can be ma sked in the dmac_intr_ena register. offset: 0014h size: 32 bits bits description type default 31:23 reserved ro - 22:20 transmit process state (ts) this read-only field indicates the stat e of the transmit process. this field does not generate an interrupt. the ts field is encoded as follows: ro 000b 19:17 receive process state (rs) this read-only field indicates the state of the receive process. this field does not generate an interrupt. the rs field is encoded as follows: ro 000b 16 normal interrupt summary (nis) this bit is the logical or of other bi ts within this register. only unmasked bits affect this register. below is the list of bits: dmac_status[0]: transmit interrupt (ti) dmac_status[2]: transmit buffer unavailable (tu) dmac_status[6]: receive interrupt (ri) r/wc 0b state description 000 stopped - reset or stop command issued 001 running - fetching the transmit descriptor 010 running - waiting for the end of transmission 011 running - reading the data from memory and queuing into tx fifo 100 reserved 101 reserved 110 suspended - unavailable transmit descriptor 111 running - closing the transmit descriptor state description 000 stopped - reset or stop receive command 001 running - fetching the receive descriptor 010 running - checking for end of receive packet before prefetch of next descriptor 011 running - waiting for receive packet 100 suspended - unavailable receive descriptor 101 running - closing receive descriptor 110 running - flushing the current frame from the receive buffer because of unavailable receive buffer 111 running - queuing the receive frame from the receive buffer into the host memory
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 111 revision 1.6 (07-18-11) datasheet 15 abnormal interrupt summary (ais) this bit is the logical or of other bi ts within this register. only unmasked bits affect this register. below is the list of bits: dmac_status[1]: transmit process stopped (tps) dmac_status[7]: receive buffer unavailable (ru) dmac_status[8]: receive process stopped (rps) r/wc 0b 14:10 reserved ro - 9 receive watchdog timeout (rwt) a receive watchdog timeout occurs when the length of the receiving frame is greater than 2048 bytes through 2560 bytes. r/wc 0b 8 receive process stopped (rps) asserted when the receive process enters the stopped state. r/wc 0b 7 receive buffer unavailable (ru) indicates that the next de scriptor in the receive list is owned by the host and cannot be acquired by the dma co ntroller. the reception process is suspended. to resume processing receive descriptors, the host should change the ownership of the descriptor and issue a receive poll demand command. if no receive poll demand is issued, the reception process resumes when the next recognized incoming frame is received. after the first assertion, ru is not as serted for any subsequent ?not owned? receive descriptor fetches. ru is set only when the previous receive descriptor was owned by the dma controller. ru remains asserted until it is cleared by software. r/wc 0b 6 receive interrupt (ri) indicates the completion of the fram e reception. specific frame status information has been posted in the descriptor. the reception process remains in the running state. r/wc 0b 5:3 reserved ro - 2 transmit buffer unavailable (tu) indicates that the next descriptor in the transmit list is owned by the host system and cannot be acqui red by the dma controller. the transmission process is suspended (bits [22:20]). to resume processing transmit descriptors, the ownership bit in the descr iptor should be set, indicating that the dma controller now owns the buffer and then a transmit poll demand command should be issued. r/wc 0b 1 transmit process stopped (tps) set when the transmit process enters the stopped state. r/wc 0b 0 transmit interrupt (ti) indicates that a frame transmission wa s completed and tdes1 [31] is set in the first descriptor indicating that the tx descriptor has been updated. r/wc 0b bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 112 smsc lan9420/lan9420i datasheet 4.3.7 dma controller control (opera tion mode) register (dmac_control) this register establishes the rx and tx operating modes and commands. this should be the last dcsr written as part of initialization. offset: 0018h size: 32 bits bits description type default 31:23 reserved ro - 22 reserved r/w 0b 21 must be one (mbo) this bit must be set to ?1? for normal device operation. r/w 0b 19:16 reserved ro - 15:14 reserved r/w 00b 13 start/stop transmission command (st) when set, the transmission process is placed in the running state, and the dmac checks the transmit list at t he current position for a frame to be transmitted. descriptor acquisition is attempted either from the current position in the list, which is the transmit list base address set by tx_base_addr, or from the position retained when the transmit process was previously stopped. if no descriptor can be acquired, the transmit process enters the suspended state. if the current de scriptor is not owned by the dma controller, the transmission process enters the susp ended state and the transmit buffer unavailable (dmac_status bit [2]) is set. the start transmission command is effective only when the transmission process is stopped. if the command is issued before setting the tx_base_addr, then the dma controller?s behavior will be undefined. when reset, the transmission process is placed in the stopped state after completing the transmission of the current frame. the next descriptor position in the transmit list is saved, and becomes the current position when transmission is restarted. the stop transmission command is effective only when the transmission process is in either running or suspended state. r/w 0b 12:3 reserved ro - 2 operate on second frame (osf) when set, this bit instructs the dma controller to process a second frame of transmit data even before status fo r the first frame is obtained. this bit affects the dma controller but not the mil. r/w 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 113 revision 1.6 (07-18-11) datasheet 1 start/stop receive (sr) when set, the receive process is placed in the running state. the dma controller attempts to acquire the descriptor from the receive list and process incoming frames. descriptor acquisition is attempted fr om the current position in the list, which is the address set by the rx_base_addr or the position retained when the receive process was previously stopped. if no descriptor is owned by the dma controller, the receive process enters the suspended state and the receive buffer unavailable (dmac_status bit [7]) is set. the start reception command is effective only when the reception process has stopped. if the command wa s issued before setting the rx_base_addr, the dma controller?s behavior will be undefined. when cleared, the receive process enters t he stopped state after completing the reception of the current frame. the ne xt descriptor position in the receive list is saved, and becomes the curren t position after the receive process is restarted. the stop reception command is effective only when the receive process is in the running or suspended state. note: in order to successfully enable the receive path, the rx dmac must be enabled (by setting sr) prior to enabling the receiver (by setting the rxen bit of the mac control register (mac_cr) ). note: in order to successfully disable t he receive path, the receiver must be disabled (by clearing the rxen bit of the mac control register (mac_cr) ) prior to disabling the rx dmac (by clearing sr). otherwise, rx dma will not stop (dmac_status will continue to show the receive process state (rs) as running and receive process stopped (rps) does not assert). r/w 0b 0 reserved ro - bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 114 smsc lan9420/lan9420i datasheet 4.3.8 dma controller interrupt enable register (dmac_intr_ena) this register enables the dmac interrupts reported in the dmac_status register. setting a bit to 1 enables the corresponding interrupt. after a hardwa re or software reset, all interrupts are disabled. offset: 001ch size: 32 bits bits description type default 31:17 reserved ro - 16 normal interrupt summa ry enable (nis_en) when set, normal interrupt is enabled. when reset, no normal interrupt is enabled. this bit enables the following bits: dmac_status[0]: transmit interrupt (ti) dmac_status[2]: transmit buffer unavailable (tu) dmac_status[6]: receive interrupt (ri) r/w 0b 15 abnormal interrupt su mmary enable (ais_en) when set, abnormal interrupt is enabled. when reset, no abnormal interrupt is enabled. this bit enables the following bits: dmac_status[1]: transmit process stopped (tps) dmac_status[5]: reserved dmac_status[7]: receive buffer unavailable (ru) dmac_status[8]: receive process stopped (rps) r/w 0b 14 reserved r/w 0b 13:11 reserved ro - 10 reserved r/w 0b 9 receive watchdog timeout (rwt_en) the receive watchdog timeout is enabled only when this bit and the abnormal interrupt summary enable bit (bit [15]) are set. r/w 0b 8 receive process stopped (rps_en) the receive process stopped interrupt is enabled only when this bit and the abnormal interrupt summary enable bit (bit [15]) are set. r/w 0b 7 receive buffer unavailable (ru_en) the receive buffer unavailable interrupt is enabled only when this bit and the abnormal interrupt summary enable bit (bit [15]) are set. r/w 0b 6 receive interrupt (ri_en) the receive interrupt is enabled only when this bit and the abnormal interrupt summary enable bit (bit [15]) are set. r/w 0b 5 reserved r/w 0b 4:3 reserved ro - 2 transmit buffer unavailable (tu_en) the transmit buffer unavailable interrupt is enabled only when this bit and the normal interrupt summary en able bit (bit [16]) are set. r/w 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 115 revision 1.6 (07-18-11) datasheet 1 transmit process stopped (tps_en) the transmit process stopped interrupt is enabled only when this bit and the abnormal interrupt summary enable bit (bit [15]) are set. r/w 0b 0 transmit interrupt (ti_en) the transmit interrupt is enabled only when this bit and the normal interrupt summary enable bit (bit [16]) are set. r/w 0b bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 116 smsc lan9420/lan9420i datasheet 4.3.9 missed frame and buffer overfl ow counter reg (miss_frame_cntr) the dmac maintains two counters to track the num ber of missed frames dur ing a receive operation. the miss_frame_cntr register reports the current va lue of these counters and their overflow bits. offset: 0020h size: 32 bits bits description type default 31:29 reserved ro - 28 mil rx fifo full coun ter overflow (mil_over) overflow bit for the mil_fifo_full c ounter. this bit is automatically cleared on a read. rc 0b 27:17 mil rx fifo full counter (mil_fifo_full) this field indicates the number of fr ames missed due a mil rx fifo full condition. this counter is automatically cleared on a read. rc 000h 16 rx buffer unavailable coun ter overflow (unav_over) overflow bit for the rx_buff_unav co unter. this bit is automatically cleared on a read. rc 0b 15:0 rx buffer unavailable counter (rx_buff_unav) this field indicates the number of frames missed due to receive buffers being unavailable. this counter is incremented each time the dmac discards an incoming frame. this counter is automatically cleared on a read. rc 0000h
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 117 revision 1.6 (07-18-11) datasheet 4.3.10 current transmit buffer address register (tx_buff_addr) this register points to the current tran smit buffer address being read by the dmac. offset: 0050h size: 32 bits bits description type default 31:0 tx_buff_addr this field contains the pointer to t he current buffer address pointer used by the dmac during tx operation. ro 32?h0
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 118 smsc lan9420/lan9420i datasheet 4.3.11 current receive buffer ad dress register (rx_buff_addr) this register points to the current rece ive buffer address being read by the dmac. offset: 0054h size: 32 bits bits description type default 31:0 rx_buff_addr this field contains the pointer to t he current buffer address pointer used by the dmac during rx operation. ro 32?h0
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 119 revision 1.6 (07-18-11) datasheet 4.4 mac control and status registers (mcsr) table 4.5 lists the registers contained in this section. table 4.5 mac control and status register (mcsr) map offset symbol register name 0080h mac_cr mac control 0084h addrh mac address high 0088h addrl mac address low 008ch hashh multicast hash table high 0090h hashl multicast hash table low 0094h miiaddr mii address 0098h miidata mii data 009ch flow flow control 00a0h vlan1 vlan1 tag 00a4h vlan2 vlan2 tag 00a8h wuff wakeup frame filter 00ach wucsr wakeup control and status 00b0h coe_cr checksum offload engine control 00b4h - 00bch reserved reserved for future use
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 120 smsc lan9420/lan9420i datasheet 4.4.1 mac control register (mac_cr) this register establishes the rx and tx operating modes and inclu des controls for address filtering and packet filtering. offset: 0080h size: 32 bits bits description type default 31 receive all mode (rxall) when set, all incoming packets will be received and passed on to the address filtering function for processing of the selected filtering mode on the received frame. address filtering then occurs and is reported in receive status. when reset, only frames that pa ss destination address filtering will be sent to the application. r/w 0b 30-24 reserved ro - 23 disable receive own (rcvown) when set, the mac disables the reception of frames when txen is asserted. the mac blocks the transmitt ed frame on the receive path. when reset, the mac receives all packets the phy gives, including those transmitted by the mac.this bit should be reset when the full duplex mode bit is set. r/w 0b 22 reserved ro - 21 loopback operation mode (loopbk) selects the loop back operation modes for the mac. this is only for full duplex mode 0 - normal. no feedback 1 - internal through mii in internal loopback mode, the tx frame is received by the internal mii interface, and sent back to the mac without being sent to the phy. note: when enabling or disabling the loopback mode it can take up to 10 s for the mode change to occur. the transmitter and receiver must be stopped and disabled when modifying the loopbk bit. the transmitter or receiver should not be enabled within10 s of modifying the loopbk bit. r/w 0b 20 full duplex mode (fdpx) when set, the mac operates in full-d uplex mode, in which it can transmit and receive simultaneously. r/w 0b 19 pass all multicast (mcpas) when set, indicates that all incoming frames with a mult icast destination address (first bit in the destination addr ess field is 1) are received. incoming frames with physical address (individual address/unicast) destinations are filtered and received only if the address matches the mac address. r/w 0b 18 promiscuous mode (prms) when set, indicates that any incoming frame is received regardless of its destination address. r/w 1b 17 inverse filtering (invfilt) when set, the address check function operates in inverse filtering mode. this is valid only during perfect filtering mode. r/w 0b 16 pass bad frames (passbad) when set, all incoming frames that passed address filtering are received, including runt frames and collided frames. r/w 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 121 revision 1.6 (07-18-11) datasheet 15 hash only filtering mode (ho) when set, the address check function operates in the imperfect address filtering mode both for physical and multicast addresses r/w 0b 14 reserved ro - 13 hash/perfect filtering mode (hpfilt) when reset (0), lan9420/lan9420i will implement a perfect address filter on incoming frames according the a ddress specified in the mac address register. when set (1), the address check functi on does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. if the hash only filtering mode (ho) bit is set (1), then the physical (ia) are imperfect filtered too. if the hash only filtering mode (ho) bit is reset (0), then the ia addresses are perfect address filtered according to the mac address register. r/w 0b 12 late collision control (lcoll) when set, enables retransmission of the collided frame even after the collision period (late collision). w hen reset, the mac disables frame transmission on a late collision. in any case, the late collision status is appropriately updated in the transmit packet status. r/w 0b 11 disable broadcast frames (bcast) when set, disables the reception of broadcast frames. when reset, forwards all broadcast frames to the application. note: when wake-up frame detection is enabled via the wuen bit of the wakeup control and status register (wucsr) , a broadcast wake-up frame will wake-up the device despite the state of this bit. r/w 0b 10 disable retry (disrty) when set, the mac attempts only one transmission. when a collision is seen on the bus, the mac ignores the current frame and goes to the next frame and a retry error is reported in the transmit status. when reset, the mac attempts 16 transmissions before signaling a retry error. r/w 0b 9 reserved ro - 8 automatic pad st ripping (padstr) when set, the mac strips the pad field on all incoming frames, if the length field is less than 46 bytes. the fcs field is also stripped, since it is computed at the transmitting station based on the data and pad field characters, and is invalid for a received frame that has had the pad characters stripped. receive frames with a 46-byte or greater length field are passed to the application unmodified (fcs is not stripped). when reset, the mac passes all incoming frames to host memory unmodified. note: when padstr is enabled, the rx checksum offload engine must be disabled (rx_coe_en bit of the checksum offload engine control register (coe_cr) ) and vice versa. these functions cannot be enabled simultaneously. r/w 0b bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 122 smsc lan9420/lan9420i datasheet 7-6 backoff limit (bolmt) the bolmt bits allow the user to set its back-off limit in a relaxed or aggressive mode. according to ieee 802.3, the mac has to wait for a random number [r] of slot-times ( note 4.4 ) after it detects a collision, where: (eq.1)0 < r < 2 k the exponent k is dependent on how many times the current frame to be transmitted has been retried, as follows: (eq.2)k = min (n, 10) where n is the current number of retries. if a frame has been retried three times, then k = 3 and r= 8 slot-times maximum. if it has been retried 12 times, then k = 10, and r = 1024 slot- times maximum. an lfsr (linear feedback shift register) 20-bit counter emulates a 20bit random number generator, from which r is obtained. once a collision is detected, the number of the current re try of the current frame is used to obtain k (eq.2). this value of k transl ates into the number of bits to use from the lfsr counter. if the value of k is 3, the mac takes the value in the first three bits of the lfsr counter and uses it to count down to zero on every slot-time. this effectively c auses the mac to wait eight slot-times. to give the user more flexibility, the bolmt value forces the number of bits to be used from the lfsr counter to a predetermined value as in the table below. thus, if the value of k = 10, the mac will look at the bolmt if it is 00, then use the lower ten bits of the lfsr counter for the wait countdown. if the bolmt is 10, then it will only use the value in the first four bits for the wait countdown, etc. note 4.4 slot-time = 512 bit times. (see ieee 802.3 spec., secs. 4.2.3.25 and 4.4.2.1) r/w 00b 5 deferral check (dfchk) when set, enables the deferral check in the mac. the mac will abort the transmission attempt if it has defe rred for more than 24,288 bit times. deferral starts when the transmitter is ready to transmit, but is prevented from doing so because the crs is active. defer time is not cumulative. if the transmitter defers for 10,000 bit ti mes, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. when reset, the deferral check is disabled in the mac and the mac defers indefinitely. r/w 0b 4 reserved ro - 3 transmitter enable (txen) when set, the mac?s transmitter is enab led and it will transmit frames from the buffer onto the cable. when reset, the mac?s transmitter is disabled and will not transmit any frames. r/w 0b bits description type default bolmt value # bits used from lfsr counter 2?b00 10 2?b01 8 2?b10 4 2?b11 1
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 123 revision 1.6 (07-18-11) datasheet 2 receiver enable (rxen) when set (1), the mac?s receiver is enabled and will receive frames from the internal phy. when reset, the mac?s receiver is disabled and will not receive any frames from the internal phy. note: in order to successfully enable the receive path, the rx dmac must be enabled by setting the start/stop receive bit (sr) bit of the dma controller control (operation mode) register (dmac_control) prior to enabling the receiver (by setting rxen). note: in order to successfully disable t he receive path, the receiver must be disabled (by clearing rxen) prior to disabling the rx dmac (by clearing the start/stop receive bit (sr) bit of the dma controller control (operation mode) register (dmac_control) ). otherwise, rx dma will not stop (dmac_status will continue to show the receive process state (rs) as running and receive process stopped (rps) does not assert). r/w 0b 1-0 reserved ro - bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 124 smsc lan9420/lan9420i datasheet 4.4.2 mac address high register (addrh) this register contains the upper 16 bits of the physical address of the mac, where addrh[15:8] is the 6 th octet of the rx frame. offset: 0084h size: 32 bits bits description type default 31:16 reserved ro - 15-0 physical address [47:32] this field contains the upper 16 bits (47:32) of the physical address of the lan9420/lan9420i device. r/w ffffh
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 125 revision 1.6 (07-18-11) datasheet 4.4.3 mac address low register (addrl) this register contains the lower 32 bits of the ph ysical address of the mac, where addrl[7:0] is the first octet of the ethernet frame. table 4.6 below illustrates the byte ordering of the addrl and addrh registers with respect to the reception of the ethe rnet physical address. as an example, if the desired ethernet physical address is 12-34-56-78-9a-bc, the addrl and addrh registers would be programmed as shown in figure 4.2 . the values required to automatically load this configuration from the eeprom are shown in section 3.3.5.1, "eeprom format," on page 31 . offset: 0088h size: 32 bits bits description type default 31:0 physical address [31:0] this field contains the lower 32 bits (3 2:0) of the physical address of this mac device. r/w 32?hf table 4.6 addrl, addrh byte ordering addrl, addrh order of reception on ethernet addrl[7:0] 1 st addrl[15:8] 2 nd addrl[23:16] 3 rd addrl[31:24] 4 th addrh[7:0] 5 th addrh[15:8] 6 th figure 4.2 exam ple addrl, addrh address ordering 0x12 0 7 0x34 8 15 0x56 16 23 0x78 24 31 addrl 0x9a 0 7 0xbc 8 15 addrh xx 16 23 xx 24 31
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 126 smsc lan9420/lan9420i datasheet 4.4.4 multicast hash table high register (hashh) the 64-bit multicast table is used for group address fi ltering. for hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the hash table. the most significant bit determines the register to be used (h i/low), while the other five bits determine the bit within the register. a value of 00000 selects bit 0 of the multicast hash table lo register and a value of 11111 selects the bit 31 of the multicast hash table hi register. if the corresponding bit is 1, then the multicast frame is accepted. otherwise, it is rejected. if the ?pass all multicast? (mcpas) bit is set (1), then all multicast frames are accepted regardless of the multicast hash values. the multicast hash table hi register contains the higher 32 bits of the hash table and the multicast hash table low register contains the lower 32 bits of the hash table. offset: 008ch size: 32 bits bits description type default 31-0 upper 32 bits of the 64-bit hash table r/w 32?h0
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 127 revision 1.6 (07-18-11) datasheet 4.4.5 multicast hash table low register (hashl) this register defines the lower 32-bits of the multicast hash table. please refer to section 4.4.4, "multicast hash table high register (hashh)," on page 126 for further details. offset: 0090h size: 32 bits bits description type default 31-0 lower 32 bits of the 64-bit hash table r/w 32?h0
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 128 smsc lan9420/lan9420i datasheet 4.4.6 mii access regi ster (mii_access) this register is used to control the management cycles to the internal phy. offset: 0094h size: 32 bits bits description type default 31-16 reserved ro - 15-11 phy address for every access to this register, this field must be set to 00001b. r/w 00000b 10-6 mii register index (miirinda) these bits select the desired mii register in the phy. r/w 00000b 5-2 reserved ro - 1 mii write (miiwnr) setting this bit tells the phy that th is will be a write operation using the mii data register. if this bit is not set, this will be a read operation, packing the data in the mii data register. r/w 0b 0 mii busy (miibzy) this bit must be polled to determine when the mii register access is complete. this bit must read a logical 0 before writing to this register or to the mii data register. the lan driver software must set (1) this bit in order for the host system to read or wr ite any of the mii phy registers. during a mii register access, this bi t will be set, signifying a read or write access is in progress. the mii data register must be kept valid until the mac clears this bit during a phy write operation. the mii data register is invalid until the mac has cleared this bit during a phy read operation. r/w/sc 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 129 revision 1.6 (07-18-11) datasheet 4.4.7 mii data register (mii_data) this register contains either the data to be written to the phy register specified in the mii access register, or the read data from the phy register whose index is specified in the mii access register. refer to section 4.4.6, "mii access regi ster (mii_access)," on page 128 for further details. note: the miibzy bit in the mii_access register mu st be cleared when writing to this register. offset: 0098h size: 32 bits bits description type default 31-16 reserved ro - 15-0 mii data this contains the 16-bit value read from the phy read operation or the 16- bit data value to be written to the phy before an mii write operation. r/w 0000h
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 130 smsc lan9420/lan9420i datasheet 4.4.8 flow control register (flow) this register is used to control the generation and reception of the control frames by the mac?s flow control block. a write to this register with busy bit se t to 1 will trigger the flow control block to generate a control frame. before writing to this register, th e application has to make sure that the busy bit is not set. offset: 009ch size: 32 bits bits description type default 31:16 pause time (fcpt) this field indicates the value to be used in the pause time field in the control frame. r/w 0000h 15:3 reserved ro - 2 pass control frames (fcpass) when set, the mac sets the packet filter bit in the receive packet status to indicate to the application that a vali d pause frame has been received. the application must accept or discar d a received frame based on the packet filter control bit. the mac receiv es, decodes and performs the pause function when a valid pause frame is received in full-duplex mode and when flow control is enabled (fce bit set). when reset, the mac resets the packet filter bit in the receive packet status. the mac always passes the data of all frames it receives (including flow control frames) to the applic ation. frames that do not pass address filtering, as well as frames with errors, are pass ed to the application. the application must discard or retain the received frame?s data based on the received frame?s status field. filtering modes (promiscuous mode, for example) take precedence over the fcpass bit. r/w 0b 1 flow control enable (fcen) when set, enables the mac flow c ontrol function. the mac decodes all incoming frames for control frames; if it receives a valid control frame (pause command), it disables the transmitter for a specified time (decoded pause time x slot time). when reset, the mac flow control function is disabled; the mac does not decod e frames for control frames. note: flow control is applicable when the mac is set in full duplex mode. r/w 0b 0 flow control busy (fcbsy) in full-duplex mode this bit should read logical 0 before writing to the flow control register. to init iate a pause control frame, the host system must set this bit to 1. during a transfer of control frame, this bit continues to be set, signifying that a frame transmissi on is in progress. after the pause control frame?s transmission is complete, the mac resets to 0. r/w 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 131 revision 1.6 (07-18-11) datasheet 4.4.9 vlan1 tag re gister (vlan1) this register contains the vlan tag field to iden tify vlan1 frames. for vlan frames the legal frame length is increased from 1518 bytes to 1522 bytes. the rxcoe also uses this register to determine the protocol value to use to indicate the existence of a vlan tag. when using the rxcoe, this value may only be changed if the rx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the mac is disabled and the mil is empty. offset: 00a0h size: 32 bits bits description type default 31:16 reserved ro - 15:0 vlan1 tag identifier (vti1) this contains the vlan tag field to identify the vlan1 frames. this field is compared with the 13 th and 14 th bytes of the incoming frames for vlan1 frame detection. r/w ffffh
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 132 smsc lan9420/lan9420i datasheet 4.4.10 vlan2 tag re gister (vlan2) this register contains the vlan tag field to iden tify vlan2 frames. for vlan frames the legal frame length is increased from 1518 bytes to 1522 bytes. offset: 00a4h size: 32 bits bits description type default 31:16 reserved ro - 15:0 vlan2 tag identifier (vti2) this contains the vlan tag field to identify the vlan2 frames. this field is compared with the 13 th and 14 th bytes of the incoming frames for vlan2 frame detection. r/w ffffh
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 133 revision 1.6 (07-18-11) datasheet 4.4.11 wakeup frame filter (wuff) this register is used to c onfigure the wakeup frame filter. offset: 00a8h size: 32 bits bits description type default 31:0 wakeup frame filter (wff) the wakeup frame filter is configur ed through this register using an indexing mechanism. following a reset, the mac loads the first value written to this loca tion to the first dword in t he wakeup frame filter (filter 0 byte mask). the second value written to this location is loaded to the second dword in the wakeup frame filter (filter 1 byte mask) and so on. once all eight dwords have been wri tten, the internal pointer will once again point to the first entry and the filter entries can be modified in the same manner. similarly, eight dwords should be read sequentially to obtain the values stored in the wff. note: this register should be read and written using eight consecutive dword operations. failure to read or write the entire contents of the wff may cause the internal read/write pointers to be left in a position other than pointing to the first entry. r/w 0000_0000h
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 134 smsc lan9420/lan9420i datasheet 4.4.12 wakeup control and st atus register (wucsr) this register contains data pertaining to th e mac?s remote wakeup status and capabilities. offset: 00ach size: 32 bits bits description type default 31:10 reserved ro - 9 global unicast enable (gue) when set, the mac wakes up from power-saving mode on receipt of a global unicast frame. a global unicast frame has the mac address [0] bit set to 0. 0b 8:7 reserved ro - 6 remote wakeup frame received (wufr) the mac sets this bit upon receiving a valid remote wakeup frame. r/wc 0b 5 magic packet received (mpr) the mac sets this bit upon receiving a valid magic packet. r/wc 0b 4-3 reserved ro - 2 wakeup frame enable (wake_en) when set, remote wakeup mode is enabled and the mac is capable of detecting wakeup frames as programmed in the wakeup frame filter. r/w 0b 1 magic packet enable (mpen) when set, magic packet wakeup mode is enabled. r/w 0b 0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 135 revision 1.6 (07-18-11) datasheet 4.4.13 checksum offload engine control register (coe_cr) this register controls the rx and tx checksum offload engines . offset: 00b0h size: 32 bits bits description type default 31:17 reserved ro - 16 tx checksum offload engi ne enable (tx_coe_en) the coe_en may only be changed if the tx path is disabled. if it is desired to disable the tx_coe_en during run time, it is safe to do so only after the mac is disabled and the mil is empty. 0: the txcoe is bypassed 1: the txcoe is enabled r/w 0b 15:2 reserved ro - 1 rx checksum offload engine mode (rx_coe_mode) this register indicates whether the coe will check for vlan tags or a snap header prior to beginning its chec ksum calculation. in its default mode, the calculation will always begin 14 bytes into the frame. the coe_mode may only be changed if th e rx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the mac is disabled and the mil is empty. 0: begin checksum calculation after first 14 bytes of ethernet frame 1: begin checksum calculation at start of l3 packet by adjusting for vlan tags and/or snap header. r/w 0b 0 rx checksum offload engine enable (rx_coe_en) the coe_en may only be changed if the rx path is disabled. if it is desired to disable the coe_en during run time, it is safe to do so only after the mac is disabled and the mil is empty. 0: the rxcoe is bypassed 1: the rxcoe is enabled note: when the rxcoe is enabled, automatic pad stripping must be disabled (padstr bit of the mac control register (mac_cr) ) and vice versa. these functions cannot be enabled simultaneously. r/w 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 136 smsc lan9420/lan9420i datasheet 4.5 phy registers the phy registers are not memory mapped. these registers are acce ssed indirectly through the mac via the mii_access and mii_data registers. an index is used to access individual phy registers. phy register indexes are shown in table 4.7, "phy control and status registers" below. note: the nasr ( not affected by software reset) designation is only applicable when bit 15 of the phy basic control re gister (reset) is set. table 4.7 phy control and status registers index (in decimal) register name 0 basic control register 1 basic status register 2 phy identifier 1 3 phy identifier 2 4 auto-negotiation adve rtisement register 5 auto-negotiation link partner ability register 6 auto-negotiation expansion register 17 mode control/status register 18 special modes 27 control / status indication register 29 interrupt source register 30 interrupt mask register 31 phy special control/status register
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 137 revision 1.6 (07-18-11) datasheet 4.5.1 basic control register index (in decimal): 0 size: 16 bits bits description type default 15 phy soft reset 1 = phy software reset. bit is self-clearing. when setting this bit do not set other bits in this register. r/w/sc 0b 14 loopback 1 = loopback mode, 0 = normal operation r/w 0b 13 speed select 1 = 100mbps, 0 = 10mbps. ignored if auto negotiation is enabled (0.12 = 1). r/w 1b 12 auto-negotiation enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 0 = disable auto-negotiate process. r/w 1b 11 power down 1 = general power-down mode, 0 = normal operation note: for maximum power savings, auto-negotiation should be disabled before enabling the general power-down mode. r/w 0b 10 reserved ro - 9 restart auto-negotiate 1 = restart auto-negotiate process 0 = normal operation. bit is self-clearing. r/w/sc 0b 8 duplex mode 1 = full duplex, 0 = half duplex. ignor ed if auto negotiation is enabled (0.12 = 1). r/w 0b 7 collision test 1 = enable col test, 0 = disable col test r/w 0b 6:0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 138 smsc lan9420/lan9420i datasheet 4.5.2 basic status register index (in decimal): 1 size: 16 bits bits description type default 15 100base-t4 1 = t4 able, 0 = no t4 ability ro 0b 14 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability. ro 1b 13 100base-tx half duplex 1 = tx with half duplex, 0 = no tx half duplex ability. ro 1b 12 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability ro 1b 11 10base-t half duplex 1 = 10mbps with half duplex 0 = no 10mbps with half duplex ability ro 1b 10:6 reserved ro - 5 auto-negotiate complete 1 = auto-negotiate process completed 0 = auto-negotiate process not completed ro 0b 4 remote fault 1 = remote fault condition detected 0 = no remote fault ro/lh 0b 3 auto-negotiate ability 1 = able to perform auto-negotiation function 0 = unable to perform auto- negotiation function ro 1b 2 link status 1 = link is up, 0 = link is down ro/ll 0b 1 jabber detect 1 = jabber condition detected 0 = no jabber condition detected ro/lh 0b 0 extended capabilities 1 = supports extended capabilities re gisters 0 = does not support extended capabilities registers. ro 1b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 139 revision 1.6 (07-18-11) datasheet 4.5.3 phy identifier 1 index (in decimal): 2 size: 16 bits bits description type default 15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui), respectively. r/w 0007h
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 140 smsc lan9420/lan9420i datasheet 4.5.4 phy identifier 2 index (in decimal): 3 size: 16 bits bits description type default 15:10 phy id number b assigned to the 19th through 24th bits of the oui. r/w c0c3h 9:4 model number six-bit manufacturer?s model number. r/w 3:0 revision number four-bit manufacturer?s revision number. r/w
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 141 revision 1.6 (07-18-11) datasheet 4.5.5 auto negotiation advertisement note 4.5 when both symmetric pause and asymmetric pause support are advertised (value of 11), the device will only be configured to, at most, one of the two settings upon auto- negotiation completion. index (in decimal): 4 size: 16 bits bits description type default 15 reserved r/w 0b 14 reserved ro - 13 remote fault 1 = remote fault detected, 0 = no remote fault r/w 0b 12 reserved r/w - 11:10 pause operation (see note 4.5 ) 00 no pause 01 symmetric pause 10 asymmetric pause 11 advertise support for both symme tric pause and asymmetric pause r/w 00b 9 reserved r/w 0b 8 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability r/w 1b 7 100base-tx 1 = tx able, 0 = no tx ability r/w 1b 6 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability r/w 1b 5 10base-t 1 = 10mbps able, 0 = no 10mbps ability r/w 1b 4:0 selector field [00001] = ieee 802.3 r/w 00001b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 142 smsc lan9420/lan9420i datasheet 4.5.6 auto negotiation link partner ability index (in decimal): 5 size: 16 bits bits description type default 15 next page 1 = next page capable, 0 = no next page ability. this device does not support next page ability. ro 0b 14 acknowledge 1 = link code word received from partner 0 = link code wo rd not yet received ro 0b 13 remote fault 1 = remote fault detected, 0 = no remote fault ro 0b 12 reserved ro - 11:10 pause operation 00 no pause supported by partner station 01 symmetric pause supported by partner station 10 asymmetric pause suppor ted by partner station 11 both symmetric pause and asymmetric pause supported by partner station ro 00b 9 100base-t4 1 = t4 able, 0 = no t4 ability ro 0b 8 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability ro 0b 7 100base-tx 1 = tx able, 0 = no tx ability ro 0b 6 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability ro 0b 5 10base-t 1 = 10mbps able, 0 = no 10mbps ability ro 0b 4:0 selector field [00001] = ieee 802.3 ro 00001b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 143 revision 1.6 (07-18-11) datasheet 4.5.7 auto negotiation expansion index (in decimal): 6 size: 16 bits bits description type default 15:5 reserved ro - 4 parallel detection fault 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic ro/lh 0b 3 link partner next page able 1 = link partner has next page ability 0 = link partner does not have next page ability ro 0b 2 next page able 1 = local device has next page ability 0 = local device does not have next page ability ro 0b 1 page received 1 = new page received 0 = new page not yet received ro/lh 0b 0 link partner auto -negotiation able 1 = link partner has auto-negotiation ability 0 = link partner does not have auto-negotiation ability ro 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 144 smsc lan9420/lan9420i datasheet 4.5.8 mode control/status index (in decimal): 17 size: 16 bits bits description type default 15:14 reserved ro - 13 edpwrdown enable the energy detect power-down mode: 0=energy detect power-down is disabled 1=energy detect power-down is enabled r/w 0b 12:2 reserved ro - 1 energyon indicates whether energy is detected. this bit goes to a ?0? if no valid energy is detected within 256ms. reset to ?1? by hardware reset, unaffected by sw reset. ro 1b 0 reserved r/w 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 145 revision 1.6 (07-18-11) datasheet 4.5.9 special modes index (in decimal): 18 size: 16 bits bits description type default 15:8 reserved ro - 7-5 mode phy mode of operation. refer to ta b l e 4 . 8 for more details. r/w nasr 111b 4-0 phyadd phy address. the phy address is used for the smi address. r/w nasr 00001b table 4.8 mode control mode mode definitions default register bit values register 0 register 4 [13,12,8] [8,7,6,5] 000b 10base-t half duplex. auto-n egotiation disabled. 000 n/a 001b 10base-t full duplex. auto-n egotiation disabled. 001 n/a 010b 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 100 n/a 011b 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 101 n/a 100b 100ase-tx half duplex is advertised. auto- negotiation enabled. crs is active during transmit & receive. 110 0100 101b repeater mode. auto -negotiation enabled. 100base-tx half duplex is advertised. crs is active during receive. 110 0100 110b reserved - do not set lan9420/lan9420i in this mode. n/a n/a 111b all capable. auto-negotiation enabled. x1x 1111
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 146 smsc lan9420/lan9420i datasheet 4.5.10 special control/status indications index (in decimal): 27 size: 16 bits bits description type default 15 override automdix_en strap 0 = automdix_en configuration strap enables or disables hp auto mdix. 1 = override automdix_en configuration strap. phy register 27.14 and 27.13 determine mdix function. r/w 0b 14 auto-mdix enable only effective when 27.15=1, otherwise ignored. 0 = disable auto-mdix. 27.13 determines normal or reversed connection. 1 = enable auto-mdix. 27.13 must be set to 0. r/w 0b 13 auto-mdix state only effective when 27.15=1, otherwise ignored. when 27.14 = 0 (manually set mdix state): 0 = no crossover (tpo = output, tpi = input) 1 = crossover (tpo = input, tpi = output) when 27.14 = 1 (automatic mdix ) this bit must be set to 0. do not use the combination 27.15=1, 27.14=1, 27.13=1. r/w 0b 12:11 reserved ro - 10 vcooff_lp forces the receive pll 10m to lock on the reference clock at all times: 0 ? receive pll 10m can lock on reference or line as needed (normal operation) 1 - receive pll 10m is locked on the reference clock. in this mode 10m data packets cannot be received. r/w, nasr 0b 9:5 reserved ro - 4 xpol polarity state of the 10base-t: 0 ? normal polarity 1 ? reversed polarity ro 0b 3:0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 147 revision 1.6 (07-18-11) datasheet 4.5.11 interrupt source flag index (in decimal): 29 size: 16 bits bits description type default 15:8 reserved ro - 7 int7 1= energyon generated, 0 = not source of interrupt ro/lh 0b 6 int6 1= auto-negotiation complete, 0 = not source of interrupt ro/lh 0b 5 int5 1= remote fault detected, 0 = not source of interrupt ro/lh 0b 4 int4 1= link down (link status negated), 0 = not source of interrupt ro/lh 0b 3 int3 1= auto-negotiation lp acknowledge, 0 = not source of interrupt ro/lh 0b 2 int2 1= parallel detection fault, 0 = not source of interrupt ro/lh 0b 1 int1 1= auto-negotiation page received, 0 = not source of interrupt ro/lh 0b 0 reserved ro 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 148 smsc lan9420/lan9420i datasheet 4.5.12 interrupt mask index (in decimal): 30 size: 16 bits bits description type default 15:8 reserved ro - 7:0 mask bits 1 = interrupt source is enabled, 0 = interrupt source is masked r/w 00h
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 149 revision 1.6 (07-18-11) datasheet 4.5.13 phy special control/status note 4.6 bit 6 of this register must be set to ?1? for write operations. index (in decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 autodone auto-negotiation done indication: 0 = auto-negotiation is not done or disabled (or not active) 1 = auto-negotiation is done ro 0 11:5 reserved write as 0000010b, ignore on read. note 4.6 - 4:2 speed indication hcdspeed value: [001b] = 10mbps half-duplex [101b] = 10mbps full-duplex [010b] = 100base-tx half-duplex [110b] = 100base-tx full-duplex ro 000b 1:0 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 150 smsc lan9420/lan9420i datasheet 4.6 pci configuration sp ace csr (config csr) configuration and read back of t he config csr is accomplished by the host processor via the pci bus. these registers assume their default value on assertion of a chip-level reset or when the device power state transitions from d3 to d0. see section 3.7, "power management," on page 74 for details. registers in offsets 00h - 03fh are standard pci header registers, as described in the pci local bus specification revision 3.0. please refer to the specification for further details. register 78h is a pcib specific extension related to power management. the following is the register map for the pci configuration spac e csr (config csr): table 4.9 pci configuration space csr (config csr) address map configuration space offset register name description 00h ? 3fh - standard pci header registers (see table 4.10 on page 151 for details). 40h ? 74h reserved 78h pci_pmc pci power management capabilities register (pci_pmc) 7ch pci_pmcsr pci power management control and status register (pci_pmcsr)
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 151 revision 1.6 (07-18-11) datasheet table 4.10 lists the standard pci header registers that are supported. registers whose initial values for subsystem vendor id and subsystem device id, are confi gured from the eeprom are indicated by ? yes ? in the ?eprom configurable? column. note 4.7 default value is dependent on device revision. note 4.8 bar3?s read back value is fffffc00h after writing ffffffffh. bar4?s read back value is ffffff01h after writing ffffffffh. note 4.9 the subsystem vendor id and subsystem device id can be configured by the serial eeprom. if no eeprom is connected to lan9 420/lan9420i, then the default values in the table are used. table 4.10 standard pci header registers supported configuration space offset register name read/ write default eeprom configurable 00h - 01h vendor id ro 1055h 02h - 03h device id ro e420h 04h - 05h command r/w 00h 06h - 07h status ro, r/wc 0410h 08h revision id ro note 4.7 09h - 0bh class code ro 020000h 0ch cache line size r/w 00h 0dh latency timer r/w 00h 0eh header type ro 00h 0f - 1bh reserved ro 1ch - 1fh bar 3 ( note 4.8 ) (for np-mem mapped 1kbyte) r/w 00000000h (fffffc00h) 20h - 23h bar 4 ( note 4.8 ) (for i/o mapped 256byte) r/w 0000001h (ffffff01h) 24h - 2bh reserved ro 2ch - 2dh subsystem vendor id (ssvid) ( note 4.9 ) ro 1055h yes 2eh - 2fh subsystem device id (ssid) ( note 4.9 ) ro 9420h yes 30h - 33h reserved ro 34h capabilities pointer ro 78h 35h - 3bh reserved ro 3ch interrupt line r/w 00h 3dh interrupt pin ro 01h 3eh min_gnt ro 02h 3fh max_lat ro 04h
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 152 smsc lan9420/lan9420i datasheet 4.6.1 pci power management ca pabilities register (pci_pmc) this register implements the standard capability structure used to define power management features in a pci device. the capabilities structure is documented in the pci bus power management interface specification revision 1.1 . the host uses this register check supported power states and features. note: the format of this register is equivalent to of fsets 3:0 of the power management register block definition as de scribed in the pci bus power management interface specification revision 1.1 . offset: 78h size: 32 bits bits description type default 31 pme support from d3 cold (pme_in_d3c) when this bit is set, lan9420/lan9420i is capable asserting npme from the d3 cold state. when this bit is cleared, the device will not assert npme from the d3 cold state. this bit reflects the setting of the vauxdet input pin. ro note 4.10 30 pme support from d3 hot (pme_in_d3h) this bit is set indicating that lan9420/lan9420i is capable asserting npme from the d3 hot state. ro 1b 29 pme support from d2 (pme_in_d2) this bit is cleared since lan9420/lan9420i does not support the d2 power management state. ro 0b 28 pme support from d1 (pme_in_d1) this bit is cleared since lan9420/lan9420i does not support the d1 power management state. ro 0b 27 pme support from d0 (pme_in_d0) this bit is set indicating that lan9420/lan9420i is capable asserting npme from the d0 state. ro 1b 26 d2 power state support (d2_sup) this bit is cleared since lan9420/lan9420i does not support the d2 power management state. ro 0b 25 d1 power state support (d1_sup) this bit is cleared since lan9420/lan9420i does not support the d1 power management state. ro 0b 24:22 3.3vaux power supply current draw (aux_current) this field indicates the auxiliary power requirements for the lan9420/lan9420i device. this field is dependant on the state of the vauxdet input pin. when vauxdet is cleared, this field is cleared to 000b to indicate that there is no current draw from the 3.3vaux power supply. when vauxdet is set, this field is set to a value of 110b to indicate a current draw of 320ma from the 3.3vaux power supply. ro note 4.10 21 device specific initialization (dsi) this bit returns zero, indica ting that there are no dev ice specific initialization requirements. ro 0b 20 reserved ro 0b 19 pme clock (clk4pme) this bit is cleared to indicate that lan9420/lan9420i does not require the presence of pciclk in order to assert npme. ro 0b
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 153 revision 1.6 (07-18-11) datasheet note 4.10 the default state of this field is dependant on the setting of the vauxdet signal as noted in the description. 18:16 power management specificat ion version (version[2:0]) this device complies with revision 1.1 of the pci bus power management interface specification. ro 010b 15:8 next item offset (next_offset[7:0]) there is only a single item in the capa bilities list. no other list elements follow. this field will always return 0h. ro 0h 7:0 capability id (cap_id) this is the capability identifier fo r pci power management interface. it identifies the link list item as bei ng the pci power management registers. ro 01h bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 154 smsc lan9420/lan9420i datasheet 4.6.2 pci power management control and status register (pci_pmcsr) this register controls the device?s power state. note: the format of this register is equivalent to of fsets 7:4 of the power management register block definition as described in revision 1.1 of the pci bus power management interface specification. offset: 7ch size: 32 bits bits description type default 31:24 data (pm_data) this field is not implemented and returns zeros. ro 00h 23:16 pmcsr pci to pci bridge su pport extensions (pmcsr_bse) this field is not implemented and returns zeros. ro 00h 15 pme status (pme_status) this bit is set when an enabled power management event has been detected. writing a ?1? to this bit will cl ear it provided that the source of the event has been cleared. this bit is level-triggered and will not clear on write if the source of the pow er management event remains asserted. writing a ?0? has no effect. when the vauxdet input pin is low, this bit is reset on assertion of a power- on reset or pci reset (pcinrst). when the vauxdet input pin is high, this bit is unaffected by assertion of pci reset (pcinrst). in this case, the bit will maintain its setting until cleared with a write, or until assertion of a power-on reset. r/wc note 4.11 14:13 data scale (data_scale) this field is not implemented and return s zeros as a result of the pm_data field of this register not being implemented. ro 00b 12:9 data select (data_select) this field is not implemented and return s zeros as a result of the pm_data field of this register not being implemented. ro 0000b 8 pme enable (pme_en) when this bit is set, the device will assert the external npme signal if the pme status (pme_status) bit in this register is set. when this bit is cleared, the device will not assert the external npme signal. when the vauxdet input pin is cleared, th is bit is reset on assertion of a power-on reset or pci reset (pcinrst). when the vauxdet input pin is set, this bit is unaffected by assertion of pci reset (pcinrst). in this case, the bit will maintain its setting until cleared with a write, or until assertion of a power-on reset. if pme_en is cleared, the device will automatically place the phy into general power-down when entering the d3 hot state. r/w note 4.11 7:2 reserved ro -
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 155 revision 1.6 (07-18-11) datasheet note 4.11 the default state of this field is dependant on the setting of the vauxdet signal as noted in the description. 1:0 power management state (pm_state) this field sets the current pm state. 00b = d0 01b = reserved 10b = reserved 11b = d3 operations that at tempt to write a reserved setting to this field will complete normally on the pci bus; however d[1:0] are ignored and no state change occurs. r/w 00b bits description type default
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 156 smsc lan9420/lan9420i datasheet chapter 5 operational characteristics 5.1 absolute maximum ratings* supply voltage (vdd33a, vdd33bias, vdd33io) ( note 5.1 ) . . . . . . . . . . . . . . . . . . . . . . 0v to +3.6v positive voltage on signal pins, with respect to ground ( note 5.2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . +6v negative voltage on signal pins, with respect to ground ( note 5.3 ) . . . . . . . . . . . . . . . . . . . . . . . . -0.5v positive voltage on xi, with re spect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 4.6v positive voltage on xo, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2. 5v ambient operating temperature in still air (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 5.4 storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..+/- 5kv note 5.1 when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggeste d that a clamp circuit be used. note 5.2 this rating does not apply to the following pins: xi, xo, exres. note 5.3 this rating does not apply to the following pins: exres. note 5.4 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. *stresses exceeding those listed in this section c ould cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 5.2, "operating conditions**" , section 5.4, "dc specifications" , or any other applicable section of this specification is not implied. note, device signals are not 5 volt tolerant. 5.2 operating conditions** supply voltage (vdd33a, vdd33bias, vdd33io) . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3v +/- 300mv ambient operating temperature in still air (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 5.4 **proper operation of lan9420/lan9420i is guaranteed on ly within the ranges specified in this section.
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 157 revision 1.6 (07-18-11) datasheet 5.3 power consumption this section details the power consumption of lan9420/ lan9420i as measured during various modes of operation. power consumption val ues are provided for both the device-only, and for the device plus ethernet components. note: power dissipation is determined by operating fr equency, temperature, and supply voltage, as well as external source/sink requirements. 5.3.1 d0 - normal operation with ethernet traffic table 5.1 d0 - normal operation - supply and current (typical) parameter typical (@ 3.3v) unit 100base-tx full duplex supply current (vdd33io, vdd33bias, vdd33a) 125 ma power dissipation (device only) 415 mw power dissipation (device and ethernet components) 560 mw ambient operating temperature in still air (t a )25 o c 10base-t full duplex supply current (vdd33io, vdd33bias, vdd33a) 80 ma power dissipation (device only) 265 mw power dissipation (device and ethernet components) 615 mw ambient operating temperature in still air (t a )25 o c
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 158 smsc lan9420/lan9420i datasheet 5.3.2 d3 - enabled for w ake up packet detection 5.3.3 d3 - enabled for link status change detection (energy detect) table 5.2 d3 - enabled for wake up packet detection - supply and current (typical) parameter typical (@ 3.3v) unit 100base-tx full duplex supply current (vdd33io, vdd33bias, vdd33a) 76 ma power dissipation (device only) 252 mw power dissipation (device and ethernet components) 400 mw ambient operating temperature in still air (t a )25 o c 10base-t full duplex supply current (vdd33io, vdd33bias, vdd33a) 40 ma power dissipation (device only) 131 mw power dissipation (device and ethernet components) 502 mw ambient operating temperature in still air (t a )25 o c table 5.3 d3 - enabled for link status change detection - supply and current (typical) parameter typical (@ 3.3v) unit 100base-tx full duplex supply current (vdd33io, vdd33bias, vdd33a) 21 ma power dissipation (device only) 70 mw power dissipation (device and ethernet components) 70 mw ambient operating temperature in still air (t a )25 o c 10base-t full duplex supply current (vdd33io, vdd33bias, vdd33a) 21 ma power dissipation (device only) 70 mw power dissipation (device and ethernet components) 70 mw ambient operating temperature in still air (t a )25 o c
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 159 revision 1.6 (07-18-11) datasheet 5.3.4 d3 - phy in general power down mode 5.3.5 maximum power consumption note 5.5 over the conditions specified in section 5.2, "operating conditions**" . note: power dissipation is determined by temperature, s upply voltage, as well as external source/sink current requirements. table 5.4 d3 - phy in general power down mode - supply and current (typical) parameter typical (@ 3.3v) unit 100base-tx full duplex supply current (vdd33io, vdd33bias, vdd33a) 6 ma power dissipation (device only) 19 mw power dissipation (device and ethernet components) 19 mw ambient operating temperature in still air (t a )25 o c 10base-t full duplex supply current (vdd33io, vdd33bias, vdd33a) 6 ma power dissipation (device only) 19 mw power dissipation (device and ethernet components) 19 mw ambient operating temperature in still air (t a )25 o c table 5.5 maximum power consumption - supply and current (maximum) parameter maximum (@ 3.6v) unit 100base-tx full duplex supply current (vdd33io, vdd33bias, vdd33a) 145 ma power dissipation (device only) 530 mw power dissipation (device and ethernet components) 690 mw ambient operating temperature in still air (t a ) note 5.5 o c 10base-t full duplex supply current (vdd33io, vdd33bias, vdd33a) 85 ma power dissipation (device only) 310 mw power dissipation (device and ethernet components) 700 mw ambient operating temperature in still air (t a ) note 5.5 o c
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 160 smsc lan9420/lan9420i datasheet 5.4 dc specifications note 5.6 this specification applies to all is type inputs and tri-stated bi-direc tional non-pci pins. internal pull- down and pull-up resistors add +/- 50 a per-pin (typical) note 5.7 this buffer type adheres to section 4.2.2 (3.3v signaling environment) of the pci local bus specification revision 3.0 . device signals are not 5v tolerant. this device must not be used in a 5v pci system, or connected to 5v logic without appropriate voltage level translation. note 5.8 this specification applies to all ipci type inputs and tri-stated bi-d irectional pci pins. note 5.9 xi can optionally be driven from a 25mhz single-ended clock oscillator. table 5.6 i/o buffer characteristics parameter symbol min typ max units notes is type input buffer low input level high input level negative-going threshold positive-going threshold schmitttrigger hysteresis (v iht - v ilt ) input leakage input capacitance v ili v ihi v ilt v iht v hys i in c in -0.3 1.01 1.39 345 -10 1.18 1.6 420 3.6 1.35 1.8 485 10 3 v v v v mv ua pf schmitt trigger schmitt trigger note 5.6 ipci type input buffer low input level high input level input leakage input capacitance v ili v ihi i in c in -0.5 1.5 -10 1.08 4.1 10 3 v v ua pf note 5.7 note 5.8 opci type buffer low output level (i out =500ua) high output level (i out =-500ua) v ol v oh 2.7 0.3 v v note 5.7 o8 type buffers low output level high output level v ol v oh vdd33io - 0.4 0.4 v v i ol = 8ma i oh = -8ma o12 type buffers low output level high output level v ol v oh vdd33io - 0.4 0.4 v v i ol = 12ma i oh = -12ma od12 type buffer low output level v ol 0.4 v i ol = 12ma iclk type buffer (xi input) low input level high input level v ili v ihi -0.3 1.4 0.5 3.6 v v note 5.9
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 161 revision 1.6 (07-18-11) datasheet note 5.10 measured at line side of transformer, line replaced by 100 (+/- 1%) resistor. note 5.11 offset from 16ns pulse width at 50% of pulse peak. note 5.12 measured differentially. note 5.13 min/max voltages guaranteed as measured with 100 resistive load. table 5.7 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 5.10 peak differential output voltage low v ppl -950 - -1050 mvpk note 5.10 signal amplitude symmetry v ss 98 - 102 % note 5.10 signal rise and fall time t rf 3.0 - 5.0 ns note 5.10 rise and fall symmetry t rfs --0.5ns note 5.10 duty cycle distortion d cd 35 50 65 % note 5.11 overshoot and undershoot v os --5% jitter 1.4 ns note 5.12 table 5.8 10base-t transceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 5.13 receiver differential squelch threshold v ds 300 420 585 mv
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 162 smsc lan9420/lan9420i datasheet 5.5 ac specifications this section contains timing information for non-pci signals. note: lan9420/lan9420i adheres to the pci local bus specification revision 3.0. refer to the conventional pci 3.0 specification for pci timing details and parameters. 5.5.1 equivalent test load (non-pci signals) output timing specifications assume the 25pf equivalent test load illustrated in figure 5.1 below. note: this test load is not applicable to pci signals. these signals adhere to the pci local bus specification revision 3.0. refer to the conventional pci 3.0 specification for additional information. figure 5.1 output equivalent test load 25 pf output
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 163 revision 1.6 (07-18-11) datasheet 5.6 pci clock timing the following specifies the pci clock requirements for lan9420/lan9420i: note 5.14 this slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in figure 5.2 . figure 5.2 pci clock timing table 5.9 pci clock timing values symbol description min typ max units t cyc pciclk cycle time 30 ns t high pciclk high time 11 ns t low pciclk low time 11 ns - pciclk slew rate ( note 5.14 )1 4v/ns t high t cyc t low pciclk 0.6*vdd33io 0.2*vdd33io 0.5*vdd33io 0.4*vdd33io 0.3*vdd33io 0.4*vdd33io p-to-p (minimum)
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 164 smsc lan9420/lan9420i datasheet 5.7 pci i/o timing the following specifies the pci i/o requirements for lan9420/lan9420i: note: input test is done with 0. 1*vdd33io overdrive. v max specifies the maximum peak-to-peak waveform allowed for testing input timing. figure 5.3 pci i/o timing table 5.10 pci i/o timing measurement conditions symbol value units v th 0.6*vdd33io v v tl 0.2*vdd33io v v test 0.4*vdd33io v v trise 0.285*vdd33io v v tfall 0.615*vdd33io v v max 0.4*vdd33io v input signal edge rate 1v/ns pciclk tri-state pci outputs pci outputs t val t on t off t su t h pci inputs v test v trise, v tfall v test v th v tl v th v tl v max
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 165 revision 1.6 (07-18-11) datasheet note: pci signal timing is specified with loads de tailed in section 4.2.3.2 of the pci local bus specification, rev. 3.0. note 5.15 nreq and ngnt are point-to-point signals and have different timing characteristics than bussed signals. all other signals are bussed. note 5.16 pcinrst is asserted and deasserted asynchronously with respect to the pciclk signal. table 5.11 pci i/o timing values symbol description min typ max units t val pciclk to signal valid delay - bussed signals 2 11 ns t val(nreq) pciclk to nreq signal valid delay ( note 5.15 ) 2 12 ns t on float to active delay 2 ns t off active to float delay 28 ns t su input setup time to pciclk - bussed signals 7 ns t su(ngnt) ngnt input setup time to pciclk ( note 5.15 )10 ns t h input hold time from pciclk 0 ns t rst pcinrst active time after power stable ( note 5.16 ) 1ms t rst-clk pcinrst active time after pciclk stable ( note 5.16 ) 100 us t rst-off rest active to output float delay ( note 5.16 )40ns
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 166 smsc lan9420/lan9420i datasheet 5.8 eeprom timing the following specifies the eeprom timing requirements for lan9420/lan9420i: figure 5.4 eeprom timing table 5.12 eeprom timing values symbol description min typ max units t ckcyc eeclk cycle time 1110 1130 ns t ckh eeclk high time 550 570 ns t ckl eeclk low time 550 570 ns t cshckh eecs high before rising edge of eeclk 1070 ns t cklcsl eeclk falling edge to eecs low 30 ns t dvckh eedio valid before rising edge of eeclk (output) 550 ns t ckhdis eedio disable after rising edge eeclk (output) 550 ns t dsckh eedio setup to rising edge of eeclk (input) 90 ns t dhckh eedio hold after rising edge of eeclk (input) 0ns t ckldis eeclk low to data disable (output) 580 ns t cshdv eedio valid after eecs high (verify) 600 ns t dhcsl eedio hold after eecs low (verify) 0 ns t csl eecs low 1070 ns eeclk eedo eedi eecs t ckldis t cshckh eedi (verify) t ckh t ckl t ckcyc t cklcsl t csl t dvckh t ckhdis t dsckh t dhckh t dhcsl t cshdv
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 167 revision 1.6 (07-18-11) datasheet 5.9 clock circuit lan9420/lan9420i can accept either a 25mhz cryst al (preferred) or a 25mhz single-ended clock oscillator (+/- 50ppm) input. if the single-ended clock oscillator met hod is implemented, xo should be left unconnected and xi should be driven with a nomin al 0-3.3v clock signal. the input clock duty cycle is 40% minimum, 50% typical and 60% maximum. it is recommended that a crystal utilizing matchi ng parallel load capacitors be used for the crystal input/output signals (xi/xo). see table 5.13 for the recommended crystal specifications. note 5.17 the maximum allowable values for frequency tolerance and frequency stability are application dependant. since any particular application must meet the ieee +/-50 ppm total ppm budget, the combination of these tw o values must be approximately +/-45 ppm (allowing for aging). note 5.18 frequency deviation over time is also referred to as aging. note 5.19 the total deviation for the transmitter clock frequency is specified by ieee 802.3u as +/- 50 ppm. note 5.20 0 o c for commercial version, -40 o c for industrial version. note 5.21 +70 o c for commercial version, +85 o c for industrial version. note 5.22 this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xo/xi pin and pcb capacitance values are required to accurately calculate the value of the two exte rnal load capacitors. these two external load capacitors determine the accuracy of the 25.000 mhz frequency. table 5.13 lan9420/lan9420i crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - +/-50 ppm note 5.17 frequency stability over temp f temp - - +/-50 ppm note 5.17 frequency deviation over time f age - +/-3 to 5 - ppm note 5.18 total allowable ppm budget - - +/-50 ppm note 5.19 shunt capacitance c o -7 typ-pf load capacitance c l - 20 typ - pf drive level p w 0.5 - - mw equivalent series resistance r 1 --50ohm operating temperature range note 5.20 - note 5.21 o c lan9420/lan9420i xi pin capacitance -3 typ-pf note 5.22 lan9420/lan9420i xo pin capacitance -3 typ-pf note 5.22
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 168 smsc lan9420/lan9420i datasheet chapter 6 package outline 6.1 128-vtqfp package figure 6.1 lan9420/lan9420i 128-vtqfp package definition
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 169 revision 1.6 (07-18-11) datasheet notes: 1. all dimensions are in mill imeters unless otherwise noted. 2. dimensions b & c apply to the flat section of the lead foot between 0. 10 and 0.25mm from the lead tip. the base metal is exposed at the lead tip. 3. dimensions d1 and e1 do not include mold protrusi ons. maximum allowed protru sion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 4. the pin 1 identifier may vary, but is always located within the zone indicated. table 6.1 lan9420/lan9420i 128-vtqfp dimensions min nominal max remarks a - - 1.20 overall package height a1 0.05 - 0.15 standoff a2 0.95 1.00 1.05 body thickness d/e 15.80 16.00 16.20 x/y span d1/e1 13.80 14.00 14.20 x/y plastic body size l 0.45 0.60 0.75 lead foot length b 0.13 0.18 0.23 lead width c 0.09 - 0.20 lead foot thickness e 0.40 bsc lead pitch ddd 0.00 - 0.07 true position spread ccc - - 0.08 coplanarity figure 6.2 lan9420/lan9420i 128-vtq fp recommended pcb land pattern
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet revision 1.6 (07-18-11) 170 smsc lan9420/lan9420i datasheet chapter 7 datasheet revision history table 7.1 customer revision history revision level & date secti on/figure/entr y correction rev. 1.6 (07-18-11) section 3.5.6.1, "tx checksum calculation" added note stating tx checksum calculation should not be used for udp packets under ipv6. rev. 1.5 (04-12-11) section 3.7.7, "enabling link status change (energy detect) wake events," on page 82 step #2 corrected from ?this is done by setting the int7 bit in the phy?s interrupt source flag register.? to ?this is done by setting bit 7 in the phy?s interrupt mask register.? section 4.3.1, "bus mode register (bus_mode)," on page 105 added note to pbl field description: ?pci bursts are always 16 cycles, regardless of the value in this field.? rev. 1.4 (12-17-08) all fixed various typos. section 3.7.7, "enabling link status change (energy detect) wake events," on page 82 corrected second sentence of step 3: ?this is done by setting the edpwrdown bit in the phy?s mode control/status register.? section 4.3.1, "bus mode register (bus_mode)," on page 105 added dbo and ble bit definitions. table 5.13, ?lan9420/lan9420i crystal specifications,? on page 167 updated max esr value to 50 ohms. rev. 1.22 (09-23-08) added pci sig certification logo to cover rev. 1.21 (07-30-08) figure 1.2 lan9420/lan9420i internal block diagram on page 11 fixed error: changed ?to option..? text to ?(optional)? and moved it to the end of the descriptions. figure 1.2 lan9420/lan9420i internal block diagram on page 11 - changed ?to option..? text to ?(optional)? and moved it to the end of the descriptions. - removed ?to? from ?to ethernet?. - placed bi-directional arrows on eeprom, gpio/led, and phy blocks. section 4.5.5, "auto negotiation advertisement," on page 141 changed bits 9 and 15 to reserved with a default value of 0b. table 4.10, ?standard pci header registers supported,? on page 151 added note to default value of revision id stating that the default value is dependent on device revision. table 4.10, ?standard pci header registers supported,? on page 151 changed default values of min_gnt and max_lat to 02h and 04h, respectively. section 3.5.5.1, "rx checksum calculation," on page 63 changed last line of rx checksum calculation to ?checksum = [b1, b0] + c0 + [b3, b2] + c1 + ? + [0, bn] + cn-1?
single-chip ethernet controller with hp auto-mdix support and pci interface datasheet smsc lan9420/lan9420i 171 revision 1.6 (07-18-11) datasheet section 3.5.4, "wakeup frame detection," on page 57 , section 4.4.1, "mac control register (mac_cr)," on page 120 added note: ?when wake-up frame detection is enabled via the wuen bit of the wakeup control and status register (wucsr) , a broadcast wake- up frame will wake-up the device despite the state of the disable broadcast (bcast) bit in the mac control register (mac_cr) . ? section 4.4.12, "wakeup control and status register (wucsr)," on page 134 corrected gue bit description to state: ?....a global unicast frame has the mac address [0] bit set to 0.? section 5.9, "clock circuit," on page 167 updated drive level from 0.5mw to 300uw. section 4.5.5, "auto negotiation advertisement," on page 141 fixed pause operation bit definitions to: 00 no pause 01 symmetric pause 10 asymmetric pause 11 advertise support for both symmetric pause and asymmetric pause added note stating: when both symmetric pause and asymmetric pause support are advertised (value of 11), the device will only be configured to, at most, one of the two settings upon auto- negotiation completion. table 7.1 customer revision history (continued) revision level & date secti on/figure/entr y correction

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