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silego technology, inc. rev 1.08 SLG46537_ds_108 revised october 12, 2017 greenpak programmable mixed-signal matrix with asynchronous state machine SLG46537 block diagram features ? logic & mixed signal circuits ? highly versatile macrocells ? read back protection (read lock) ? 1.8 v (5%) to 5 v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? 20-pin stqfn: 2 x 3 x 0 .55 mm, 0.4 mm pitch or 22-pin mstqfn 2x 2.2 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics available package options stqfn-20 (top view) mstqfn-22 (top view) packages drawn to scale 2 mm 2.2 mm 2 mm 3 mm 3-bit lut3_2 or dff5 programmable delay rc oscillator acmp0 acmp1 acmp2 acmp 3 additional logic functions combination function macrocells 2-bit lut2_0 or dff0 2-bit lut2_2 or dff2 2-bit lut2_1 or dff1 2-bit lut2_3 or pgen 3-bit lut3_1 or dff4 3bit lut3_0 or dff3 3-bit lut3_4 or dff7 3-bit lut3_3 or dff6 filter_1 with edge detect por i 2 c serial communication asm 8 states 3-bit lut3_5 or cnt/dly2 3-bit lut3_6 or cnt/dly3 3-bit lut3_7 or cnt/dly4 3-bit lut3_8 or cnt/dly5 3-bit lut3_9 or cnt/dly6 4-bit lut4_0 or cnt/dly0 4-bit lut4_1 or cnt/dly1 3-bit lut3_10 or pipe delay 8 byte ram + otp memory vref crystal oscillator 25m oscillator io4 io5 vdd io0 io1 io2 io3 io9 gnd io14 io13 io12 io11 io10 io6 io7 io8 io17 io16 io15 filter_0 with edge detect
SLG46537_ds_108 page 1 of 192 SLG46537 1.0 overview the SLG46537 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macrocells of the SLG46537. this highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single in tegrated circuit. the macrocells in the device include the following: ? four analog comparators (acmp) ? two voltage references (vref) ? nineteen combination function macrocells ? three selectable dff/latch or 2-bit luts ? one selectable continuous dff/latch or 3-bit lut ? four selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pattern generator or 2-bit lut ? five 8-bit delays/co unters or 3-bit luts ? two 16-bit delays/co unters or 4-bit luts ? two deglitch filters with edge detectors ? asynchronous state machine ? eight states ? flexible input logic from state transitions ? serial communications ?i 2 c protocol compliant ? pipe delay C 16 sta ge/3 output (part of c ombination function m acrocell) ? programmable delay ? two oscillators (osc) ? configurable 25 khz/2 mhz ? 25 mhz rc oscillator ? crystal oscillator ? power-on-reset (por) ? eight byte ram + otp user memory ? ram memory space that is readable and wr itable via i 2 c ? user defined initial valu es transferred from otp ? analog temperature sensor SLG46537_ds_108 page 2 of 192 SLG46537 2.0 pin description 2.1 functional pin description stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options 1 16 vdd vdd power supply -- -- 2 1 io0 io0 general purpose input digital input without schmitt trigger -- digital input with schmitt trigger -- low voltage digital input -- 3 2 io1 io1 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- 4 3 io2 io2 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) 5 4 io3 io3 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- 6 5 io4 io4 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) acmp0+ analog comparator 0 positive input analog -- 7 6 io5 io5 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp0- analog comparator 0 negative input analog -- SLG46537_ds_108 page 3 of 192 SLG46537 8 19 io6 io6 general purpose i/o with oe* digital input without schmitt trigger open drain nmos (1x) (2x) digital input with schmitt trigger -- low voltage digital input -- scl i 2 c serial clock digital input without schmitt trigger open drain nmos digital input with schmitt trigger open drain nmos low voltage digital input open drain nmos 9 7 io7 io7 general purpose i/o digital input without schmitt trigger open drain nmos (1x) (2x) digital input with schmitt trigger -- low voltage digital input -- sda i 2 c serial data digital input without schmitt trigger open drain nmos digital input with schmitt trigger open drain nmos low voltage digital input open drain nmos 10 8 io8 io8 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) (4x) low voltage digital input open drain pmos (1x) (2x) acmp1+ analog comparator 1 positive input analog -- 11 20 gnd gnd ground -- -- 12 21 io9 io9 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) (4x) low voltage digital input -- ext_vref analog comparator negative input analog -- 13 11 io10 io10 general purpose i/o with oe* digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp2+ analog comparator 2 positive input analog -- acmp3+ analog comparator 3 positive input analog -- stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options SLG46537_ds_108 page 4 of 192 SLG46537 14 12 io11 io11 general purpose i/o with oe* digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp2- analog comparator 2 negative input analog -- acmp3- analog comparator 3 negative input analog -- 15 22 io12 io12 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) acmp3+ analog comparator 3 positive input analog -- 16 13 io13 io13 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp3+ analog comparator 3 positive input analog -- xtal0 external crystal connection 0 -- analog 17 14 io14 io14 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) xtal1 external crystal connection 1 analog -- ext_clk0 external clock connection 0 digital input without schmitt trigger -- digital input with schmitt trigger -- low voltage digital input -- stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options SLG46537_ds_108 page 5 of 192 SLG46537 18 18 io15 io15 general purpose i/o with oe* digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- vref0 voltage reference 0 output -- analog ext_clk1 external clock connection 1 digital input without schmitt trigger -- digital input with schmitt trigger -- low voltage digital input -- 19 15 io16 io16 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- vref0 voltage reference 0 out- put -- analog 20 17 io17 io17 general purpose i/o digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) ext_clk2 external clock connec- tion 2 digital input without schmitt trig- ger -- digital input with schmitt trigger -- low voltage digital input -- -- 9 nc nc no connection -- -- -- 10 nc nc no connection -- -- note: * general purpose i/o's with oe can be used to implement bidirectional signals under user control via connection matrix to oe signal in i/o structure stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options SLG46537_ds_108 page 6 of 192 SLG46537 2.2 pin configuration - stqfn20l 2.3 pin configuration - mstqfn-22l io11 io12 io13 io14 io2 io1 2 3 414 15 16 17 io0 vdd 1 stqfn-20 (top view) io4 io3 5 6 io9 io10 12 13 io5 7 gnd 11 io7 io6 8 9 io8 10 io16 io15 18 19 io17 20 pin # signal name pin functions 1vdd 2 io0 gpi 3 io1 gpio with oe 4 io2 gpio 5 io3 gpio with oe 6 io4 gpio / acmp0+ 7 io5 gpio with oe / acmp0- 8 io6 gpio / scl 9 io7 gpio / sda 10 io8 gpio with oe/ acmp1+ 11 gnd gnd 12 io9 gpio / acmp0- / acmp1- / acmp2- / acmp3- 13 io10 gpio with oe / acmp2+ / acmp3+ 14 io11 gpio with oe / acmp2- / acmp3- 15 io12 gpio with oe / acmp3+ 16 io13 gpio with oe / acmp3+ / xtal0 17 io14 gpio with oe / xtal1 / ext_clk0 18 io15 gpio with oe / vref0 / ext_clk1 19 io16 gpio with oe / vref0 20 io17 gpio with oe / ext_clk2 nc io10 io11 io13 io3 io2 2 3 410 11 12 13 io1 io0 1 mstqfn-22l (top view) io4 5 nc 9 io7 io5 6 7 io8 8 io16 io14 14 15 vdd 16 20 21 22 19 18 17 gnd io6 io15 io17 20 19 18 17 io12 io9 22 21 pin # signal name pin functions 1 io0 gpi 2 io1 gpio with oe 3 io2 gpio 4 io3 gpio with oe 5 io4 gpio / acmp0+ 6 io5 gpio with oe 7 io7 gpio / sda 8 io8 gpio with oe/ acmp1+ 9nc 10 nc 11 io10 gpio with oe / acmp2+ / acmp3+ 12 io11 gpio with oe / acmp2- / acmp3- 13 io13 gpio with oe / acmp3+ / xtal0 14 io14 gpio with oe / xtal1 / ext_clk0 15 io16 gpio with oe / vref0 16 vdd 17 io17 gpio with oe / ext_clk2 18 io15 gpio with oe / vref0 / ext_clk1 19 io6 gpio / scl 20 gnd gnd 21 io9 gpio / acmp0- / acmp1- / acmp2- / acmp3- 22 io12 gpio with oe / acmp3+ oe : output enable acmpx+ : acmpx positive input acmpx- : acmpx negative input scl/od : i 2 c clock input/ nmos open drain output only sda/od : i 2 c data input/ nmos open drain output only vrefx : voltage reference output ext_clkx : external clock input legend: SLG46537_ds_108 page 7 of 192 SLG46537 3.0 user programmability the SLG46537 is a user programmable device with one-time-progra mmable (otp) memory elements that are able to construct combinatorial logic elements. three of the i/o pins provide a c onnection for the bit patterns into the otp on board memory. a programming development kit allows the user the ability to crea te initial devices. once the design is finalized, the programmi ng code (.gpx file) is forwarded to silego to integrate into a pro duction process. figure 1. steps to create a cu stom silego greenpak device 3 u r g x f w ' h i l q l w l r q & |