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[ ak 4458 ] 014011794 - e - 00 2015/01 - 1 - 1. g eneral description the ak44 58 is a 32 - bit 8 ch premium dac, which achieves industrys best low distortion characteristics by a newly developed low distortion technology. it corresponds to a 768khz pcm input and an 11.2mhz dsd input at maximum, su itable for play backing high resolution audio sources that are becoming widespread in network audios, usb - dacs and car audio systems. in addition, osr - doubler technology is newly adopted, making the ak44 58 capable of supporting wide range signals and ach ieving low out - of - band noise while realizing low power consumption. moreover, the ak44 58 has five types of 32 - bit digital filters, realizing simple and flexible sound making in wide range of applications. application : av receivers, cd/sacd players, networ k audio s , usb dacs, usb headphones, sound plate/bars, car audios, automotive external amplifiers, measuring instruments and control systems. 2. features (1) dr, s/n: 1 15 db (2) thd+n: - 10 7 db (3) 256 x over sampling (osr - doubler) (4) sampling rate : 8 khz ? (5) 3 2bit 8x dig ital filter - ripple: ? (6) high tolerance to clock jitter (7) low distortion differential output (8) dsd data input (9) daisy chain (10) digital de - emphasis for 32, 44 .1 , 4 8khz sampling (11) soft mute (12) digital attenuator ( 25 5 levels and 0.5db step ) (13) i/f forma t: - 24/32bit msb justified - 16/20/24/32bit - lsb justified - i 2 s - dsd - tdm (14) 3 - wire serial and i 2 c p i/f (15) master clock: - 30khz ~ 32khz : 1152fs - 30khz ~ 54khz : 512 fs or 768fs - 30khz ~ 108khz: 256fs or 384fs - 108khz ~ 216khz: 128 fs or 192 fs ~ 384khz: 64fs or 128fs ~ 768khz: 64fs ak4458 115db 768khz 32 - bit 8ch premium dac
[ ak 4458 ] 014011794 - e - 00 2015/01 - 2 - (16) digital input level: cmos (17) power supply: - tvdd = 1. 7 ? - a vdd = 3.0 ? (18) supporting 105 c temperature ( exposed pad is connected to ground ) (19) package: 4 8 - pin qfn
[ ak 4458 ] 014011794 - e - 00 2015/01 - 3 - 3. table of contents 1. general description ................................ ................................ ................................ ............................... - 1 - 2. features ................................ ................................ ................................ ................................ .................. - 1 - 3. table of contents ................................ ................................ ................................ ................................ ... - 3 - 4. block diagram and functions ................................ ................................ ................................ ............... - 5 - functions ................................ ................................ ................................ ................................ .............. - 6 - 5. pin configurations and functions ................................ ................................ ................................ .......... - 7 - ordering guide ................................ ................................ ................................ ................................ ..... - 7 - pin configurations ................................ ................................ ................................ ................................ - 7 - pin functions ................................ ................................ ................................ ................................ ........ - 8 - handling of unused pin ................................ ................................ ................................ ....................... - 9 - 6. absolute maximum ratings ................................ ................................ ................................ ................ - 10 - 7. recommended operation conditions ................................ ................................ ................................ .. - 10 - 8. electrical characteristics ................................ ................................ ................................ ..................... - 11 - analog characteristics ................................ ................................ ................................ ........................ - 11 - sharp roll - off filter characteristics ................................ ................................ ................................ .. - 13 - slow roll - off filter characteristics ................................ ................................ ................................ ... - 14 - sho rt delay sharp roll - off filter characteristics ................................ ................................ .............. - 15 - short delay slow roll - off filter characteristics ................................ ................................ ............... - 16 - dsd mode characteristics ................................ ................................ ................................ ................. - 17 - dc characteristics ................................ ................................ ................................ .............................. - 17 - switching characteristics ................................ ................................ ................................ ................... - 18 - timing diagram ................................ ................................ ................................ ................................ . - 22 - 9. functional descriptions ................................ ................................ ................................ ....................... - 26 - d/a conversion mode (pcm mode, ds d mode) ................................ ................................ .............. - 26 - system clock ................................ ................................ ................................ ................................ ...... - 26 - audio interface format ................................ ................................ ................................ ...................... - 30 - d/a conversion mo de (pcm mode, dsd mode) swit ching timing ................................ ............... - 43 - digital filter (pcm mode) ................................ ................................ ................................ ................. - 44 - de-emphasis filter (pcm mode) ................................ ................................ ................................ ........ - 44 - output volume (pcm mode, dsd mode) ................................ ................................ ......................... - 45 - out of band noise reduction filter (pcm mode, dsd mode) ................................ ......................... - 46 - zero detection ( pcm mode, dsd mode ) ................................ ................................ .......................... - 52 - lr channel ou tput signal select ( pcm mode, dsd mode ) ................................ ............................. - 52 - sound quality adjustment ( pcm mode, dsd mode ) ................................ ................................ ....... - 54 - dsd full scale (fs) signal detection function ................................ ................................ ................ - 55 - soft mute operation (pcm mode, dsd mode) ................................ ................................ ................. - 56 - error detection ................................ ................................ ................................ ................................ ... - 57 - system reset ................................ ................................ ................................ ................................ ...... - 57 - power down function ................................ ................................ ................................ ........................ - 58 - power off and reset functions ................................ ................................ ................................ .......... - 59 - synchronization function (pcm mode) ................................ ................................ ............................ - 62 - parallel mode ................................ ................................ ................................ ................................ ...... - 63 - serial control interface ................................ ................................ ................................ ...................... - 63 - function list ................................ ................................ ................................ ................................ ....... - 68 - register map ................................ ................................ ................................ ................................ ...... - 69 - register definitions ................................ ................................ ................................ ............................ - 70 - 10. recommended external circuits ................................ ................................ ................................ ...... - 78 - typical connection diagram ................................ ................................ ................................ .............. - 78 -
[ ak 4458 ] 014011794 - e - 00 2015/01 - 4 - 11. package ................................ ................................ ................................ ................................ ............ - 81 - outline dimensions ................................ ................................ ................................ ............................ - 81 - material & lead finish ................................ ................................ ................................ ....................... - 81 - marking ................................ ................................ ................................ ................................ .............. - 82 - 12. revision history ................................ ................................ ................................ .............................. - 82 - important notice ................................ ................................ ................................ ............................ - 83 -
[ ak 4458 ] 014011794 - e - 00 2015/01 - 5 - 4. block di agram and functions figure 1 . block diagram mclk s dti1/dsd r 1 lrck/dsd l1 cad 0 _i2c / c sn /dif bi ck /dclk scl /cclk /tdm1 sda /cdti /tdm0 pdn avdd clock divider dvss t vdd ps/ cad 0 _sp i aoutr1 n vrefh1 vrefl1 avss aoutl1 p aoutr1 p pcm data interface de - empha sis dsd data interface 8x i nterpolator control register scf scf aoutr2 n vrefh2 vrefl2 aoutl2 p aoutl2 n aoutr2 p vref s dti2/dsdl2 8x interpolator scf scf vref bias i2c aoutr 3 n vrefh 3 vrefl 3 aoutl 3 p aoutl 3 n aoutr 3 p 8x interpolator scf scf aoutr 4 n vrefh 4 vrefl 4 aoutl 4 p aoutl 4 n aoutr 4 p vref 8x interpolator scf scf vref s d ti 3 /dsd r2 /tdmo1 s dti 4 /dsdl 3 /tdmo2 dsd r3 dsd l4 dsd r4 vdd 18 ldo dzf /smute ca d1/ dchain ldoe datt soft mute dsd filter datt soft mute datt soft mute dsd filter datt soft mute d att soft mute dsd filter datt soft mute datt soft mute dsd filter datt soft mute ? ? ? modulator noise rejection filter ? ? ? modulator noise rejection filter ? ? ? modulator noise rejection filter ? ? ? modulator noise rejection filter aoutl1 n
[ ak 4458 ] 014011794 - e - 00 2015/01 - 6 - functions block functions pcm data interface this block executes serial/parallel conversion of sdti inp ut 32bit data by synchronizing with lrck and bick . dsd data interface 1 - bit data that is input from dsdl1 - 4 and dsdr1 - 4 pins is received by synchronizing with dclk . datt ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 7 - 5. pin configurations and functions ordering guide AK4458VN ? 40 ? +105 ? c (exposed pad is connected to ground) ? 40 ? +85 ? c (exposed pad is open ) 48 - pin qfn (0.5mm pitch) akd4458 evaluation board for ak4458 pin configurations note 1 . the exposed pad at back face of the package must be open or connected to the gro und of the board . 37 a out r 4p 38 3 9 4 0 aoutl4n 41 vrefh4 42 43 vrefl4 44 aoutr4n ldoe 36 35 34 33 32 31 30 29 1 2 mclk 3 lrck/dsdl1 4 sdti1/dsdr1 5 sdti2/dsdl2 6 sdti3/dsdr2/tdmo1 7 sdti4/dsdl3/tdmo2 8 dsdr3 20 19 18 17 16 15 14 13 scl/cclk /tdm1 cad0_i2c/ csn/ dif i2c ps/ cad 0_spi aoutl1n aoutl1p aoutr3n vrefl3 vrefh3 aoutl3n avss aoutr 2p sda/ c dti /tdm0 bick/dclk top view aoutr3p aoutl4p aoutl3p a vdd v refl 1 d vss 45 46 47 tvdd vdd 18 9 dsdl4 10 dsdr4 11 dzf / smute 48 pdn 2 4 23 22 21 vref h 1 aoutr1p aoutr1n aout l 2p 12 cad1/ dchain 28 27 26 25 vref l 2 aout l 2n aoutr2 n vref h 2 back pad : note 1
[ ak 4458 ] 014011794 - e - 00 2015/01 - 8 - pin functions no. pin name i/o function pd state 1 mclk i external master clock input pin hi - z 2 bick i audio serial data clock pin in pcm mode hi - z dclk i dsd clock pin in dsd mode 3 lrck i input channel clock pin in pcm mode hi - z dsdl1 i audio serial data input in dsd m ode 4 sdti1 i audio serial data input in pcm mode hi - z dsdr1 i audio serial data input in dsd m ode 5 sdti2 i au dio serial data input in pcm mode hi - z dsdl2 i audio serial data input in dsd m ode 6 sdti3 i audio serial data input in pcm mode 100k 2 c bus or 3 - wire s erial control mode 100k 2 c bus or 3 - wire s erial control mode hi - z dchain i daisy chain mode select pin in parallel control mode. 13 sda i/o control data pin in i 2 c bus s erial control mode hi - z cdti i control data input pin in 3 - wire s erial control mode tdm0 i tdm mode select pin in parallel control mode. 14 scl i control data clock pin in i 2 c bus s erial control mode hi - z cclk i control data clock pin in 3 - wire s erial control mode tdm1 i tdm mode select pin in parallel control mode. 15 cad 0_i2c i chip address 0 pin in i 2 c bus s erial control mode hi - z csn i chip select pin in 3 - wire serial control mode dif i audio data format select in parallel control mode. 2 s 16 ps i (i2c pin = : i 2 c bus serial control mode , : l: 3 h: i 2 c bus serial control mode or parallel control mode. hi - z 18 aoutl1p o l ch positive analog ou tput 1 pin hi - z 19 aoutl1n o l ch negative analog output 1 pin hi - z 20 vrefl1 i negative voltage reference input pin, avss hi - z 21 vrefh1 i positive voltage reference input pin, avdd hi - z
[ ak 4458 ] 014011794 - e - 00 2015/01 - 9 - no . pin name i/o function pd state 22 aoutr1n o r ch negative analog output 1 pin hi - z 23 aoutr1p o r ch positive analog output 1 pin hi - z 24 aoutl2p o l ch positive analog output 2 pin hi - z 25 aoutl2n o l ch negative analog output 2 pin hi - z 26 vrefl2 i negative voltage reference input pin, avss hi - z 27 vrefh2 i positive voltage reference input pin, avdd hi - z 28 aoutr2n o r ch negative analog output 2 pin hi - z 29 aoutr2p o r ch positive analog output 2 pin hi - z 30 avss - analog ground pin 31 avdd - analog power supply pin, 3.0v ? 5.5 v 32 aoutl3p o l ch positive analog output 3 pin hi - z 33 aoutl3n o l ch negative analog output 3 pin hi - z 34 vrefh3 i positive voltage reference input pin, avdd hi - z 35 vrefl3 i negative voltage reference i nput pin, avss hi - z 36 aoutr3n o r ch negative analog output 3 pin hi - z 37 aoutr3p o r ch positive analog output 3 pin hi - z 38 aoutl4p o l ch positive analog output 4 pin hi - z 39 aoutl4n o l ch negative analog output 4 pin hi - z 40 vrefh4 i positive voltage reference input pin, avdd hi - z 41 vrefl4 i negative voltage reference input pin, avss hi - z 42 aoutr4n o r ch negative analog output 4 pin hi - z 43 aoutr4p o r ch positive analog output 4 pin hi - z 44 ldoe i internal ldo enable pin. l: disable , h: ena ble hi - z 45 tvdd - digital power supply pin, 3.0 v ? 3.6v 46 d vss - digital ground pin 47 vdd18 o ldo output pin (ldoe pin = h) this pin should be connected to dvss with 1.0 f. ( note 4 ) i 1.8v power input pin (ldoe pin = l) 48 pdn i power - down & reset pin w hen this pin is l, t he ak4458 is powered - down and the control registers are reset to default state. hi - z note 2 . all input pins except internal pull - up/down pi ns should not b e left floating. note 3 . pcm mode and dsd mode are controlled by registers. daisy chain mode is controlled by both registers and pins. note 4 . this pin outputs dvss when the ldoe pin = h and hi - z when the ld oe pin = l . handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog aoutl1p/n, aoutr1p/n aoutl2p/n, aoutr2p/n aoutl3p/n, aoutr3p/n aoutl4p/n, aoutr4p/n these pins must be open. digital dzf th is pin must be open. sdti1 - 4, dsdr3, dsdl4, dsdr4 these pins must be connected to dvss
[ ak 4458 ] 014011794 - e - 00 2015/01 - 10 - 6. absolute maximum ratings ( avss =dvss =0 v ; note 5 ) parameter symbol m in . m ax . unit power supplies: analog d igital i/o digital core |avss ? ? ? ? ? ? ? ? ? ? ? ? ? 7. recommended operation conditions ( avss =dvss = 0v ; note 5 ) parameter symbol m in . t yp . m ax . unit power supplies analog (ldoe pin= l ) ( note 7 ) digital i/o digital core (ldoe pin = h )( note 8 ) digital i/ o avdd tvdd vdd18 tvdd 3.0 vdd18 1.7 3.0 5.0 1.8 1.8 3.3 5.5 3.6 1.98 3.6 v v v v voltage reference h voltage reference l voltage reference vrefh1 - 4 vrefl1 - 4 avdd ? 0.5 - - avss avdd - v v note 7 . tvdd must be powered up before vdd18 when the ldoe pin = l . the po wer up sequence between avdd and tvdd or avdd and vdd18 is not critical. note 8 . when ldoe pin = h , the internal ldo supplies 1.8v (typ) . the power up sequence s between avdd and tvdd , avdd and vdd18 are n ot critical. * akm assumes no responsibility for the usage beyond the conditions in thi s data sheet.
[ ak 4458 ] 014011794 - e - 00 2015/01 - 11 - 8. electrical characteristics analog characteristics (1) avdd = 5.0v (ta=25 ? c : tvdd=3.3v, avdd=5.0v: avss= dvss=0v: vrefh1/2/3/4=avdd, vrefl1/2/3/4= avss: fs=44.1khz : bick=64fs : signal frequency=1khz : 24 - bit input data : r l ? 2 k ? : measurement bandwidth = 20hz ~ 20khz : external circu it: ( figure 74 ) , unless otherwise specified.) parameter m in . t yp . m ax . unit resolution - - 32 bi t dynamic characteristics ( note 9 ) thd+n fs=44.1khz bw=20k hz 0dbfs ? ? ? ? ? dc accuracy interchannel gai n mismatch - 0 0.3 db gain drift ( note 12 ) - 20 - ppm/ ? ? ? ? ? power supplies power supply current normal operation (pdn pin = ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 12 - (2) a vdd = 3.3v (ta=25 c: tvdd=3.3v, avdd=3.3v: avss= dvss=0v: vrefh1/2/3/4=avdd, vrefl1/2/3/4= avss: fs=44.1khz : bick=64fs : signal frequency=1khz : 24 - bit input data : r l ? 2 k ? : measurement bandwidth = 20hz ~ 20khz : external circuit: ( figure 74 ) , unless otherwise specified.) parameter m in . t yp . m ax . unit resolution 32 b it dynamic characteristics ( note 9 ) thd+n fs=44.1khz bw=20khz 0dbfs ? ? ? ? ? dc accuracy inter c hannel gain mismatch 0 0.3 db gain drift ( note 12 ) - 20 - ppm/ c output voltage ( n ote 13 ) ? ? ? ? power supplies power supply current normal operation (pdn pin = h, power down (pdn pin = l) ? ? vrefl1/2 /3/ 4) is held +5v externally. n ote 13 . the f ull scale voltage when applying a 1khz sine wave (0db) in pcm mode, or when applying a 1khz sine wave ( 25~75% duty ) in dsd mode . o utput voltage scales with the voltage of (vrefh 1/2 /3/4 ? vrefl 1/2 /3/4 ). dac1 : aout (typ.@ 0db) = (aout+) ? (aout ? ) = ? 2.8vpp ? (vrefh1 ? vrefl1)/5 dac2 : aout (typ.@0db) = (aout+) ? (aout ? ) = ? 2.8vpp ? (vrefh2 ? vrefl2)/5 dac3 : aout (typ.@0db) = (aout+) ? (aout ? ) = ? 2.8vpp ? (vrefh3 ? vrefl3)/5 dac4 : aout (typ.@0db) = (aout+) ? (aout ? ) = ? 2.8 vpp ? (vrefh4 ? vrefl4)/5 note 14 . regarding load resistance, a c load is 2 k ? (min) with a dc cut capacitor ( figure 74 ). dc load is 3.5 k ? (m in) without a d c cut capacitor ( figure 74 ). the load resistance value is with respect to ground. analog characteristics are sensitive to capacitive load that is connected to the output pin. therefore the capacitive load must be minimized. note 15 . in the power down mode. a ll other digital input pins including clock pins (mclk, bick and lrck) are held dvss.
[ ak 4458 ] 014011794 - e - 00 2015/01 - 13 - sharp roll - off filter characteristics sharp roll - off filter characteristics (fs= 44.1khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3 .6v ; normal speed mode; dem=off; slow bit = 0 , sd bit= 0 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( note 16 ) pb 0 20.0 khz pass band ripple ( note 17 ) pr - 0.0032 0.00 32 db stop band ( note 16 ) sb 24.1 khz stop band attenuation ( note 19 ) sa 80 db group delay ( note 18 ) gd - 26.8 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ? (fs= 96khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; double sp eed mode; dem=off; slow bit = 0 , sd bit= 0 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( note 16 ) pb 0 43.5 khz pass band ripple ( note 17 ) pr - 0.0032 0.00 32 db stop band ( note 16 ) sb 52.5 0 43.5 stop band attenuation ( note 19 ) sa 80 db group delay ( note 18 ) gd - 26.8 - 1/fs frequency response ( note 19 ) ? ? di gital filter + scf ( note 19 ) frequency response : 0 ? (fs= 192khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; quad spee d mode; dem=off; slow bit = 0 , sd bit= 0 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( note 16 ) pb 0 87.0 khz pass band ripple ( note 17 ) pr - 0.0032 0.00 32 db stop band ( note 16 ) sb 105 khz stop band attenuation ( note 19 ) sa 80 db group delay ( note 18 ) gd - 26.8 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 14 - slow roll - off filter characteristics slow roll - off filter characteristics (fs = 44.1khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; normal speed mode; dem=off; slow bit = 1 , sd bit= 0 ) parameter symbol m in . t yp . m ax . unit digital filter p ass band ( no te 20 ) pb 0 8.1 khz pass band ripple ( note 17 ) pr - 0.043 0.043 db stop band ( no te 20 ) sb 39.2 stop band attenuation ( note 19 ) sa 73 db group delay ( note 18 ) gd - 6.3 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ? (fs = 96khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; double speed mode; dem=off; slow bit = 1 , sd bit= 0 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( no te 20 ) pb 0 17.7 khz pass band ripple ( note 17 ) pr - 0.043 0.043 db stop band ( no te 20 ) sb 85.3 stop band attenuation ( note 19 ) sa 73 db group delay ( note 18 ) gd - 6. 3 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ? (fs = 192khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; quad spee d mode; dem=off; slow bit = 1 , sd bit= 0 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( no te 20 ) pb 0 35.5 khz pass band ripple ( note 17 ) pr - 0.043 0.043 db stop band ( no te 20 ) sb 1 71 khz stop band attenuation ( note 19 ) sa 73 db group delay ( note 18 ) gd - 6.3 - 1/fs fr equency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 15 - short delay sharp roll - off filter characteristics short delay sharp roll - off filter characteristics (fs= 44.1khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; normal speed mode; dem=off; slow bit = 0 , sd bit= 1 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( note 16 ) pb 0 20.0 khz pass band ripple ( note 17 ) pr - 0.00 31 0.00 31 db sto p band ( note 16 ) sb 24.1 khz stop band attenuation ( note 19 ) sa 80 db group delay ( note 18 ) gd - 5.8 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ? (fs= 96khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; double speed mode; dem=off; slow bit = 0 , sd bit= 1 ) parameter s ymbol m in . t yp . m ax . unit digital filter pass band ( note 16 ) pb 0 43.5 khz pass band ripple ( note 17 ) p r - 0.00 31 0.00 31 db stop band ( note 16 ) sb 52.5 0 43.5 stop band attenuation ( note 19 ) sa 80 db group delay ( note 18 ) gd - 5.8 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ? (fs= 192khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; quad spee d mode; dem=off; slow bit = 0 , sd bit= 1 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( note 16 ) pb 0 87.0 khz pass band ripple ( note 17 ) pr - 0.00 31 0.00 31 db stop band ( note 16 ) sb 105 khz stop band attenuation ( note 19 ) sa 80 db group delay ( note 18 ) gd - 5.8 - 1/fs frequency response ( note 19 ) ? ? digit al filter + scf ( note 19 ) frequency response : 0 ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 16 - short delay slow roll - off filter characteristics short delay slow roll - off filter characteristics (fs= 44.1khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; normal speed mode; dem=off; slow bit = 1 , sd bit= 1 ) parameter symbol m in . t yp . m ax . u nit digital filter pass band ( note 21 ) pb 0 11.1 khz pass band ripple ( note 17 ) pr - 0.05 0.0 5 db stop band ( note 21 ) sb 38.1 khz stop band attenuation ( note 19 ) sa 82 db group delay ( note 18 ) gd - 4.8 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ? (fs= 96khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; double speed mode; dem=off; slow bit = 1 , sd bit= 1 ) parameter symbol m in . t yp . m ax . unit digital filter pass band ( note 21 ) pb 0 24.2 khz pass band ripple ( note 17 ) pr - 0.0 5 0.0 5 db stop band ( note 21 ) sb 83.0 43.5 stop band attenuation ( note 19 ) sa 82 db group delay ( note 18 ) gd - 4.8 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) frequency response : 0 ? (fs= 192khz) ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1.7 ? 3.6v ; quad spee d mode; dem=off; slow bit = 1 , sd bit= 1 ) parameter symbol m in . t yp . m ax . unit di gital filter pass band ( note 21 ) pb 0 48.4 khz pass band ripple ( note 17 ) pr - 0.0 5 0.0 5 db stop band ( note 21 ) sb 165.9 khz stop band attenuation ( note 19 ) sa 82 db group delay ( note 18 ) gd - 4.8 - 1/fs frequency response ( note 19 ) ? ? digital filter + scf ( note 19 ) fre quency response : 0 ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 17 - dsd mode characteristics (1) dsdf bit= 0 ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd=1.7 ? 3.6v ; fs=44.1khz ; d/p bit=1 , dsdf bit= 0 ) parameter m in . t yp . m ax . unit digital filter response frequency response ( note 22 ) dsdsel[1:0] 00 0 (2) dsdf bit= 1 ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd=1.7 ? 3.6v ; fs=44.1khz ; d/p bit=1 , dsdf bit= 1 ) parameter m in . t yp . m ax . unit digital filter response frequency response ( note 22 ) dsdsel[1:0] 00 0 dc characteristics ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd = 1. 7 ? 3.6v) parameter symbol m in . t yp . m ax . unit tvdd=1.7 ? ? ? ? ? ? ? ? ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 18 - switching characteristics ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd= 1.7 ? 3.6v , c l =20pf ) parameter symbol m in . t yp . m ax . unit master clock timing frequency duty cycle minimum pulse width fclk dclk tclkh tclkl 2.048 4 0 9.155 9.155 49.152 60 m hz % ns ns lrck frequency ( note 24 ) normal mode (tdm1 - 0 bits = 00 ) normal speed mode double speed mode quad speed mode oct speed mode hex speed mode duty cycle fsn fsd fsq fso fsh d uty 8 54 108 45 384 768 54 108 216 55 khz khz khz khz khz % tdm128 mode (tdm1 - 0 bits = 01 ) normal speed mode double speed mode quad speed mode high time low time fsn fsd fsq tlrh tlrl 8 54 108 1/128fs 1/128fs 54 108 216 khz khz khz ns e c ns tdm256 mode (tdm1 - 0 bits = 10 ) normal speed mode high time double speed mode high time low time fsn fsd tlrh tlrl 8 54 1/256fs 1/256fs 54 108 khz khz ns ec ns ec tdm512 mode (tdm1 - 0 bits = 11 ) normal speed mode high time low time fsn tlrh tlrl 8 1/512fs 1/512fs 54 khz ns ec ns ec pcm audio interface timing normal mode (tdm1 - 0 bits = 00 ) bick period normal speed mode double speed mode quad speed mode oct speed mode hex speed mode bick pulse wi dth low bick pulse width high bick ? ? tbck tbck tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/256fsn 1/128fsd 1/64fsq 1/64fso 1/64fsh 9 9 5 5 5 5 ns ec ns ec ns ec ns ec ns ec ns ec ns ec ns ec ns ec ns ec ns ec
[ ak 4458 ] 014011794 - e - 00 2015/01 - 19 - parameter symbol m in . t yp . m ax . unit tdm128 mode (tdm1 - 0 b its = 01 ) bick period normal speed mode double speed mode quad speed mode bick pulse width low bick pulse width high bick ? ? tdm2 56 mode (tdm1 - 0 bits = 10 ) bick period normal speed mode double speed mode ( note 26 ) bick pulse width low bick pulse width high bick ? ? ? ? tdm512 mode (tdm1 - 0 bits = 11 ) bick period normal speed mode ( note 27 ) bick pulse width low bick pulse width high bick ? ? ? ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 20 - parameter symbol m in . t yp . m ax . unit dsd audio interface timing (64 mode, dsdsel 1 - 0 bit s = 00 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( note 29 ) tdck tdckl tdckh tddd 144 144 ? (128 mode, dsdsel 1 - 0 bit s = 01 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( note 29 ) tdck tdckl tdckh tddd 72 72 ? (256 mode, dsdsel 1 - 0 bits = 10 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( note 29 ) tdck tdckl tdckh tddd 36 36 ? l . note 29 . dsd data transmitting device must meet this time. tddd is defined from a falling edge of dclk to a dsdl/r edge when dc kb bit = 0 and it is defined from a rising edge of dclk to a dsdl/r edge when dckb bit = 1 .
[ ak 4458 ] 014011794 - e - 00 2015/01 - 21 - ( ta= - 40 ? 105 ? c ; avdd=3.0 ? 5.5v, tvdd=1.62 ? 1.98v / 3.0 ? 3.6v) parameter symbol m in . t yp . m ax . unit control interface timing (3 - wire serial mode): cc lk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ? ? ? ? co ntrol interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 30 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capaci tive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 1.0 0.3 - 50 400 khz ? sec ? sec ? sec ? sec ? sec ? sec ? sec ? sec ? sec ? sec nsec pf power - down & reset tim ing ( note 31 ) pdn accept pulse width pdn reject pulse width tapd trpd 150 30 nsec nsec note 30 . data must be held for sufficient time to bridge the 300 ns tr ansition time of scl. note 31 . the ak44 58 can be reset by setting the pdn pin to l upon power - up. the pdn pin must held l for more than 150ns for a certain reset. the ak44 58 is not reset by the l pulse less than 30ns. note 32 . i 2 c is a trademark of nxp b.v.
[ ak 4458 ] 014011794 - e - 00 2015/01 - 22 - timing diagram figure 2 . clock timing figure 3 . audio interface timing (pcm mode) 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tlrl tlrh duty=tlrh x fs, tlrl x fs tbck tbckl vih tbckh bick vil tlrb lrck vih bick vil tdm o 5 0% t vdd tbss vih vil tblr tsds sdti vih vil tsdh tbsh
[ ak 4458 ] 014011794 - e - 00 2015/01 - 23 - figure 4 . audio serial interface timing (dsd normal mode, dckb bit = 0 ) figure 5 . audio serial interface timing (dsd phase modulation mode, dckb bit = 0 ) vih dclk vil tddd vih dsdl 1 - 4 dsdr 1 - 4 vil tdckh tdckl tdck tddd vih dsdl1 - 4 dsdr1 - 4 vil vih dclk vil tddd vih dsdl 1 - 4 dsdr 1 - 4 vil tdckh tdckl tdck tddd tddd vih dsdl 1 - 4 dsdr 1 - 4 vil tddd
[ ak 4458 ] 014011794 - e - 00 2015/01 - 24 - figure 6 . write command input timing ( 3 - wire serial mode) figure 7 . write data input timing ( 3 - wire serial mode) tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh
[ ak 4458 ] 014011794 - e - 00 2015/01 - 25 - figure 8 . i 2 c bus mode timing figure 9 . power - down & reset timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp tapd trpd pdn vil tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 t apd tcckh tcds tcdh
[ ak 4458 ] 014011794 - e - 00 2015/01 - 26 - 9. functional descriptions d/a conversion mode ( pcm mode, dsd mode ) t he ak 44 58 can perform d/a conversion for either pcm data or dsd data. the d p bit controls pcm/dsd mode. when dsd mode, dsd data can be input from dclk, dsdl and dsdr pins. when pcm mode, pcm data can be input from bick, lrck and sdti pins. when pcm/dsd mode is ch ange d by d p bit , the ak 4458 should be reset by rstn bit. it takes about 2/fs to 3/fs to change the mode. only a pcm data is supported in parallel mode. dp bit interface 0 pcm 1 dsd table 1 . pcm/dsd mode control system clock [1] pcm m ode the external clocks, which are required to operate the ak 4458 , are mclk, bick and lrck. mclk should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta - sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks bit= 0: default), the sampling speed is set by dfs0, dfs1 ( table 2 ). the frequency of mclk at each sampling spee d is set automatically. when reset is released (pdn pin = ), the ak4458 is in manual setting mode. in auto setting mode (acks bit= 1), as mclk frequency is detected automatically ( table 5 ) and the internal master clock attains the appropriate frequency ( table 6 , table 7 ), so it is not necessary to set dfs bits .
[ ak 4458 ] 014011794 - e - 00 2015/01 - 27 - 1. manual setting mode (acks bit = 0 ) mclk frequency is detected automatical ly and the sampling rate is set by dfs 2 - 0 bit s ( table 2 ). the mclk frequency corresponding to each sampling speed should be provided externally ( table 3 , table 4 ). the ak 4458 is set to manual setting mode at power - up (pdn pin = l h). when dfs 2 - 0 bits are changed, the ak 4458 should be reset by rstn bit. dfs2 dfs1 dfs0 sampling rate (fs) (default) 0 0 0 normal speed mode 8khz ? ? ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 28 - 2. auto setting mode (acks bit = 1 ) mclk frequency and the sam pling speed are detected automatically ( table 5 ) and dfs 2 - 0 bits are ignored. the mclk frequency corresponding to each sampling speed should be provided externally ( table 6 , table 7 ). mclk sampling spe ed 1152fs normal (fs ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 29 - [2] dsd m ode the ak4458 is capable to playback dsd data. the external clocks, which are required to operate the ak4 458 , are mclk and dclk. mclk should be synchronized with dclk but the phase is not critical. the frequency of mclk is set by dcks bit. ( table 9 ) after exiting reset (pdn pin = l h , rstn bit= 0 1 ) upo n power - up , the ak4458 is in power - down s tate until mclk and dclk are input. dcks bit mclk frequency dclk frequency 0 512fs 64fs/128fs/256fs (default) 1 768fs 64fs/128fs/256fs table 9 . system clock (dsd mode) the ak4458 supports 64fs, 128fs and 256fs data stream (f s= 32khzm 44.1khz, 48khz). dsdsell1 - 0 bits control this setting. ( table 10 ) dsdsel1 dsdsel0 dsd data stream fs=32khz fs=44.1khz fs=48khz 0 0 2.048mhz 2.8224mhz 3.072mhz (default) 0 1 4.096mhz 5.6448mhz 6.1 44mhz 1 0 8.192mhz 11.2896mhz 12.288mhz 1 1 reserved reserved reserved table 10 . dsd d ata s tream s elect dsdd bit selects dsd playback mode ( table 11 ) . when dsdd bit= 1 , the output volume control is not available and the cut off filter value is fixed to 100khz. d sdd bit mode 0 full function (default) 1 volume by pass table 11 . dsd p lay back mode s elect the cut off filter characteristic in dsd mode can be selected by dsdf bit. ( table 12 ) dsdf bit cut off filter 0 50khz (default) 1 100khz table 12 . dsd f ilter s elect
[ ak 4458 ] 014011794 - e - 00 2015/01 - 30 - audio interface format the ak4458 supports both pcm and dsd for mats for digital input signal. mode settings are available by the pins (tdm1 - 0 pins, dif pin and dchain pin) and registers ( tdm1 - 0 bits, dif2 - 0 bits, sds2 - 0 bits and dchain bit ) but do not change these settings during operation . [ 1 ] pcm mode normal mode ( tdm1 - 0 bit s = 00 ) eight channels audio d ata is shifted in via the sdt i1 - 4 pin s using bick and lrck inputs. data is selected by sds2 - 0 bits. eight data formats are supported and selected by the dif2 - 0 bits as shown in table 13 . in all formats the serial data is msb first, 2's compliment format an d is clocked in on t he rising edge of bick. mode 2 can be used in 16 - bit and 20 - bit msb justified and mode 6 can be used in 16 - bit , 20 - bit and 24 - bit msb justified formats by zeroing the unused lsbs. tdm128 mode ( tdm1 - 0 bit s = 01 ) eight channels audio d ata is shifted in via the sdt i1 - 2 pin s using bick and lrck inputs. data is selected by sds2 - 0 bits. the data input to the sdti3 - 4 pins are ignored. bick is fixed to 128fs. s ix data formats are supported and selected by the dif2 - 0 bits as shown in table 13 . in all formats the serial data is msb first, 2's compliment format and is clocked in o n the rising edge of bick. tdm256 mode ( t dm1 - 0 bit s = 10 ) sixteen channels audio d ata is shifted in via the sdt i1 - 2 pin s using bick and lrck inputs. data is selected by sds2 - 0 bits. the data input to the sdti3 - 4 pins are ignored. bick is fixed to 256 fs. six data formats are supported and selected by the dif2 - 0 bits as shown in table 13 . in all formats the serial data is msb first, 2's compliment format and is clocked in o n the rising edge of bick. tdm512 mode ( tdm1 - 0 bit s = 11 ) sixteen channels audio d a ta is shifted in via the sdt i1 pin using bick and lrck inputs. data is selected by sds2 - 0 bits. the data input to the sdti2 - 4 pins are ignored. bick is fixed to 512 fs. six data formats are supported and selected by the dif2 - 0 bits as shown in table 13 . in all formats the serial data is msb first, 2's compliment format and is clocked in on the rising edge of bick.
[ ak 4458 ] 014011794 - e - 00 2015/01 - 31 - mode tdm1 tdm0 dif2 dif1 dif0 sdti format lrck bick normal ( note 33 ) 0 0 0 0 0 0 16 - bit lsb justified h/l ? ? ? 2 s compatible l/h ? ? ? ? 2 s compatible l/h ? ? ? ? 2 s compatible ? ? ? ? 2 s compatible ? ? ? ? 2 s compatible ? ? ? ? 2 s compatible ? ? ? ? 2 s compatible ? ? ? ? 2 s compatible ?
[ ak 4458 ] 014011794 - e - 00 2015/01 - 32 - figure 10 . mode 0 timing figure 11 . mode 1/ 4 timing figure 12 . mode 2 timing sd ti1 - 4 bick lrck sd ti1 - 4 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 (32fs) (64fs) 0 14 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don t care don t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data sd ti1 - 4 lrck bick (64fs) 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don t care don t care 1 9:msb, 0:lsb sd ti1 - 4 mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don t care don t care 22 21 22 21 lch data rch data 8 23 23 8 lrck bick (64fs) sd ti1 - 4 0 22 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don t care 23 lch data rch data 23 30 22 2 24 23 30 22 1 0 don t care 23 22 23
[ ak 4458 ] 014011794 - e - 00 2015/01 - 33 - figure 13 . mode 3 timing figure 14 . mode 5/6 timing figure 15 . mode 7 timing lrck bick (64fs) sd ti1 - 4 0 3 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don t care 23 lch data rch data 23 25 3 2 24 23 25 22 1 0 don t care 23 23 lrck bick (64fs) sd ti1 - 4 0 22 1 2 24 31 0 1 31 0 1 32:msb, 0:lsb 30 1 0 31 lch data rch data 23 30 22 2 24 23 3 0 30 1 0 31 30 31 mode 5,6 lrck bick (64fs) sd ti1 - 4 0 3 1 2 24 31 0 1 31 0 1 32:msb, 0:lsb 30 1 0 31 lch data rch dat a 23 25 3 2 24 23 25 30 1 0 31 30 31
[ ak 4458 ] 014011794 - e - 00 2015/01 - 34 - figure 16 . mode 8/11 /12 timing figure 17 . mode 9/13 timing figure 18 . mode 10 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick sd ti1 - 2 22 0 22 0 22 0 22 0 23 23 23 23 22 23 mode 8 sd ti1 - 2 30 0 30 0 30 2 0 30 0 31 31 31 31 30 31 mode 11 ,1 2 lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick sd ti1 - 2 22 0 22 0 22 0 22 0 23 23 23 23 23 sd ti 1 - 2 mode 9 mode1 3 30 0 30 0 30 2 0 30 0 31 31 31 31 30 31 lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick sd ti1 - 2 22 0 22 0 22 0 22 0 23 23 23 23 23
[ ak 4458 ] 014011794 - e - 00 2015/01 - 35 - figure 19 . mode 14 /1 7 /1 8 timing figure 20 . mode 15 /1 9 timing figure 21 . mode 1 6 timing 23 lrck bick (256fs) 22 0 l1 32 bick 256 bick 22 0 r1 32 bick 22 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 s dti 1 31 30 0 30 31 31 30 0 31 30 0 31 30 0 s dti 1 mode 14 mode 17 ,1 8 23 22 0 l3 32 bick 22 0 r3 32 bick 23 22 0 l4 32 bick 22 0 r4 32 bick 23 23 31 30 0 31 30 0 31 30 0 31 30 0 lrck bick (256fs) 23 0 l1 32 bick 256 bick 23 0 r1 32 bick 23 23 0 l2 32 bick 23 0 r2 32 bick sd ti 1 mode 15 31 0 31 30 31 0 30 31 0 30 31 0 30 sd ti 1 mode1 9 23 0 l3 32 bick 23 0 r3 32 bick 23 0 l4 32 bick 23 0 r4 32 bick 31 0 30 31 0 30 31 0 30 31 0 30 lrck bick(256fs) sd ti1 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 23 23 23 23 23 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 23 23 23 23
[ ak 4458 ] 014011794 - e - 00 2015/01 - 36 - figure 22 . mode 20 / 23 / 24 timin g figure 23 . mode 21 / 25 timing figure 24 . mode 22 timing bick(512fs) s dti1 mode8 lrck 512bick 22 0 23 22 0 23 22 0 23 22 0 23 22 2 0 23 22 0 23 22 0 23 22 0 23 sdti1 mode11,12 l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 32 bick 32 bick 32 bick 3 2 bick 32 bick 32 bick 32 bick 32 bick 22 0 31 23 22 0 31 22 0 31 22 0 31 22 0 31 22 0 31 22 0 31 22 0 31 31 bick(512fs) s dti1 mode 21 lrck 512bick 22 0 23 22 0 23 22 0 23 22 0 23 22 2 0 23 22 0 23 22 0 23 22 0 23 sdti1 mode 25 l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 22 0 31 23 22 0 31 22 0 31 22 0 31 22 0 31 22 0 31 22 0 31 22 0 31 31 bick(512fs) s dti1 mode 22 lrck 512bick 22 0 23 22 0 23 22 0 23 22 0 23 22 2 0 23 22 0 23 22 0 23 22 0 23 l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 23
[ ak 4458 ] 014011794 - e - 00 2015/01 - 37 - [ 1 ] - 1. data select one data cycle of sd ti 1 - 4 for each format are defined as below. sds2 - 0 bits control playback channel of each dac. figure 25 . data slot in normal mode figure 26 . data slot in tdm128 mode figur e 27 . data slot in tdm256 mode figure 28 . data slot in tdm512 mode lrck sd ti 1 r1 l1 sd ti 2 r 2 l2 sd ti 3 r 3 l 3 sd ti 4 r 4 l4 sd ti 1 r1 l1 sd ti 2 lrck 128 bick r 2 l2 r3 l3 r 4 l4 sd ti 1 r1 l1 lrck 256 bick r 2 l2 r 3 l 3 r 4 l 4 sd ti 2 r 5 l 5 r 6 l 6 r 7 l 7 r 8 l 8 sd ti1 r1 l1 lrck 512 bick r 2 l 2 r 3 l 3 r 4 l 4 r 5 r 6 l 6 r 7 l 7 r 8 l 8 l 5
[ ak 4458 ] 014011794 - e - 00 2015/01 - 38 - sd s2 sd s 1 sd s0 dac1 dac2 dac 3 dac 4 l ch r ch l ch r ch l ch r ch l ch r ch normal * 0 0 l1 r1 l2 r2 l3 r3 l4 r4 * 0 1 l1 r1 l1 r1 l3 r3 l3 r3 * 1 0 l2 r2 l2 r2 l4 r4 l4 r4 * 1 1 l2 r2 l1 r1 l4 r4 l3 r3 tdm128 * 0 0 l1 r1 l2 r2 l3 r3 l4 r4 * 0 1 l1 r1 l4 r4 l3 r3 l2 r2 * 1 0 l3 r3 l2 r2 l1 r1 l4 r4 * 1 1 l3 r3 l4 r4 l1 r1 l2 r2 tdm256 0 0 0 l1 r1 l2 r2 l3 r3 l4 r4 0 0 1 l2 r2 l3 r3 l4 r4 l 5 r 5 0 1 0 l3 r3 l4 r4 l 5 r 5 l 6 r 6 0 1 1 l4 r4 l 5 r 5 l 6 r 6 l 7 r 7 1 0 0 l 5 r 5 l 6 r 6 l 7 r 7 l8 r8 1 0 1 l 6 r 6 l 7 r 7 l8 r8 l 1 r 1 1 1 0 l 7 r 7 l8 r8 l 1 r 1 l 2 r 2 1 1 1 l8 r8 l 1 r 1 l 2 r 2 l 3 r 3 tdm512 0 0 0 l1 r1 l2 r2 l3 r3 l4 r4 0 0 1 l2 r2 l3 r3 l4 r4 l 5 r 5 0 1 0 l3 r3 l4 r4 l 5 r 5 l 6 r 6 0 1 1 l4 r4 l 5 r 5 l 6 r 6 l 7 r 7 1 0 0 l 5 r 5 l 6 r 6 l 7 r 7 l8 r8 1 0 1 l 6 r 6 l 7 r 7 l8 r8 l 1 r 1 1 1 0 l 7 r 7 l8 r8 l 1 r 1 l 2 r 2 1 1 1 l8 r8 l 1 r 1 l 2 r 2 l 3 r 3 (*: d o n o t care ) table 14 . data select
[ ak 4458 ] 014011794 - e - 00 2015/01 - 39 - [1 ] - 2. daisy chain multiple ak4458 s can be connected by daisy c hain . daisy chain mode can be arranged from dchain bit or dchain pin ( table 15 ). daisy chain supports tdm512/256 mode. dchain bit dchain pin mode tdmo1/2 0 normal input(sdti3/4) (default) 1 daisy chain output(tdmo1/2) table 15 . daisy chain control (1) tdm512 mode figure 29 shows example of tdm512 mode daisy chain structure (tdm1 - 0 bits= 11 ). 16ch data is input to the s econd ak4458 s sdti1 pin from a dsp. connect the s econd ak4458 s tdmo1 pin to the f irst ak4458 s sdti1 pin . tdmo1 is 8ch shifted data of sdti1. at tdm512 mo de, tdmo2 outputs "l". figure 30 shows data i/o example of tdm512 mode. sdti1 (l5 - 8, r5 - 8) data is the input for the dac of the s econd a k4458 , and the s econd ak4458 outputs the data from tdmo1 by shifting 8ch. t h e f irst ak4458 accepts sdti1 (l1 - 4, r1 - 4) data as input data of dac. dif2 - 0 bits setting of both f irst ak4458 and the s econd ak4458 must be the same. figure 29 . daisy chain for two devices (tdm5 12 mode) figure 30 . daisy chai n for two devices (tdm 512 mode) first ak4458 second ak4458 dsp sdti1 tdmo 1 sdti1 tdmo 1 sdti 2 tdmo2 sdti 2 tdmo2 dvss sd ti1 (dsp) r1 l1 lrck 512 bick r 2 l 2 r 3 l 3 r 4 l 4 r 5 r 6 l 6 r 7 l 7 r 8 l 8 l 5 tdmo 1 (second) second ak4458 first ak4458 r 1 r 2 l 2 r 3 l 3 r 4 l 4 l 1
[ ak 4458 ] 014011794 - e - 00 2015/01 - 40 - when the total number of connected channel is more than sixteen, exceeded channel data that are over 16ch are output from the last data of a 16ch signal output from the dsp in the same order ( figure 31 , figure 32 ) . figure 31 . daisy chain for three devices (tdm512 mode) figure 32 . daisy chain for three devices (tdm512 mode) second ak4458 third ak4458 dsp sdti1 tdmo 1 sdti1 tdmo 1 sdti 2 tdmo2 sdti 2 tdmo2 dvss first ak4458 sdti1 tdmo1 sdti 2 tdmo2 sd ti1 (dsp) lrck 512 bick tdmo 1 (third) third ak4458 tdmo1(second) r 5 r 6 l 6 r 7 l 7 r 8 l 8 l 5 first ak4458 r 1 r 2 l 2 r 3 l 3 r 4 l 4 l 1 second ak4458 r 5 r 6 l 6 r 7 l 7 r 8 l 8 l 5 r1 l1 r 2 l 2 r 3 l 3 r 4 l 4 r 5 r 6 l 6 r 7 l 7 r 8 l 8 l 5
[ ak 4458 ] 014011794 - e - 00 2015/01 - 41 - (2) tdm256 mode figure 33 shows example of tdm256 mode daisy chain structure (tdm1 - 0 bits= 10 ). 16ch data is input to the s econd ak4458 s sdti1/2 pin from a dsp. connect the s econd ak4458 s tdmo1/2 pin to the f irst ak4458 s sdti1/2 pin . tdmo1/2 are 4ch shifted data of sdti1/2. figure 34 shows data i/o example of tdm256 mode. sdti1 ( l3 - 4 , r3 - 4 ) and sdti2 (l7 - 8, r7 - 8) data is the input for the dac of the second ak4458, and the second ak4458 outputs the data from tdmo1/2 by shifting 4ch . t he f irst ak4458 accepts sdti1 (l1 - 2, r1 - 2 ) and sdti2 (l5 - 6, r5 - 6) da ta as input data of dac . dif2 - 0 bits setting of both f irst ak4458 a nd the s econd ak4458 must be the same. figure 33 . daisy chain (tdm 256 mode) figure 34 . daisy chain (tdm256 mode) note 34 . when the total number of connected channel is more than sixteen, exceeded channel data that are over 16ch are output from the last data of a 16ch signal output from the dsp in the same order. first ak4458 second ak4458 dsp sdti1 tdmo 1 sdti1 tdmo 1 sdti 2 tdmo2 sdti 2 tdmo2 sdti1 r1 l1 lrck 256 bick r 2 l2 r3 l 3 r 4 l4 tdmo1 r1 l1 r 2 l2 second ak4458 first ak4458 sdti2 r 5 l 5 r 6 l6 r7 l7 r 8 l8 tdmo2 r5 l5 r 6 l6 second ak4458 first ak4458
[ ak 4458 ] 014011794 - e - 00 2015/01 - 42 - [ 2 ] dsd mode 8ch data is shifted in via the dsdl1 - 4 and dsdr1 - 4 pins using dclk inputs. dsd data is supported by both normal mode ( figure 35 ) and phase modulation mode ( figure 36 ) . input data is clocked in on a rising or falling edge of dclk that is set by dckb bit. the frequency of dclk is variable at 64fs, 128fs a nd 256fs by setting dsdsel1 - 0 bits . figure 35 . dsd mode timi ng (normal mode) figure 36 . dsd mode timing (phase modulation m ode) dclk ( dckb bit = 0 ) dsdl,dsdr d1 d0 d2 d3 dclk ( dckb bit = 0 ) d0 d1 d2 d1 d2 d3 dsdl,dsdr
[ ak 4458 ] 014011794 - e - 00 2015/01 - 43 - d/a conversion mo de (pcm mode, dsd mode) swit ching timing figure 37 . d/a mode switching timing (pcm to dsd) figure 38 . d/a mode switching timing ( dsd to pcm) note 35 . the signal range is defined as 25% ~ 75% duty ratios in dsd mode. dsd signal must not go beyond this duty range at the sacd format book (scarlet book). rstn bit d/a data d/a mode ? 5 /fs ? 0 pcm data dsd data pcm mode dsd mode rstn bit d/a data d/a mode ? 5 /fs dsd data pcm data dsd mode pcm mode
[ ak 4458 ] 014011794 - e - 00 2015/01 - 44 - digital filter ( pcm mode ) four digital filters are av ailable for playback, providing a choice of different sound colors . these d i gital filters are selected by sd bit, slow bit and sslow bit. sslow sd bit slow bit mode 0 0 0 sharp roll - off f ilter 0 0 1 slow roll - off f ilter 0 1 0 short delay sharp roll - off f ilter (default) 0 1 1 short delay slow roll - off f ilter 1 * * super slow roll - off filter table 16 . digital f i lter setting (*: do not care) t h e slowest frequency characteristics setting is w hen sslow bit = 1 . de-emphasis filter ( pcm mode ) a digital de-emphasis filter is available for 32 khz , 44.1 khz or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem1 1 - 1 0 / dem 21 - 2 0/ dem 31 - 30/ dem 41 - 40 bits (dem bits) . dem11 - 10/dem21 - 20/dem31 - 30/dem41 - 40 bits control de - emphasis mode of dac1/2/3/4, respectively. this mode is only valid in pcm normal speed mode. dem 1 1 / dem21/ dem 3 1 / dem41 dem 1 0 / dem20/ dem 3 0 / dem40 mode 0 0 44.1khz 0 1 off (d efault ) 1 0 48khz 1 1 32khz table 17 . dac1/2/3/4 de - emphasis control
[ ak 4458 ] 014011794 - e - 00 2015/01 - 45 - output volume ( pcm mode , dsd mode ) the ak4458 has a channel - independent digital attenuator (256 levels, 0.5db steps). attenuation level of each dac1 - 4 can be set by at t 7 - 0 bit s (register 0a - 11 h) , respectively ( table 18 ). input data is attenuated from 0db to - 127db including mute. the transition between set values is a soft transition, thus no switching noise is occurred . at t 7 - 0bits (register 0a - 11h) attenuation level ff h +0db (default) fe h - 0.5db fd h - 1.0 db : : : : 02h - 126.5db 01 h - 127.0db 00 h mute ( - ) pin goes to l, at t 7 - 0 bits are initialized to ff h . if the digital volume is changed during reset, the volume will be changed to the setting value after releasing the reset. if the volume is changed in 5/fs after releasing a reset, the volume is changed immediately without soft transition. in dsd mode, the digital volume is set to mute by setting att7 - 0 bits = 02h or 01h .
[ ak 4458 ] 014011794 - e - 00 2015/01 - 46 - out of band noise reduction f i lter ( pcm mode , dsd mode ) the ak4458 has an out of band noise reduction filter that can change frequency response. this fir filter attenuate s out of band noise and prevents a degradation of the analog characteristics caused by a switching regulator, etc. fir2 - 0 bits set the frequency for noise attenuation. the filter characteristics will differ in dsd direct mode compared with other modes ( table 20 ) . fir2 - 0 bits fir filter mode fi r filter e xcept dsd direct mode dsd direct mode 000 0 1/4*[1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 ] 1/ 2 *[ 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] (default) 001 1 1/4*[1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1] 1/ 2 *[ 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ] 010 2 1/4*[1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1] 1/ 2 *[ 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 ] 011 3 1/4*[1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1] 1/ 2 *[ 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 ] 100 4 1/4*[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1] 1/ 2 *[ 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 ] 101 5 1/4*[1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1] 1/ 2 *[ 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ] 110 6 1/4*[1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1] 1/ 2 *[ 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 ] 111 7 1/4*[1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1] 1/ 2 *[ 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] table 20 . fir f ilter s etting figure 39 . mode0 fir f ilter (except dsd direct mode) figure 40 . mode1 fir filter ( e xcept dsd direct mode)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 47 - figure 41 . mode2 fir filter (e xcept dsd direct mode) figure 42 . mode3 fir filter (e xcept dsd direct mode) figure 43 . mode4 fir filter (e xcept dsd direct mode)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 48 - figure 44 . mode5 fir filter (e xcept dsd direct mode) figure 45 . mode6 fir filter ( e xcept dsd direct mode) figure 46 . mode7 fir filter (e xcept dsd direct mode)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 49 - figure 47 . mode0 fir f ilter (dsd d irect m ode) fig ure 48 . mode1 fir filter ( dsd d irect m ode) figure 49 . mode2 fir filter (dsd d irect m ode)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 50 - figure 50 . mode3 fir filter ( dsd d irect m ode) figure 51 . mode4 fir filter ( dsd d irect m ode) figure 52 . mode5 fir filter ( dsd d irect m ode)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 51 - figure 53 . mode6 fir filter ( dsd d irect m ode) figure 54 . mode7 fir filter (e xcept dsd d irect m ode)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 52 - zero detection ( pcm mode, dsd mode ) when zero detect ion function is enabled, the dzf pin goes to h if the input data at each channel is continuously zero s for 8192 lrck cycles . zero detection channels (aoutl1 - 4n/p and aoutr1 - 4n/p pins) can be selected by 07h/08h registers (l1 - 4 bits, r1 - 4 bits). the dzf pin immediately returns to l if the input data of each channel is not zero. if the rstn bit is 0 , the dzf pins of both channels go to h . the dzf pin of both channel s go to l after 4 ~ 5/fs when rstn bit returns to 1 . the dzfb bit can invert the polarity of the dzf pin. if all channels are disabled, the dzf pin outputs not zero . zero detection function is disabled when dsdd bit = 1 . dzfb bit data dzf pin 0 n ot zero l z ero detect h 1 n ot zero h z ero detect l n ot zero: one of the zero detection channels set by l1 - 4 bi ts and r1 - 4 bits does not detect zero. z ero detect: all zero detection channels set by l1 - 4 bits and r1 - 4 bits detect zero. table 21 . dzf pin f unction lr channel ou tput signal select ( pcm mode, dsd mode ) input and output signal combination of aoutl1 - 4 and aoutr1 - 4 pins can be set by mono 1 - 4 bit s and sellr 1 - 4 bit s . the output signal phase of dac is controlled by invl 1 - 4 and invr 1 - 4 bits. with these set tings, sixteen patterns of signal combinations are available for dac1 - 4. these settings are available for any audio format. mono 1 bit sellr1 bit invl1 bit invr1 bit l 1 ch out r 1 ch out 0 0 0 0 l1ch in r1ch in 1 0 l1ch in invert r1ch in 0 1 l1ch in r 1ch in invert 1 1 l1ch in invert r 1ch in invert 0 1 0 0 r1ch in l1ch in 1 0 r1ch in invert l1ch in 0 1 r1ch in l1ch in invert 1 1 r1ch in invert l1ch in invert 1 0 0 0 l1ch in l1ch in 1 0 l1ch in invert l1ch in 0 1 l1ch in l1ch in inve rt 1 1 l1ch in invert l1ch in invert 1 1 0 0 r1ch in r1ch in 1 0 r1ch in invert r1ch in 0 1 r1ch in r1ch in invert 1 1 r1ch in invert r1ch in invert table 22 . output select for dac 1
[ ak 4458 ] 014011794 - e - 00 2015/01 - 53 - mono 2 bit sellr2 bit invl2 bit in vr2 bit l 2 ch out r 2 ch out 0 0 0 0 l2ch in r2ch in 1 0 l2ch in invert r2ch in 0 1 l2ch in r 2ch in invert 1 1 l2ch in invert r 2ch in invert 0 1 0 0 r2ch in l2ch in 1 0 r2ch in invert l2ch in 0 1 r2ch in l2ch in invert 1 1 r2ch in invert l 2ch in invert 1 0 0 0 l2ch in l2ch in 1 0 l2ch in invert l2ch in 0 1 l2ch in l2ch in invert 1 1 l2ch in invert l2ch in invert 1 1 0 0 r2ch in r2ch in 1 0 r2ch in invert r2ch in 0 1 r2ch in r2ch in invert 1 1 r2ch in invert r2ch in inver t table 23 . output select for dac 2 mono 3 bit sellr 3 bit invl 3 bit invr 3 bit l 3 (aoutl 3 n, aoutl 3 p pins ) r3 (aou tr3 n, aout r3 p pins ) 0 0 0 0 l 3 r 3 1 0 l 3 invert r 3 0 1 l 3 r 3 invert 1 1 l 3 invert r 3 invert 0 1 0 0 r 3 l 3 1 0 r 3 invert l 3 0 1 r 3 l 3 invert 1 1 r 3 invert l 3 invert 1 0 0 0 l 3 l 3 1 0 l 3 invert l 3 0 1 l 3 l 3 invert 1 1 l 3 invert l 3 invert 1 1 0 0 r 3 r 3 1 0 r 3 invert r 3 0 1 r 3 r 3 invert 1 1 r 3 invert r 3 invert table 24 . output select for dac 3
[ ak 4458 ] 014011794 - e - 00 2015/01 - 54 - mono 4 bit sellr 4 bit invl 4 bit invr 4 bit l 4 (aoutl 4 n, aoutl 4 p pins ) r4 (aou tr4 n, aout r4 p pins ) 0 0 0 0 l 4 r 4 1 0 l 4 invert r 4 0 1 l 4 r 4 invert 1 1 l 4 invert r 4 invert 0 1 0 0 r 4 l 4 1 0 r 4 invert l 4 0 1 r 4 l 4 invert 1 1 r 4 invert l 4 invert 1 0 0 0 l 4 l 4 1 0 l 4 invert l 4 0 1 l 4 l 4 invert 1 1 l 4 invert l 4 invert 1 1 0 0 r 4 r 4 1 0 r 4 invert r 4 0 1 r 4 r 4 invert 1 1 r 4 invert r 4 invert table 25 . output select for dac 4 sound quality adjustment ( pcm m ode, dsd m ode ) the sound color of the ak4458 can be controlled by sc1 - 0 bit s. s c 1 s c 0 sound mode 0 0 1 (default) 0 1 2 1 0 3 1 1 reserved table 26 . sound quality select m ode
[ ak 4458 ] 014011794 - e - 00 2015/01 - 55 - dsd f ull scale (fs) signal detection function the ak44 58 has a full scale signal detection function for each channel in dsd mode. when the input data of each channel (dsdl1/2/3/4, dsdr1/2/3/4) is continuously 0 ( - fs) or 1 (+fs) for 2048 cycles, the ak4458 detects a full scale signal and outputs 1 on the dml1/2/3/4 and dmr1/2/3/4 bits. the output data is muted if a full scale signal is detected. when dsdd bit = 0 , the output data is changed in soft transition, and the output data is changed without soft transition when dsdd bit = 1 . a recovering condition to normal operation mode from full scale detection status is selected by dmc bit if ddm bit = 1 . when dmc bit = 0 , the ak4458 will return to normal operation automatically by inputting a normal signal. when dmc bit = 1 , the ak4458 will return to normal operation mode by writing 1 to dmre bit. d sdd bit mode status after detection 0 normal p ath dsd m ute (default) 1 volum e by pass pd table 27 . dsd mode and the devic e status after full scale detection (ddm bit= 0 ) figure 55 . analog output waveform when dsd fs is detected (dsd d bit = 1 ) figure 56 . anal og output waveform when dsd fs is detected (dsd d bit = 0 ) dsd error (ddr or ddlbit ) d sd data dsd data dsd data (fs or - fs ) dsd data 2048fs aout dsd error (ddr or ddlbit ) d sd data dsd data dsd data (fs or - fs ) dsd data 2048fs aout
[ ak 4458 ] 014011794 - e - 00 2015/01 - 56 - soft mute operation ( pcm mode , dsd mode ) the s oft mute operation is performed at digital domain. when the smute pin goes to h or set smute bit to 1 , the output signal is attenuated by ? ? during att_data ? att transition time from the current att lev el . when the smute pin is returned to l or the smute bit is returned to 0 , the mute is cancelled and the output attenuation gradually changes to the att level during att_data ? att transition time . if the soft mute is cancelled before attenuating ? ? , t he attenuation is discontinued and returned to att level by the same cycle . the soft mute is effective for changing the signal source without stopping the signal transmission. notes: ( 1) att_data ? att transition time. for ex ample, this time is 4080 lrck cycles (1020/fs) at att_data=255 in normal speed mode. (2) the a nalog outpu t corresponding to the digital input has group delay (gd). (3) if the soft mute is cancelled before attenuating ? ? after starting the operation, the att enuation is discontinued and returned to att level by the same cycle . (4) when the input dat a for a zero detection channel is continuously zeros for 8192 lrck cycles, the dzf pin goes to h . the dzf pin immediately returns to l if input data are not zer o. figure 57 . soft mute function smute pin or smute bit attenuat ion dzf pin att_level - ? aout 8192/fs gd gd (1) (2) (3) (4) (1) (2)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 57 - error detection three types of error can be detected in i 2 c mode when the ldoe pin = h . ( table 28 ) no error error condition 1 internal referenc e voltage error internal reference voltage is not powered up. 2 ldo over voltage detection ldo voltage > 2. 2 ~ 2.5v 3 ldo over current detection ldo current < 4 0 ~ 1 1 0ma table 28 . error detection in i 2 c mode, t h e ak4458 does no t generate acknowledge (ack) in error status. system reset the ak4458 should be r eset once by bringing the pdn pin = l upon power - up. in pcm (dsd) mode, t he ak4458 exits this system reset (power - down mode) by mclk and lrck (dclk) after the pdn pin = h . the ak4458 detects a rising edge of mclk f irst, and then t he analog block exits power - down mode by a rising edge of lrck (dclk) . t he digital block exits power - down mode after the internal counter counts mclk for 4/fs.
[ ak 4458 ] 014011794 - e - 00 2015/01 - 58 - power down function the ak4458 is placed in power - down mode by bringing th e pdn pin l and t he analog outputs become floating (hi - z) state . power - up and power - down timings are shown in figure 58 . n otes: (1) after avdd and tvdd are powered - up , the pdn pin shoul d be l for 150ns . (2) after pdn pin = h, the internal ldo po wer - up if the ldoe pin = h . the in ternal circuits will be power ed up afte r shutdown switch is o n in the end of a counter by the internal oscillator ( 10 ms (max ) ). if the ldoe pin = l , the shutdo wn switch is activated after the ak4458 is powered up. the internal circuit s will be powered up in 1msec (max) after the activation of the shutdown switch. (3) the analog output corresponding to digital input has group delay (gd). (4) analog outputs are floating (hi - z) in power down mode. (5) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (6) mute the analog output externally if click noise (3) adversely affect system performance the timing example is shown in this figure. ( 7 ) the dzf pin is l in the internal power - down mode. figure 58 . power down /up sequence example pdn pin power reset normal operation ( register write and dac input are available ) clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on ( 6 ) dzf 0 data gd ( 3 ) ( 5 ) ( 7 ) gd ( 5 ) mute on 0 data don t ca re internal state ( 4 ) ( 4 ) (1) i nternal pdn (2) vdd 18 pin
[ ak 4458 ] 014011794 - e - 00 2015/01 - 59 - power off and r eset function s rstn pw1/2/3/4 dac1/2/3/4 register digital analog output dac1 dac2 dac3 dac4 1 0000 off/off /off/off hold off hi - z hi - z hi - z hi - z 1 1000 on/off/off/off hold on normal hi - z hi - z hi - z 1 0100 off/on/off/off hold on hi - z normal hi - z hi - z 1 0010 off/off/on/off hold on hi - z hi - z normal hi - z 1 0001 off/off/off/on hold on hi - z hi - z hi - z normal 1 111 1 on/on/on/on hold on normal normal normal normal 0 0000 off /off/off/off hold off hi - z hi - z hi - z hi - z 0 1000 on/off/off/off hold off vrefh/2 hi - z hi - z hi - z 0 0100 off/on/off/off hold off hi - z vrefh/2 hi - z hi - z 0 0010 off/off/on/off hold off hi - z hi - z vrefh/2 hi - z 0 0001 off/off/off/on hold off hi - z hi - z hi - z vrefh/2 0 1111 on/on/on/on hold off vrefh/2 vrefh/2 vrefh/2 vrefh/2 table 29 . power o ff and reset f unction (1) power off function 1 (pw 1 - 4 bits) all dac1 - 4 can be power ed down immediately by setting pw1 - 4 bits to 0 000 . in this time, all circuits except registers are powered down and the analog output goes to floating state (hi - z). figure 59 shows a timing example of power - on and power - down. notes: ( 1) the a nalog output corresponding to digital input ha s group delay (gd). (2) analog outputs are floating (hi - z) in power down mode. (3) small pop noise occurs at the edges( ? ? ) of the internal timing of pw1 - 4 bit s . this noise is output even if 0 data is input. ( 4 ) mute the analog output externally if click noise (3) adversely affect system performance . ( 5 ) the dzf pin outputs l , in power down mode (pw1 - 4 bits = 0000 ). figure 59 . power - off/on sequence example 1 normal operation internal state p w 1 - 4 bit power - off normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (1) (3) ( 5 ) dzf external mute ( 4 ) (3) (1) mute on (2) don t care
[ ak 4458 ] 014011794 - e - 00 2015/01 - 60 - ( 2 ) reset function (rstn bit) the dac can be re set by setting rstn bit to 0 but the internal registers are not initialized . in this time, the corresponding analog outputs go to vrefh/2 and the dzf pin outputs h if clocks (mclk, bick and lrck) are input . figure 60 shows an example of reset sequence by rstn bit. notes: ( 1) the a nalog output corresponding to digital input ha s group delay (gd). (2 ) analog outputs are floating (hi - z) in power down mode. (3) small pop noise occurs at the edges( ? ? ) of the internal timing of rstn bit . this noise is output even if 0 data is input. (4) the dzf pin goes to h on the falling edge of rstn bit and goe s to l in 2/fs after a rising edge of the internal rstn. (5) there is a delay, 3 ~ 4/fs from rstn bit 0 to the internal rstn bit 0 , and 2 ~ 3/fs from rstn bit 1 to the internal rstn bit 1 . figure 60 . reset sequence exampl e 1 note: when using both reset (rstn bit = 0 ) and dac power - off bits (pw1 - 4 bits), power - off bits should be set to 0 before rstn bit. internal state rstn bit digital block power - down normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in bick (1) (3) dzf (3) (1) (2) normal operation 2/fs( 4 ) internal rstn bit 2~3/fs ( 5 ) 3~4/fs (6) don t care
[ ak 4458 ] 014011794 - e - 00 2015/01 - 61 - (3) reset function ( mclk stop) when the mclk stops for more than 10us during operation (pdn pin = h ) , the ak4 458 is placed in reset state and the analo g output goes to floating state (hi - z) . when the mclk is restarted, reset state is released and the ak 4458 returns to normal operation mode. zero detection function is disabled while the mclk is stopped. figure 61 shows a reset sequence by stopping the mclk. notes: (1) after the ak4458 is powered - up , the pdn pin should be l for 150ns . (2) the analog output corresponding to digital input has group delay (g d). (3) the digital data input can be stopped. click noise after mclk is input again can be reduced by inputting 0 data during this period . (4) click noise occurs within 3 ~ 4lrck from the riding edge ( ) of the pdn pin or mclk inputs. this noise is output even if 0 data is input. (5) mute the analog output externally if click noise ( 4 ) adversely affect system performance . figure 61 . reset s equence e xample 2 normal operation internal state digital circuit power - down normal operation gd gd d/a out (analog) d/a in (digital) clock in mclk (2) (3) external mute ( 5 ) (2) mclk stop rst n bit power - down power - down (4) (4) (4) hi - z ( 5 ) (1) pdn pin ( 5 )
[ ak 4458 ] 014011794 - e - 00 2015/01 - 62 - s ynchroniz atio n function (pcm mode) synchronization functi on (analog output phase synchronization) this function synchronizes analog output phase by suppressing the phase difference of the ak4458 and other akm devices with synchronization function to within 3/256fs . analog output phase synchronization function becomes valid when input data at all channels are continuo usly 0 for 8192 times if synce bit is set to 1 during operation in pcm mode or when rstn bit is set to 0 . example) in the case of using the ak4 458 with the ak4452 ( figure 62 ) the ak4452 and the ak4458 have synchronization function. the output phase difference between the ak4452 s output (aout1lp/n_2, aout1rp/n_2) and the ak4458 s output (aout1 - 4lp/n_8, a out1 - 4rp/n_8) will be within 3/256fs. figure 62 . system example of clock synchronization function ak445 2 ak4458 dsp mclk aout1lp/n mclk lrck aout1rp/n lrck mclk lrck aout1lp/n aout1rp/n aout4lp/n aout4rp/n aout1lp/n _ 2 aout1rp/n _2 aout1lp/n _ 8 aout1rp/n _8 aout4lp/n _ 8 aout4rp/n _8
[ ak 4458 ] 014011794 - e - 00 2015/01 - 63 - p arallel m ode parallel mode is available by setting the i2c pin = h , and the ps pin = h . audio interface format of the parallel mode is controlled by tdm1 - 0 bits and dif bit ( table 30 ). daisy chain mode is also available by setting the dchain pin = h ( table 15 ). in parallel mode, the audio interface format is always in auto setting mode and reset is released . zero detection function and functions set by registers are not available in parallel mode. tdm 1 pin tdm0 pin dif pin mode 0 0 0 mode 6 ( table 13 ) 0 0 1 mode 7 ( table 13 ) 0 1 0 mode 12 ( table 13 ) 0 1 1 mode 13 ( table 13 ) 1 0 0 mode1 8 ( table 13 ) 1 0 1 mode1 9 ( table 13 ) 1 1 0 mode 24 ( table 13 ) 1 1 1 mode 25 ( table 13 ) table 30 . parallel m ode serial control interface the ak44 58 s functions are controlled through registers. the registers may be written by two types of control modes. the internal registers are controlled in 3 - wire serial control mode wh en the i2c pin = l , and in i 2 c bus control mode when the i2c pin = h and the ps pin = l .
[ ak 4458 ] 014011794 - e - 00 2015/01 - 64 - (1) 3 - wire serial control mode ( i2c pin = l ) the internal registers may be written through the 3 - wire p interface pins ( csn , cclk and cdti). the data on t his interface consists of a 2 - bit chip address, read/write (1bit, fixed to 1, write only), register address (msb first, 5bits) and control data (msb first, 8bits). a ddress and data are clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after a low - to - high transition of csn . the clock speed of cclk is 5mhz (max). the internal registers are initialized by setting the pdn pin = l . in serial mode, an internal timing circuit is reset by setting rstn bit = 0 but register values are not initialized. c1 - c0: chip address (c1= cad 0 pin , c0= cad 0 pin ) r/w: read/write (fixed to 1, write only) a4 - a0: register address d7 - d0: control data figure 63 . 3 - wire serial control i/f timing * the ak44 58 does not support read commands in 3wire serial control mode. * when the ak44 58 is in power down mode (pdn pin = l) or the mclk is not provided, a writing into the control register s is prohibite d. * the control data can not be written when the cclk rising edge is 15 times or less or 17 times or more during csn is l. cdti cclk csn c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3
[ ak 4458 ] 014011794 - e - 00 2015/01 - 65 - (2) i 2 c - bus control mode ,&slq 3+ the ak44 58 supports the fast - mode i 2 c - bus (max: 400khz, ver1.0) . 1. write operations figure 64 shows the data transfer sequence of the i 2 c - bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 70 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as 37kh next bit s are cad 1 - 0 (device address bit s ). this bit s identifie s the specific device on the bus. the hard - wired input pin s (cad 1 - 0 pin s ) set these device address bit ( figure 65 ). if the slave address matches that of the ak4458 , the ak4458 generates an acknowledge and the operation is executed. the master must generate the acknowledge - related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 71 5:elw 3lqglfdwhvwkdwwkhuhdgrshudwlrqlvwrehh[hfxwhg3lqglfdwhvwkdwwkhzulwh operation is to be executed. the second byte consists of the control register address of the ak4458 . the format is msb first, and those most significant 3 - bits are fixed to zeros ( figure 66 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 67 ). the ak4458 generates an acknowledge af ter each byte is received. data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 70 ). the ak4458 can perform more than one byte write operation per sequence. after receipt of the third byte the ak4458 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data b yte is transferred. after receiving each data packet the internal 6 - bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceed s 3 14 h pr i or to generating a stop condition, the address co xqwhuzloo3urooryhu to 3 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 72 ) except for the start and stop conditions. figure 64 . data transfer sequence at the i 2 c - bus mode 0 0 1 0 0 cad1 cad0 r/w (th ese cad 1 - 0 should match w ith cad 1 - 0 pin s ) figure 65 . the first byte 0 0 0 a4 a3 a2 a1 a0 figure 66 . the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 67 . byte structure a fter t he s econd b yte sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p
[ ak 4458 ] 014011794 - e - 00 2015/01 - 66 - 2. read opera tions set the r/w bit = 1 for the read operation of the ak4458 . after transmission of data, the master can read the next addresss data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after re ceiving each data packet the internal 6 - bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 0eh prior to generating stop condition, the address counter will roll over to 00h and the data of 14 h wi ll be read out. the ak4458 supports two basic read operations: c urrent a ddress r ead and r andom a ddress read . 2 - 1. c urrent address read the ak4458 contains an internal address counter that maintains the address of the last word ac cessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit 1, the ak4458 generates an ac knowledge, transmits 1 - byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4458 ceases transmission. figure 68 . c urrent address read 2 - 2. r andom address read the random read operation allows the master to access any memory location at random. prior to issuing a slave address with the r/w bit =1, t he master must execute a dummy write operation first. the master issues a start request, a slave address (r/w bit = 0) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit =1. the ak4458 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4458 ceases transmission. figure 69 . r andom address read sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r
[ ak 4458 ] 014011794 - e - 00 2015/01 - 67 - figure 70 . start and stop conditions figure 71 . acknowledge on the i 2 c - bus figure 72 . bit transfer on the i 2 c - bus scl sda stop condition start condition s p scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 scl sda data line stable; data valid change of data allowed
[ ak 4458 ] 014011794 - e - 00 2015/01 - 68 - function list available functions are different in pcm mode and in dsd mode. function default address bit pcm dsd attenuation level 0db 03 - 04h 0f - 14h att7 - 0 y y audio data interface modes 32 - bit msb justified 00h dif2 - 0 y - data zero detect enable d isable 07 - 08h l1 - 4/r1 - 4 y y minimum delay filter enable sharp roll - off filter 01 - 02h sd slow y - slow roll - off filter enable y - short delay filter enable y - de - emphasis response off 01h,0ah 0eh dem3 - 0 y - soft mute enable normal operation 01h smute y y dsd/pcm mode select pcm mode 02h d/p y y master clock frequency select at dsd mode 512fs 02h dcks - y mono mode stereo mode select stereo 02h,0dh mono y y inverting enable of dzf
[ ak 4458 ] 014011794 - e - 00 2015/01 - 69 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 0 dif2 dif1 dif0 rstn 01h control 2 0 0 sd dfs1 dfs0 dem11 dem10 smute 02h control 3 dp 0 dcks dckb mono1 dzfb sellr1 slow 03h l1ch att att7 att6 att5 att4 att3 att2 att1 att0 04h r1ch att att7 att6 att5 att4 att3 att2 att1 att0 05h control 4 invl1 invr1 invl2 invr2 sellr2 0 dfs2 sslow 0 6 h dsd1 ddm dml1 dmr1 dmc dmre 0 dsdd dsdsel0 07h control 6 l 3 r 3 l 4 r 4 0 0 1 synce 08h sound control l1 r1 l2 r2 0 0 sc1 sc0 09h ds d2 dml2 dmr2 dml3 dmr3 dml4 dmr4 dsdf dsdsel1 0ah control 7 tdm1 tdm0 sds1 sds2 pw2 pw1 dem 21 dem 20 0bh control 8 ats1 ats0 0 sds0 pw4 pw3 dchain 0 0ch control 9 invr4 invl4 invr3 invl3 0 fir2 fir1 fir0 0dh control 10 mono4 mono3 mono2 0 sellr4 sellr3 0 0 0eh control 11 dem41 dem40 dem31 dem30 0 0 0 0 0fh l2ch att att7 att6 att5 att4 att3 att2 att1 att0 10h r2ch att att7 att6 att5 att4 att3 att2 att1 att0 11h l3ch att att7 att6 att5 att4 att3 att2 att1 att0 12h r3ch att att7 att6 att5 att4 att3 att 2 att1 att0 13h l4ch att att7 att6 att5 att4 att3 att2 att1 att0 14h r4ch att att7 att6 att5 att4 att3 att2 att1 att0 note 36 . data must not be written into addresses from 15 h to 1fh. note 37 . when the pdn p in is set to l, all registers are initialized to their default values. note 38 . when rstn bit is set to 0, only the internal timing circuit is reset but register values are not initialized .
[ ak 4458 ] 014011794 - e - 00 2015/01 - 70 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 0 dif2 dif1 dif0 rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 1 1 0 0 rstn: internal timing reset 0: reset. all registers are not initialized. (default) 1: normal operation inter nal clock timings are reset but registers are not reset. dif2 - 0: audio data interface modes ( table 13 ) default value is 110 (mode 6 : 32 - bit msb justified). be careful because format varies in tdm1 and tdm0. ack s: master clock frequency auto setting mode enable (pcm only) 0: disable : manual setting mode (default) 1: enable : auto setting mode when acks bit = 1 , the sampling frequency and mclk frequency are detected automatically. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 sd dfs1 dfs0 dem 1 1 dem 1 0 smute r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 1 0 smute: soft mute enable. 0: normal operation (default) 1: dac outputs soft - muted. de m 1 1 - 0: dac1 de - emphasis response ( table 17 ) default value is 01 (off) . dfs2 - 0: sampling speed control ( table 2 ) default value is 0 0 0 (normal spee d) . a c lick noise occurs when switching dfs 2 - 0 bit s setting . dfs2 is address 05h sd: short delay filter enable . ( table 12 ) 0: sharp roll - off filter 1: short delay filter (default)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 71 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 dp 0 dcks d ckb mono 1 dzfb sellr 1 slow r/w r/w r /w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 slow: slow roll - off filter enable. ( table 12 ) 0: sharp roll - off filter (default) 1: slow roll - off filter sellr1: t he data selection of da c1 l channel and r channel, when mono mode ( table 22 ) default value is 0 . dzfb: inverting enable of dz f ( table 21 ) 0: dzf pin goes h at zero detection (default) 1: dzf pin goes l at zero detection mon o1: dac1 enters monaural output mode when mono bit = 1 . ( table 22 ) 0: stereo mode (default) 1: mono mode dckb : polarity of dclk (dsd onl y) 0: dsd data is output from dclk falling edge. (default) 1: dsd data is output from dclk rising edge. dcks : master clock frequency select at dsd mode (dsd only) 0: 512fs (default) 1: 768fs dp: dsd/pcm mode select 0: pcm mode (default) 1 : dsd m ode the ak4458 must be reset by rstn bit when changing d p bit setting. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h l1ch att att7 att6 att5 att4 att3 att2 att1 att0 04h r1ch att att7 att6 att5 att4 att3 att2 att1 att0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 1 1 1 1 1 1 1 1 att7 - 0: attenuation level ( table 18 ) default value is ff ( 0db)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h control 4 invl1 invr1 invl2 invr2 sellr2 0 dfs2 sslow r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 sslow : digital filter bypass mode enable ( table 16 ) 0: roll - off filter (default) 1: super slow roll - off mode dfs2 - 0: sampling speed control ( table 2 ) default value is 0 0 0 (normal spe ed) . a click noise occurs when switching dfs 2 - 0 bit s setting. dfs1, dfs0 is address 01 h sellr2: data s election of dac2 l channel and r channel, when mono mode ( table 23 ) default value is 0 . invl1: aoutl1 output phase inverting bit invr1: aoutr1 output phase inverting bit invl2: aoutl2 output phase inverting bit invr2: aoutr2 output phase inverting bit 0: normal (default) 1: inverted
[ ak 4458 ] 014011794 - e - 00 2015/01 - 73 - ad dr register name d7 d6 d5 d4 d3 d2 d1 d0 0 6 h dsd1 ddm dml 1 dmr 1 dmc dmre 0 dsdd dsdsel0 r/w r/w r r r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 dsdsel 1 - 0 : dsd sampling speed control ( table 10 ) default value is 0 0 . dsdd : dsd play back path control ( table 11 ) 0: f u ll function (default) 1: volume bypass dmre : dsd mute release 0: hold (default) 1: m ute r elease this register is only valid when ddm bit = 1 and dmc bit = 1 . it releases a mute state when dsd data is muted by ddm and dmc bits. dmc : dsd mute control 0: auto r eturn (default) 1: mute h old this register is only valid when ddm bit = 1 . i t selects the process when dsd data level drops under full scale whil e dsd data is muted by ddm bit. dmr 1 /dml 1 this register output detection flag when the signal level of the dsdr1/l1 pin is full scale. ddm : dsd d ata m ute 0: disable (default) 1: enable the ak4458 has a function that mutes the output when dsd data is all 1 or 0 for 2048 samplings (1/fs). this register controls the dsd mute function.
[ ak 4458 ] 014011794 - e - 00 2015/01 - 74 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h control 6 l 3 r 3 l 4 r 4 0 0 1 synce r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 1 1 synce : sync mode ena ble 0: sync mode disable 1: sync mode enable (default) l3 - 4, r3 - 4: zero detect flag enable bit for the dzf pin 0: disable(default) 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h sound control l1 r1 l2 r2 0 0 sc1 sc0 r/w r/w r/w r/w r/w r/w r /w r/w r/w d efault 0 0 0 0 0 0 0 0 sc 1 - 0: sound c ontrol ( table 26 ) default value is 0 0 . l3 - 4, r3 - 4: zero detect flag enable bit for the dzf pin 0: disable (default) 1: enable
[ ak 4458 ] 014011794 - e - 00 2015/01 - 75 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h dsd2 dml2 dmr2 dml3 dmr3 dml4 dmr4 dsdf dsdsel1 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 dsdsel 1 - 0 : dsd sampling speed c ontrol ( table 10 ) default value is 0 0 . dsdf: dsd f ilter s elect ( table 12 ) default value is 0 . dmr 2 - 4/dm l 2 - 4 these registers output detection flag when signal level s of the dsdr2 - 4/l2 - 4 pins are full scale. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah contr ol 7 tdm1 tdm0 sds1 sds2 pw2 pw1 dem 21 dem 2 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 1 1 0 1 de m 2 1 - 0: dac 2 de - emphasis response ( table 17 ) default value is 01 . (off) pw2 - 1: power down control for dac pw2 : power management for dac 2 0: dac 2 power off 1: dac 2 power on (default) pw1 : power management for dac 1 0: dac 1 power off 1: dac 1 power on (default) sds2 - 0 : dac1 - 4 data select 0: normal operation 1: output other slot data ( table 14 ) default value is 0 00 . tdm0 - 1: tdm mode select default value is 00 .
[ ak 4458 ] 014011794 - e - 00 2015/01 - 76 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh control 8 ats1 ats0 0 sds0 pw4 pw3 dchain 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 1 1 0 0 dchain : daisy chain mode enable 0: daisy chain mode disable (default) 1: daisy chain mode enable pw4 - 3 : power down control for dac pw4 : power management for dac 4 0: dac 4 power off 1: dac 4 power on (default) pw3 : power management for dac 3 0: dac 3 power off 1: dac 3 power on (default) sds2 - 0 : dac1 - 4 data select 0: normal operation 1: output other slot data ( table 14 ) ats1 - 0: dac digital attenuator transition time setting ( table 19 ) default value is 00 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch control 9 invr4 invl4 invr3 invl3 0 fir2 fir1 fir0 r/w r/w r/w r/w r/w r/ w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 fir2 - 0: fir f ilter c ontrol ( table 20 ) default value is 000 . invl3: aoutl3 output phase inverting bit invr3: aoutr3 output phase inverting bit invl4: aoutl4 output phase inverting bit invr4: aoutr4 output phase inverting bit 0: normal (default) 1: inverted
[ ak 4458 ] 014011794 - e - 00 2015/01 - 77 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh control 10 mono4 mono3 mono2 0 sellr4 sellr3 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 sellr3: the data selection of dac3 l channel and r channel, when mono mode ( table 24 ) default value is 0 . sellr4: the data selection of dac4 l channel and r channel, when mono mode ( table 25 ) default value is 0 . mono2: dac2 enters mono output mode when mono 2 bit = 1 . ( table 23 ) mono3: dac3 enters mono output mode when mono 3 bit = 1 . ( table 24 ) mono4: dac4 enter s mono output mode when mono 4 bit = 1 . ( table 25 ) 0: stereo mode (default) 1: mono mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh control 11 dem41 dem40 dem31 dem30 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d e fault 0 1 0 1 0 0 0 0 de m 3 1 - 0: dac 3 de - emphasis response ( table 17 ) de m 4 1 - 0: dac 4 de - emphasis response ( table 17 ) default value is 01 . (off) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh l2ch att att7 att6 att5 att4 att3 att2 att1 att0 10h r2ch att att7 att6 att5 att4 att3 att2 att1 att0 11h l3ch att att7 att6 att5 att4 att3 att2 att1 att0 12h r3ch att att7 att6 att5 att4 att3 att2 att1 att0 13h l4ch att att7 at t6 att5 att4 att3 att2 att1 att0 14h r4ch att att7 att6 att5 att4 att3 att2 att1 att0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 1 1 1 1 1 1 1 1 att7 - 0: attenuation level ( table 18 ) initial value is ff ( 0d b)
[ ak 4458 ] 014011794 - e - 00 2015/01 - 78 - 10. recommended external circuits typical connection diagram figure 73 shows system connection diagram, and figure 74 shows the analog output circuit example. notes: - chip address = 00 . bick = 64fs, lrck = fs - power lines of avdd and vrefh1 - 4 should be distributed separately from ldo and etc. while keeping low impedan ce . if it is not possible, it is recommended to connect a lpf composed b y a 10 resistor and a 220uf capacitor between vrefl1 - 4 and vrefh1 - 4. - dvss and avss must be connected to the same potential . - all digital input pins should not be allowed to float. figure 73 . typical connection diagram (avdd=5v, tvd d=3.3v) a nalog 5.0v ceramic capacitor + electrolytic capacitor l3 ch lpf l3 ch mute l3 ch out analog ground digital ground digital 3 . 3 v + 0.1u 10u dsp micro - controller 0.1u 0.1u r 2ch lpf r 2ch mute r 2ch out l 4 ch lpf l 4 ch mute l 4 ch out r 1 ch lpf r 1 ch mute r 1 ch out mclk vdd18 1 bick 4 7 2 lrck 3 sdti1 4 sdti2 5 sdti3 6 sdti4 7 dsdr3 8 dsdl4 9 dsdr4 10 dzf 11 sda 1 3 3 5 vrefl3 ak44 58vn 1 4 1 5 1 6 1 7 1 8 1 9 20 2 1 2 2 2 3 scl cad0_i 2 c ps i2c aout1lp aout1ln vref l 1 v refh 1 aoutr 1 n aoutr1p 3 4 vref h3 3 3 aoutl3n 3 2 aout l3 p 31 avdd 30 avss 2 9 aout r 2 p n 2 8 aout r 2 n 2 7 vref h 2 2 6 vref l 2 2 5 aoutl2n dvss 4 6 tvdd 4 5 ldoe 4 4 aoutr4p 4 3 aoutr4n 42 vrefl4 41 vrefh4 40 aoutl 4n 3 9 aoutl 4p 3 8 aoutr3p 3 7 cad1 1 2 24 aout l 2p 36 aoutr3n pdn 48 1u + + 10u 0.1u l2ch lpf l2ch mute l2ch out l1ch lpf l1ch mute l1ch out r3ch lpf r3ch mute r3ch out r4 ch lpf r4 ch mute r4 ch out 0.1u 0.1u analog 5.0v
[ ak 4458 ] 014011794 - e - 00 2015/01 - 79 - 1. grounding and power supply decoupling to minimize coupl ing by digital noise, decoupling capacitors should be connected to avd d and tvdd respectively. avdd are supplied from the analog supply of the system and tvdd is supplied from the digita l supply of the system. dv ss and avss must be connected to the same potential . decoupling capacitors especially small ceramic capacitors for high frequency should be placed as near as possible to the supply pin. 2. voltage reference the potential differ en ce betw een the vrefh 1 / 2 /3/4 pin and the vrefl 1 / 2 /3/4 pin sets the analog output range. the vrefh 1/2 /3/4 pin is normally connected to avdd, and the vrefl 1/2 /3/4 pin is normally connected to avss . vrefh 1/2 /3/4 and vrefl 1/2 /3/4 should be connected with a 0. 1f ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency noise. all signals, especially clocks, should be kept away from the vrefh 1/2 /3/4 and vrefl 1/2 /3/4 pins in order to avoid unwanted noise coupling into the ak 4458 .
[ ak 4458 ] 014011794 - e - 00 2015/01 - 80 - 3. analog outputs the analog outputs are full differential outputs and 2.8 vpp (typ , vref h1/2 /3/4 ? vrefl1/2 /3/4 = 5v) centered around vrefh 2 . the differential outputs are summed externally, v aout = (aout+) ? (aout ? ) between aout+ and aout ? . if the sum ming gain is 1, the output range is 5.6 vpp (typ , vref h1/2 /3/4 ? vrefl1/2 /3/4 = 5v). the bias voltage of the external summing cir cuit is supplied externally. pcm input data format is 2's complement. the output voltage (v aout ) is a positive full scale for 7f ffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal v aout is 0v for 000000h(@24bit). the output level is determined by the 1 - bit signal duty ratio in dsd input mode. the output level is positive full scale when the duty is 100% (all 1 ) and the output level is negative full scale when the duty is 0% (all 0 ). in ideal case , a 0v voltage is output when the input signal duty is 50%. the internal switched - capacitor filter s attenuate the noise generated by the delta -sigma modulator beyond the audio pass band. figure 74 show s an example of differential outputs and lpf circuit example by a single op - amp . figure 74 external lpf circuit ex ample 1 for pcm (fc = 99.0khz, q=0.680) r1 3.3k 3.9k 3.9k 4.3k 4.7k 5.6k r2 3.3k 4.7k 5.6k 6.8k 8.2k 12.0k gain(db) 0 1.620665 3.142468 3.980809 4.83432 6.619864 dc load (max) 3.8k 4.0k 3.5k 3.6k 3.6k 3.8k table 32 . external l pf circuit example 1 for pcm frequency response gain 20khz ? ? ? 3.9 k 4.7 k 150 3 . 9 k 150 4 . 7 k 470 p +vop 470 p - vop aout - aout+ 3. 9 n analog out ak4 4 58 njm2043
[ ak 4458 ] 014011794 - e - 00 2015/01 - 81 - 11. package outline dimensions material & lea d finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ ak 4458 ] 014011794 - e - 00 2015/01 - 82 - marking 1) pin #1 indication 2) akm logo 3) date code: xxxxxxx( 7 digits) 4) produ ct code: ak4458 vn 12. revision history date (y/m/d) revision reason page contents 1 5 / 0 1/ 23 00 first edition ak4 458vn xxxxxxx akm 1
[ ak 4458 ] 014011794 - e - 00 2015/01 - 83 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information conta ined in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all inf ormation included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this doc ument nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your produc t design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or sy stems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment use d in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality a nd reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product coul d cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, includi ng without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any informatio n contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may no t be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such a s the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liabilit y for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warra nty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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