cystech electronics corp. spec. no. : c307s6r issued date : 2016.03.30 revised date : page no. : 1/7 HBA1514S6R cystek product specification general purpose pnp epitaxial planar transistors (dual transistors) HBA1514S6R features ? two bta1514 chips in a sot-363 package. ? mounting possible with sot-323 automatic mounting machines. ? transistor elements are independent, eliminating interference. ? mounting cost and area can be cut in half. ? complementary to hbc3906s6r. ? pb-free lead plating and halogen-free package. symbol outline HBA1514S6R sot-363r ordering information device package shipping HBA1514S6R-0-t1-g sot-363 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pcs / tape & reel, 7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c307s6r issued date : 2016.03.30 revised date : page no. : 2/7 HBA1514S6R cystek product specification the following characteristics apply to both tr1 and tr2 absolute maximum ratings (ta=25 c) parameter symbol limits unit collector-base voltage v cbo -180 v collector-emitter voltage v ceo -160 v emitter-base voltage v ebo -5 v collector current i c -0.6 a total power dissipation p d 200 (note ) mw thermal resistance, junction to ambient r ja 625 c/w operating junction and storage temperature range tj ; tstg -55~+150 c note : 150mw per element must not be exceeded characteristics (ta=25 c) symbol min. typ. max. unit test conditions bv cbo -180 - - v i c =-50 a bv ceo -160 - - v i c =-1ma bv ebo -5 - - v i e =-50 a i cbo - - -50 na v cb =-120v i ebo - - -50 na v eb =-4v *v ce(sat) 1 - 0.11 -0.16 v i c =-10ma, i b =-1ma *v ce(sat) 2 - 0.25 -0.3 v i c =-50ma, i b =-5ma *v be(sat) 1 - - -1 v i c =-10ma, i b =-1ma *v be(sat) 2 - - -1 v i c =-50ma, i b =-5ma h fe 1 100 - - - v ce =-5v, i c =-1ma h fe 2 100 - - - v ce =-5v, i c =-10ma h fe 3 50 - - - v ce =-5v, i c =-50ma h fe 4 120 - 270 - v ce =-6v, i c =-2ma f t 100 - - mhz v ce =-30v, i c =-10ma, f=100mhz cob - - 6 pf v cb =-10v, f=1mhz *pulse test: pulse width 380 s, duty cycle 2%
cystech electronics corp. spec. no. : c307s6r issued date : 2016.03.30 revised date : page no. : 3/7 HBA1514S6R cystek product specification typical characteristics current gain vs collector current 1 10 100 1000 0.1 1 10 100 1000 collector current---i c (ma) current gain--- h fe v ce =5v v ce =1v v ce =6v h fe saturation voltage vs collector current 100 1000 10000 1 10 100 1000 collector current---i c (ma) saturation voltage---(mv) v ce(sat) @i c =10i b saturation voltage vs collector current 100 1000 1 10 100 1000 collector current---i c (ma) saturation voltage---(mv) v be(sat) @i c =10i b cutoff frequency vs collector current 10 100 1000 0.1 1 10 100 collector current---i c (ma) cutoff frequency---f t (mhz) f t @v ce =10v capacitance characteristics 1 10 100 0.1 1 10 100 reverse biased voltage---v cb, v eb (v) capacitance---(pf) cib cob f t =1mhz power derating curves 0 50 100 150 200 250 0 50 100 150 200 ambient temperature --- ta( ) power dissipation---pd(mw) dual single
cystech electronics corp. spec. no. : c307s6r issued date : 2016.03.30 revised date : page no. : 4/7 HBA1514S6R cystek product specification recommended soldering footprint
cystech electronics corp. spec. no. : c307s6r issued date : 2016.03.30 revised date : page no. : 5/7 HBA1514S6R cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c307s6r issued date : 2016.03.30 revised date : page no. : 6/7 HBA1514S6R cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c307s6r issued date : 2016.03.30 revised date : page no. : 7/7 HBA1514S6R cystek product specification sot-363 dimension marking: millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 0.900 1.100 0.035 0.043 e1 2.150 2.450 0.085 0.096 a1 0.000 0.100 0.000 0.004 e 0.650 typ 0.026 typ a2 0.900 1.000 0.035 0.039 e1 1.200 1.400 0.047 0.055 b 0.150 0.350 0.006 0.014 l 0.525 ref 0.021 ref c 0.080 0.150 0.003 0.006 l1 0.260 0.460 0.010 0.018 d 2.000 2.200 0.079 0.087 0 8 0 8 e 1.150 1.350 0.045 0.053 notes : 1 .controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material : x lead : pure tin plated. x mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: x all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. x cystek reserves the right to make changes to its products without notice. x cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. x cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . 6-lead sot-363 plastic surface mounted package cystek package code: s6r style: pin 1. emitter1 (e1) pin 2. base1 (b1) pin 3. collector2 (c2) pin 4. emitter2 (e2) pin 5. base2 (b2) pin 6. collector1 (c1) device code date code: year + month year : 6 2006, 7 2007,?, etc month : 1 jan 2 feb, ?, 9 sep, a oct, b nov, c dec 2l xx
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