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this is information on a product in full production. july 2013 docid17450 rev 4 1/17 17 STL12N65M5 n-channel 650 v, 0.475 typ., 8.5 a mdmesh? v power mosfet in a powerflat? 5x6 hv package datasheet ? production data figure 1. internal schematic diagram features ? outstanding r ds(on) *area ? extremely large avalanche performance ? gate charge minimized ? very low intrinsic capacitance ? 100% avalanche tested applications ? switching applications description this device is an n-channel mdmesh? v power mosfet based on an innovative proprietary vertical process technology, which is combined with stmicroelectronics? well-known powermesh? horizontal layout structure. the resulting product has extremely low on- resistance, which is unmatched among silicon- based power mosfets, making it especially suitable for applications which require superior power density and outstanding efficiency. $0y ' * 6 powerflat 5x6 hv 1 2 3 4 tm order code v dss r ds(on) max i d STL12N65M5 710 v 0.530 8.5 a table 1. device summary order code marking package packaging STL12N65M5 12n65m5 powerflat ? hv tape and reel www.st.com
contents STL12N65M5 2/17 docid17450 rev 4 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
docid17450 rev 4 3/17 STL12N65M5 electrical ratings 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 650 v v gs gate-source voltage 25 v i d (1) 1. limited by maximum junction temperature drain current (continuous) at t c = 25 c 8.5 a i d (1) drain current (continuous) at t c = 100 c 4 a i dm (1),(2) 2. pulse width limited by safe operating area. drain current (pulsed) 34 a p tot (1) total dissipation at t c = 25 c 48 w i ar avalanche current, repetitive or not- repetitive (pulse width limited by t j max) 1.9 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 130 mj dv/dt (3) 3. i sd 8.5 a, di/dt 400 a/ s, v peak v (br)dss , v dd = 400 v. peak diode recovery voltage slope 15 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 2.6 c/w r thj-pcb (1) 1. when mounted on 1inch2 fr-4 board, 2 oz cu. thermal resistance junction-pcb max 59 c/w
electrical characteristics STL12N65M5 4/17 docid17450 rev 4 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 1 ma 650 v i dss zero gate voltage drain current (v gs = 0) v ds = 650 v 1 a v ds = 650 v, t c =125 c 100 a i gss gate-body leakage current (v ds = 0) v gs = 25 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 345v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 4.25 a 0.475 0.530 table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 -644-pf c oss output capacitance - 18 - pf c rss reverse transfer capacitance -2.5-pf c o(tr) (1) 1. c oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss equivalent capacitance time related v ds = 0 to 520 v, v gs = 0 -55-pf c o(er) (2) 2. c oss eq. energy related is defined as a constant equival ent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss equivalent capacitance energy related -17-pf r g intrinsic gate resistance f = 1 mhz open drain - 5 - q g total gate charge v dd = 520 v, i d = 4.5 a, v gs = 10 v (see figure 16 ) -17-nc q gs gate-source charge - 4.6 - nc q gd gate-drain charge - 8.5 - nc
docid17450 rev 4 5/17 STL12N65M5 electrical characteristics table 7. source drain diode table 6. switching times symbol parameter test conditions min. typ. max unit t d (v) voltage delay time v dd = 400 v, i d = 6 a, r g = 4.7 , v gs = 10 v (see figure 17 ), (see figure 20 ) -23-ns t r(v) voltage rise time - 10 - ns t f(i) current fall time - 13.5 - ns t c(off) crossing time - 13 - ns symbol parameter test conditions min. typ. max. unit i sd (1) source-drain current - 8.5 a i sdm (1),(2) 1. limited by maximum junction temperature 2. pulse width limited by safe operating area source-drain current (pulsed) - 34 a v sd (3) 3. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 8.5 a, v gs = 0 - 1.5 v t rr reverse recovery time i sd = 8.5 a, di/dt = 100 a/ s v dd = 60 v (see figure 17 ) -232 ns q rr reverse recovery charge - 2 c i rrm reverse recovery current - 17.5 a t rr reverse recovery time i sd = 8.5 a, di/dt = 100 a/ s v dd = 60 v, t j = 150 c (see figure 17 ) -328 ns q rr reverse recovery charge - 2.8 c i rrm reverse recovery current - 17 a
electrical characteristics STL12N65M5 6/17 docid17450 rev 4 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. static drain-source on-resistance figure 7. gate charge vs gate-source voltage i d 10 1 0.1 0.1 1 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 10ms 10 s 0.01 tj=150c tc=25c single pulse 100 s 1ms 100 am15896v1 single pulse 0.05 0.02 0.01 =0.5 0.1 0.2 k 10 t p (s) -5 10 -4 10 -3 10 10 -2 10 -1 10 -6 10 -3 10 -2 -1 10 zthpowerflat_5x6_19 i d 6 4 2 0 0 10 v ds (v) 20 (a) 5 15 25 v gs =9, 10v 8 6v 7v 8v 10 12 14 16 am15897v1 i d 6 4 2 0 3 5 v ds (v) 7 (a) 4 6 8 v ds =25v 9 8 10 12 14 16 am15898v1 r ds(on) 0.475 0.45 0.425 0.4 0 7 i d (a) ( ) 3 0.5 0.525 2 5 8 1 46 0.55 0.575 v gs =10 v am15899v1 v gs 6 4 2 0 0 5 q g (nc) (v) 20 8 10 15 10 v dd =520v i d =4.5a 12 300 200 100 0 400 500 v ds v ds (v) am15900v1
docid17450 rev 4 7/17 STL12N65M5 electrical characteristics figure 8. capacitance variations figure 9. output capacitance stored energy figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on-resistance vs temperature figure 12. source-drain diode forward characteristics figure 13. normalized v ds vs temperature c 1000 100 10 1 0.1 1 v ds (v) (pf) 10 ciss coss crss 100 am15903v1 e oss 1 0.5 0 0 100 v ds (v) (j) 400 1.5 200 300 2 2.5 500 600 3 3.5 am15901v1 v gs(th) 1.00 0.90 0.80 0.70 -50 0 t j (c) (norm) -25 1.10 75 25 50 100 i d = 250 a v ds = v gs am05459v1 r ds(on) 1.7 1.3 0.9 0.5 -50 0 t j (c) (norm) -25 75 25 50 100 0.7 1.1 1.5 1.9 2.1 v gs = 10v i d = 4.25 a am05460v1 v sd 0 20 i sd (a) (v) 10 50 30 40 0 0.2 0.4 0.6 0.8 1.0 1.2 t j =-50c t j =150c t j =25c am05461v1 9 '6 7 - ?& qrup , ' p$ $0y
electrical characteristics STL12N65M5 8/17 docid17450 rev 4 figure 14. switching losses vs gate resistance (1) 1. eon including reverse recovery of a sic diode e 0 0 20 r g ( ) ( j) 10 30 20 40 40 i d =6a v dd =400v eon eoff 60 v gs =10v 80 100 am15902v1
docid17450 rev 4 9/17 STL12N65M5 test circuits 3 test circuits figure 15. switching times test circuit for resistive load figure 16. gate charge test circuit figure 17. test circuit for inductive load switching and diode recovery times figure 18. unclamped inductive load test circuit figure 19. unclamped inductive waveform figure 20. switching time waveform am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd am01472v1 v (br)dss v dd v dd v d i dm i d am05540v2 id vgs vds 90%vds 10%id 90%vgs on tdelay-off tfall trise tcross -over 10%vds 90%id vgs(i(t)) on -off tfall trise - )) concept waveform for inductive load turn-off
package mechanical data STL12N65M5 10/17 docid17450 rev 4 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid17450 rev 4 11/17 STL12N65M5 package mechanical data table 8. powerflat? 5x6 hv mechanical data dim. mm min. typ. max. a0.80 1.00 a1 0.02 0.05 a2 0.25 b0.30 0.50 d5.005.205.40 e5.956.156.35 d2 4.30 4.40 4.50 e2 3.10 3.20 3.30 e1.27 l0.500.550.60 k1.902.002.10
package mechanical data STL12N65M5 12/17 docid17450 rev 4 figure 21. powerflat? 5x6 hv drawing 8368143_rev_b
docid17450 rev 4 13/17 STL12N65M5 package mechanical data figure 22. powerflat? 5x6 hv recommended footprint (dimensions are in mm) 8368143_rev_b_footprint
packaging mechanical data STL12N65M5 14/17 docid17450 rev 4 5 packaging mechanical data figure 23. powerflat? 5x6 tape (a) figure 24. powerflat? 5x6 package orientation in carrier tape. a. all dimensions are in millimeters. measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centerline of sprocket hole to centerline of pocket. (i) (ii) (iii) 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 4.00.1 (ii) p 0 y y section y-y c l p1(8.000.1) do d1 e 1 (0.30 t ref.r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_tape_rev_c pin 1 identification
docid17450 rev 4 15/17 STL12N65M5 packaging mechanical data figure 25. powerflat? 5x6 reel 2.20 ?21.2 13.00 core detail 2.50 1.90 r0.60 77 128 ?a r1.10 2.50 4.00 r25.00 part no. w1 w2 18.4 (max) w3 06 ps esd logo at t e n t i o n observe precautions for handling electrostatic sensitive devices 11.9/15.4 12.4 (+2/-0) a 330 (+0/-4.0) all dimensions are in millimeters ?n 178(2.0) 8234350_reel_rev_c
revision history STL12N65M5 16/17 docid17450 rev 4 6 revision history table 9. document revision history date revision changes 30-apr-2010 1 first release 22-nov-2011 2 document status promoted from preliminary data to datasheet: ? added section 2.1: electrical characteristics (curves) ? added section 5: packaging mechanical data minor text changes 08-jul-2013 3 ? changed: package ? modified: i d (at t c =100 c), p tot value ? deleted: i d at t amb =25 c and 100 c ? modified: note 1 and 3 in table 2 , r g in table 5 , i sd in table 7 ? changed: figures in section 2.1: electrical characteristics (curves) 17-jul-2013 4 ? minor text changes ? modified: table 6: switching times ? updated: section 4: package mechanical data
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