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? 2016 microchip technology inc. ds20005543b-page 1 pl138-48 features ? four differential 2.5v/3 .3v lvpecl output pairs ? output frequency: 800 mhz ? two selectable differential input pairs ? translates any standard single-ended or differential input format to lvpecl output. it can accept the following standard input formats and more: - lvpecl, lvcmos, lvds, hcsl, sstl, lvhstl, cml ? output skew: 25 ps (typ.) ? part-to-part skew: 140 ps (typ.) ? propagation delay: 1.5 ns (typ.) ? additive jitter: <100 fs (max.) ? operating supply voltage: 2.375v ~ 3.63v ? operating temperature range from ?40 c to +85 c ? package availability: 16-pin qfn and 20-pin tssop general description the pl138-48 is a high performance low-cost 1:4 outputs differential lvpecl fanout buffer. microchip?s family of differential lvpecl buffers are designed to operate from a single power supply of 2.5v 5% or 3.3v 10%. the differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to-lot skew. designed to fit in a small form-factor package, the pl138-48 offers up to 800 mh z of output operation with very low-power consumption and lowest additive jitter of any comparable device. block diagram 2.5v to 3.3v, low-skew, 1:4 di fferential pecl fanout buffer
pl138-48 ds20005543b-page 2 ? 2016 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? supply voltage (v dd ) .............................................................................................................................. .................+4.6v input voltage, dc (v i )..........................................................................................................................?0.5 v to v dd +0.5v output voltage, dc (v o ) .....................................................................................................................?0.5v to v dd +0.5v esd protection (hbm) ........................................ ................................................................... ....................................2 kv ? notice: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and functiona l operation of the device at those or an y other conditions above those indicated in the operational sections of this s pecification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics specifications: v cc = 3.3v; v ee = 0v. input and output parameters vary 1:1 with v cc when v cc varies 10%. parameters symbol min. typ. max. units conditions output high voltage, ( note 1 )v oh 2.215 2.320 2.420 v at ?40c 2.275 2.350 2.420 at +25c 2.275 2.350 2.420 at +85c output voltage low, ( note 1 )v ol 1.470 1.610 1.745 v at ?40c 1.490 1.585 1.680 at +25c 1.490 1.585 1.680 at +85c input high voltage v ih 2.075 ? 2.420 v at ?40c 2.135 ? 2.420 at +25c 2.135 ? 2.420 at +85c input low voltage v il 1.470 ? 1.890 v at ?40c 1.490 ? 1.825 at +25c 1.490 ? 1.825 at +85c output voltage reference, ( note 2 ) v bb 1.86 ? 1.98 v at ?40c 1.92 ? 2.04 at +25c 1.92 ? 2.04 at +85c input high voltage common mode range, ( note 3 , note 4 ) v cmr 1.2 ? 3.3 v at ?40c 1.2 ? 3.3 at +25c 1.2 ? 3.3 at +85c input high current, ( note 5 )i ih ??75 a at ?40c ??75 at +25c ??75 at +85c input low current, ( note 5 )i il ?75 ? ? a at ?40c ?75 ? ? at +25c ?75 ? ? at +85c note 1: outputs terminated with 50 ? to v cco ?2v. 2: single-ended input operation is limited to vcc 3v in lvpecl mode. 3: common mode voltage is defined as v ih . 4: for single-ended applications, the maximum input voltage for clk-inx, clk-inxb is v cc +0.3v. 5: clk-in0, clk-in1; clk-in0b, clk-in1b.
? 2016 microchip technology inc. ds20005543b-page 3 pl138-48 dc electrical characteristics specifications: v cc = 2.5v; v ee = 0v. input and output parameters vary 1:1 with v cc when v cc varies 5%. parameters symbol min. ty p. max. units conditions output high voltage, ( note 1 )v oh 1.415 1.520 1.620 v at ?40c 1.475 1.550 1.620 at +25c 1.475 1.550 1.620 at +85c output voltage low, ( note 1 )v ol 0.670 0.810 0.945 v at ?40c 0.690 0.785 0.880 at +25c 0.690 0.785 0.880 at +85c input high voltage v ih 1.275 ? 1.620 v at ?40c 1.335 ? 1.620 at +25c 1.335 ? 1.620 at +85c input low voltage v il 0.670 ? 1.090 v at ?40c 0.690 ? 1.025 at +25c 0.690 ? 1.025 at +85c input high voltage common mode range, ( note 2 , note 3 ) v cmr 1.2 ? 2.5 v at ?40c 1.2 ? 2.5 at +25c 1.2 ? 2.5 at +85c input high current, ( note 4 )i ih ??60 a at ?40c ? ? 60 at +25c ? ? 60 at +85c input low current, ( note 4 )i il ?60 ? ? a at ?40c ?60 ? ? at +25c ?60 ? ? at +85c note 1: outputs terminated with 50 ? to v cco ?2v. 2: common mode voltage is defined as v ih . 3: for single-ended applications, the maximum input voltage for clk-inx, clk-inxb is v cc +0.3v. 4: clk-in0, clk-in1; clk-in0b, clk-in1b.
pl138-48 ds20005543b-page 4 ? 2016 microchip technology inc. ac electrical characteristics v cc = ?3.8v to ?2.375 or v cc = 2.375v to 3.8v; v ee = 0v; t a = ?40c to +85c. all parameters are measured at f 800 mhz unless otherwise noted. parameters symbol min. ty p. max. units conditions output frequency f max ? ? 800 mhz at all temperatures propagation delay, ( note 1 )t pd 600 680 750 ps at ?40c 650 725 790 at +25c 690 790 890 at +85c output skew, ( note 2 , note 4 )t sk(o) ? 25 37 ps at all temperatures part-to-part skew, ( note 3 , note 4 ) t sk(pp) ? 85 225 ps at all temperatures buffer additive phase jitter, rms t apj ? ? 0.10 ps at all temperatures; refer to noise characteristics section peak-to-peak input voltage (differential configuration) v pp 150 800 1200 mv at all temperatures peak-to-peak output voltage v swing 470 800 950 mv at ?40c 600 800 930 at +25c 600 800 930 at +85c output rise/fall time t r /t f 200 ? 550 ps at all temperatures; 20% to 80% at full output swing. note 1: measured from the differential input crossing po int to the differential output crossing point. 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. 3: defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the dif- ferential cross points. 4: this parameter is defined in accordance with jedec standard 65.
? 2016 microchip technology inc. ds20005543b-page 5 pl138-48 temperature specifications ( note 1 ) parameters sym. min. typ. max. units conditions temperature ranges ambient operating temperature t a ?40 ? +85 c note 2 junction temperature t j ??+110c? storage temperature range t s ?65 ? +150 c ? soldering temperature ? ? ? +260 c 10 sec. note 1: the maximum allowable power dissipation is a functi on of ambient temperature, the maximum allowable junction temperature, and the thermal resi stance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the dev ice operating junction te mperature to exceed the maximum +125c rating. sustained junction temperat ures above +125c can impa ct the device reliability. 2: operating temperature is guaranteed by design for al l parts (commercial and indu strial), but tested for commercial grade only.
pl138-48 ds20005543b-page 6 ? 2016 microchip technology inc. 2.0 pin descriptions figure 2-1: pin configuration, 16-pin qfn. figure 2-2: pin configuration, 20-pin tssop. the descriptions of the pins are listed in table 2-1 . table 2-1: pin function table pin number qfn-16 pin number tssop-20 pin name type description 41v ee p power supply pin connection. 16 2 clk-en i synchronizing clock enable. when high, clock outputs follow clock input. when low, q outputs are forced low, qb outputs are forced high. lvttl/lvcmos interface levels. 50 k ? internal pull-up resistor. ? 3 clk-sel i clock select input. when high, selects clk1 input. when low, selects clk0 input. lvttl/lvcmos interface levels. 50 k ? internal pull-down resistor. 2 4 clk-in0 i true part of differential clock input signal. 75 k ? internal pull-down resistor. 3 5 clk-in0b i complementary part of differential clock input signal. 100 k ? internal pull-up and pull-down resistors.
? 2016 microchip technology inc. ds20005543b-page 7 pl138-48 ? 6 clk-in1 i true part of differential clock input signal. 75 k ? internal pull-down resistor. ? 7 clk-in1b i complementary part of differential clock input signal. 100 k ? internal pull-up and pull-down resistors. 1, 5 8, 9 dnc ? do not connect. 8, 13 10, 13, 18 v cc p power supply pin connection. 6, 9, 11 ,14 11, 14, 16, 19 qb0 ~ qb3 o lvpecl complementary output. 7, 10, 12, 15 12, 15, 17, 20 q0 ~ q3 o lvpecl true output. table 2-1: pin function table (continued) pin number qfn-16 pin number tssop-20 pin name type description
pl138-48 ds20005543b-page 8 ? 2016 microchip technology inc. 3.0 noise characteristics when a buffer is used to pass a signal, the buffer adds a li ttle bit of its own noise. the phase noise on the output of the buffer will be a little bit more than the phase noise of the input signal. to quantify the noise addition in the buffer we compare the phase jitter numbers from t he input and the output. the difference is called "additive phase jitter". the formula for the additive phase jitter is as follows: equation 3-1: figure 3-1: pl138-48 additive phase jitter plot, 622 mhz. table 3-1: pl138-48 noise characteristics parameters symbol min. typ. max. units conditions additive phase jitter t apj ?2040 fs v dd = 3.3v, frequency = 622.08 mhz offset = 12 khz ~ 20 mhz ?50100 v dd = 3.3v, frequency = 156.25 mhz offset = 12 khz ~ 20 mhz ?50100 v dd = 3.3v, frequency = 50 mhz offset = 1 khz ~ 1 mhz ?50100 v dd = 3.3v, frequency = 25 mhz offset = 1 khz ~ 1 mhz additivephasejitter outputphasejitter 2 inputphasejitter 2 ? =
? 2016 microchip technology inc. ds20005543b-page 9 pl138-48 4.0 parameter measur ement information figure 4-1: output waveform test circuit. figure 4-2: part-to-part skew. figure 4-3: output rise/fall time. figure 4-4: differential input level. figure 4-5: output skew. figure 4-6: propagation delay.
pl138-48 ds20005543b-page 10 ? 2016 microchip technology inc. 5.0 application information 5.1 input logic configurations the following circuits show different configurations for differ ent input logic type signals. for good signal integrity at the pl138 input, the signals need to be properly terminated acco rding to the logic type requirements. the signals need to be presented at the pl138 input according to v cmr , v pp , and other input requirements. figure 5-1: clk-in input driven by a 3.3v lvpecl driver. figure 5-2: 3.3v lvpecl driver, alternative termination. figure 5-3: clk-in input driven by a cml driver. figure 5-4: clk-in input driven by an sstl driver. figure 5-5: clk-in input driven by an lvds driver. figure 5-6: lvds driver, alternative ac-coupling. this circuit is for compatibility only. ac-coupling is not really required for lvds. the v cmr range of the pl138 reaches low enough that lvds signals can be connected directly to the pl138 input like in the circuit in figure 5-5 . figure 5-7: clk-in input driven by a cmos driver.
? 2016 microchip technology inc. ds20005543b-page 11 pl138-48 figure 5-8: clk-in input driven by a single-ended lvpecl. figure 5-9: clk-in input driven by an hcsl driver. hcsl presents its signals very close to the ground rail, below the v cmr range, so the hcsl signals cannot be connected to the pl138 input directly. ac-coupling is required for hcsl signals on the pl138 input. figure 5-10: input logic block diagram. 5.2 termination for lvpecl outputs the required termination for lvpecl is 50 ? to a v cc -2v dc voltage level. below are two schematics to implement this termination. figure 5-11: lvpecl termination schematic #1. ?v cc = 3.3v - ideal values: r1 = 127 ? , r2 = 82.5 ? - commercial values (e24): r1 = 130 ? , r2 = 82 ? ?v cc = 2.5v - ideal values: r1 = 250 ? , r2 = 62.5 ? - commercial values (e24): r1 = 240 ? , r2 = 62 ? table 5-1: input pin characteristics input parameter min. typ. max. units clk-in0, clk-in1 pull-down resistor ?75 ? k ? clk-in0b, clk_in1b pull-up & pull-down resistors ?100 ? clk-en pull-up resistor ?50 ? clksel pull-down resistor ?50 ? table 5-2: input clock control selection clk_sel selected source 0clk-in0 1clk-in1 table 5-3: input clock function inputs outputs clk-en clksel source q0:q3 q0b:q3b 0 0 clk-in0 disabled low disabled high 0 1 clk-in1 disabled low disabled high 1 0 clk-in0 enabled enabled 1 1 clk-in1 enabled enabled
pl138-48 ds20005543b-page 12 ? 2016 microchip technology inc. figure 5-12: lvpecl termination schematic #2. schematic #2 is an alternative simplified termination. ?v cc = 3.3v - ideal value: rt = 48.7 ? - commercial value: rt = 50 ? (e24: 51 ? ) ?v cc = 2.5v - ideal value: rt = 18.7 ? - commercial value: rt = 18 ? 5.3 power considerations driving lvpecl outputs requ ires an amount of power that can warm up the chip significantly. the general requirement for the chip is that the junction temperature should not exceed +110c. the power consumption can be divided into two parts: 1. core power dissipation 2. output buffer power dissipation 5.3.1 core power dissipation the chip core power is equal to v cc i ee . with a worst case v cc and i ee , the power dissipation in the core is 3.63v 45 ma = 163 mw. 5.3.2 output buffer power dissipation the output buffers are not exposed to the full v cc ? v ee voltage. on the differential output, one line is at logic 1 with a small voltage across the buffer and a large output current. the othe r line is at logic 0 with a larger voltage across the buffer and a smaller output current. the power dissipation per output buffer is 32 mw. only buffers that are loaded will have power dissipation. with all 4 buffers loaded the worst case output buffer power dissipation will be 128 mw. total chip power dissipation, worst case, is 163 mw + 128 mw = 291 mw. 5.3.3 junction temperature how much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to the environment, also known as ?junction to ambient?. the thermal resistance depends upon the type of package, how the package is assembled to the pcb and if there is additional air flow for improved cooling. the temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to ja power. for an ambient temperature of +85c, all outputs loaded and no air flow, the junction temperature t j = 85c + 73 0.291 = 106c. the temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to ja power. for an ambient temperature of +85c, all outputs loaded and no air flow, the junction temperature t j = 85c + 60 0.291 = 102c. table 5-4: 20-pin tssop thermal resistance air flow velocity in linear feet/minute ja value for jedec standard multi-layer pcb 073c/w 200 67c/w 500 64c/w table 5-5: 16-pin qfn thermal resistance air flow velocity in linear feet/minute ja value for jedec standard multi-layer pcb 060c/w 200 53c/w 500 46c/w
? 2016 microchip technology inc. ds20005543b-page 13 pl138-48 6.0 package marking information 16-lead qfn 3.0 mm x 3.5 mm package outline and recommended land pattern note: for the most current package drawings, please see the microchip packaging s pecification located at http://www.microchip.com/packaging
pl138-48 ds20005543b-page 14 ? 2016 microchip technology inc. 20-lead tssop package outline and recommended land pattern note: for the most current package drawings, please see the microchip packaging s pecification located at http://www.microchip.com/packaging
? 2016 microchip technology inc. ds20005543b-page 15 pl138-48 appendix a: revision history revision a (may 2016) ? converted micrel data sheet pl138-48 to micro- chip ds20005543a. ? minor text changes throughout. revision b (june 2016) ? updated output frequency tolerances to 800 mhz.
pl138-48 ds20005543b-page 16 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005543b-page 17 pl138-48 product identification system to order or obtain information, e.g., on pricing or delivery, contact your local microchip representative or sales office . examples: a) pl138-48oc-r: 2.5v - 3.3v, low-skew, 1:4 differential pecl fanout buf- fer, 20-pin tssop, commer- cial temperature range, tape & reel b) PL138-48QI: 2.5v - 3.3v, low-skew, 1:4 differential pecl fanout buf- fer, 16-pin qfn, industrial temperature range, tube c) pl138-48oi-r: 2.5v - 3.3v, low-skew, 1:4 differential pecl fanout buf- fer, 20-pin tssop, industrial temperature range, tape & reel d) pl138-48qc: 2.5v - 3.3v, low-skew, 1:4 differential pecl fanout buf- fer, 16-pin qfn, commercial temperature range, tube part no. device device: pl138-48: 2.5v - 3.3v, low-skew, 1:4 differential pecl fanout buffer package: o = 20-pin tssop q = 16-pin qfn temperature range: c= 0 ? c to +70 ? c (commercial) i = ?40 ? c to +85 ? c (industrial) packing option: blank = tube r = tape & reel x package x temperature range - x packing option
pl138-48 ds20005543b-page 18 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005543b-page 19 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0540-5 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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