View MCP795W10-ISL_8601356.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2011-2016 microchip technology inc. ds20002280d-page 1 mcp795w1x/mcp795w2x device selection table timekeeping features real-time clock/calendar (rtcc): - hours, minutes, seconds, hundredth of seconds, day of week, date, month, year - leap year compensated to 2399 - 12/24-hour modes oscillator for 32.768 khz crystals: - optimized for 6-9 pf crystals on-chip digital trimming/calibration: - 1 ppm resolution - 259 ppm range dual programmable alarms clock output function with selectable frequency power-fail timestamp: - time logged on switchover to and from battery mode low-power features wide voltage range: - operating voltage range of 1.8v to 3.6v - backup voltage range of 1.3v to 3.6v low typical timekeeping current: - operating from v cc : 1.2 a at 3.0v - operating from v bat : 1.0 a at 3.0v automatic switchover to battery backup enhanced features programmable watchdog timer: - dedicated output pin - cleared via spi bus or evhs input dual configurable event detect modules: - high-speed digital event detect for program- mable pulse count detection - low-speed event detect for programmable switch debouncing user memory 64-byte battery-backed sram 1 kbit or 2 kbit eeprom: - software write-protect - page write up to 8 bytes - endurance: 1m erase/write cycles 128-bit protected eeprom area: - robust write unlock sequence - eui-48? mac address (mcp795wx1) - eui-64? mac address (mcp795wx2) operating ranges spi serial interface: - spi clock rate up to 5 mhz temperature range: - industrial (i): -40c to +85c packages 14-lead soic and tssop package types (not to scale) part number eeprom (kbits) protected eeprom mcp795w10 1 blank mcp795w20 2 blank mcp795w11 1 eui-48 ? mcp795w21 2 eui-48 ? mcp795w12 1 eui-64 ? mcp795w22 2 eui-64 ? evhs clkout v cc x1 soic/tssop 1 2 3 4 5 6 7 14 13 12 11 10 9 8 evls wdo irq cs v ss so si sck v bat x2 battery-backed spi real-time clock/calendar with enhanced features downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 2 ? 2011-2016 microchip technology inc. description the mcp795wxx real-time clock/calendar (rtcc) tracks time using internal counters for hours, minutes, seconds, hundredth of seconds, days, months, years and day of week. alarms can be configured on all counters up to and including months. for usage and configuration, the mcp795wxx supports spi communications up to 5 mhz. the mcp795wxx is designed to operate using a 32.768 khz tuning fork crystal with external crystal load capacitors. on-chip digital trimming can be used to adjust for frequency variance caused by crystal tolerance and temperature. sram and timekeeping circuitry are powered from the backup supply when main power is lost, allowing the device to maintain accurate time and the sram contents. the times when the device switches over to the backup supply and when primary power returns are both logged by the power-fail timestamp. the mcp795wxx features 128 bits of eeprom which is only writable after an unlock sequence, making it ideal for storing a unique id or other critical information. the mcp795wx1 and mcp795wx2 are pre-programmed with eui-48 and eui-64 addresses, respectively. custom programming is also available. two event detect modules are included on the mcp795wxx. the high-speed event detect module will generate an interrupt after a programmable number of pulses have been detected. the low-speed event detect module can be used to debounce mechanical switches and includes a selectable debounce period. the mcp795wxx also features an integrated watchdog timer peripheral. this allows applications to improve system robustness by moving this functionality outside of the microcontroller. the mcp795wxx has versatile output options. there is a dedicated pin for outputting a selectable frequency square wave or for use as a general purpose output. additionally, the alarms can be assigned to either the watchdog timer interrupt output or the event detect interrupt output. figure 1-1: typical ap plication schematic v cc v cc v cc v bat c x1 32.768 k h z c x2 v bat x2 x1 cs sck si v ss v cc 12 3 7 10 9 6 14 pic ? mcu mcp795wxx so 8 wdo 4 clkout 13 irq 5 mclr evls 11 evhs 12 evhs evls downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 3 mcp795w1x/mcp795w2x figure 1-2: block diagram 32.768 khz spi interface and addressing control logic sram eeprom clock divider digital trimming square wave output alarms wdt hundredth of seconds minutes hours day of week date month configuration oscillator x1 x2 sck wdo power control and switchover v cc v bat power-fail timestamp v ss event watchdog detect timer output logic interrupt output logic clkout evhs evls cs si so year seconds irq downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 4 ? 2011-2016 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss .......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature under bias ................................................................................................. ..............-40c to +85c esd protection on all pins ..................................................................................................... .....................................4 kv table 1-1: dc characteristics ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: industrial (i): t a = -40c to +85c v cc = 1.8v to 3.6v param. no. sym. characteristic min. typ. ( 2 ) max. units test conditions d1 v ih high-level input voltage 0.7 v cc v cc + 1 v d2 v il low-level input voltage -0.3 0.3v cc vv cc ??? 2.5v -0.3 0.2v cc v cc < 2.5v d3 v ol low-level output voltage 0.4 v i ol = 2.1 ma, v cc ?? 2.5v 0 . 2 i ol = 1.0 ma, v cc < 2.5v d4 v oh high-level output voltage v cc - 0.5 v i oh = -400 a d5 i li input leakage current 1 a cs = v cc , v in = v ss or v cc d6 i lo output leakage current 1 a cs = v cc , v out = v ss or v cc d7 c int pin capacitance (all inputs and outputs) 7p f v cc = 3.6v ( note 1 ) t a = 25c, f = 1 mhz d8 c osc oscillator pin capacitance (x1, x2 pins) 3p f note 1 d9 i cceerd eeprom operating current 3 ma v cc = 3.6v, f clk = 5 mhz so = open i cceewr 5m av cc = 3.6v d10 i ccread sram/rtcc operating current 3m a v cc = 3.6v, f clk = 5 mhz so = open i ccwrite 3m av cc = 3.6v, f clk = 5 mhz d11 i ccdat vcc data retention current (oscillator off) 1 a v cc = 3.6v note 1: this parameter is not tested but ensured by characterization. 2: typical measurements taken at room temperature. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 5 mcp795w1x/mcp795w2x d12 i cct timekeeping current 1.2 a v cc = 1.8v, cs = v cc , evhs = v ss , evls = v ss ( note 1 ) 1 . 21 . 8 a v cc = 3.0v, cs = v cc , evhs = v ss , evls = v ss ( note 1 ) 2 . 6 a v cc = 3.6v, cs = v cc , evhs = v ss , evls = v ss ( note 1 ) d13 v trip power-fail switchover voltage 1.3 1.5 1.7 v d14 v bat backup supply voltage range 1.3 3.6 v d15 i batt timekeeping backup current 850 na v bat = 1.3v, v cc =v ss ( note 1 ) 1000 1200 na v bat = 3.0v, v cc =v ss ( note 1 ) 2300 na v bat = 3.6v, v cc =v ss ( note 1 ) d16 i batdat v bat data-retention current (oscillator off) 850 na v bat = 3.6v, v cc = v ss dc characteristics (continued) electrical characteristics: industrial (i): t a = -40c to +85c v cc = 1.8v to 3.6v param. no. sym. characteristic min. typ. ( 2 ) max. units test conditions note 1: this parameter is not tested but ensured by characterization. 2: typical measurements taken at room temperature. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 6 ? 2011-2016 microchip technology inc. table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): t a = -40c to +85c v cc = 1.8v to 3.6v param. no. sym. characteristic min. typ. max. units test conditions 1f clk clock frequency 5 mhz 2.5v ?? vcc ? 3.6v 3 mhz 1.8v ?? vcc ? 2.5v 2t css cs setup time 100 ns 2.5v ?? vcc ? 3.6v 150 ns 1.8v ?? vcc ? 2.5v 3t csh cs hold time 100 ns 2.5v ?? vcc ? 3.6v 150 ns 1.8v ?? vcc ? 2.5v 4t csd cs disable time 50 ns 5t su data setup time 20 ns 2.5v ?? vcc ? 3.6v 30 ns 1.8v ?? vcc ? 2.5v 6t hd data hold time 40 ns 2.5v ?? vcc ? 3.6v 50 ns 1.8v ?? vcc ? 2.5v 7t r sck rise time 100 ns note 1 8t f sck fall time 100 ns note 1 9t hi clock high time 100 ns 2.5v ?? vcc ? 3.6v 150 ns 1.8v ?? vcc ? 2.5v 10 t lo clock low time 100 ns 2.5v ?? vcc ? 3.6v 150 ns 1.8v ?? vcc ? 2.5v 11 t cld clock delay time 50 ns 12 t cle clock enable time 50 ns 13 t v output valid from clock low 1 0 0n s2 . 5 v ?? vcc ? 3.6v 160 ns 1.8v ?? vcc ? 2.5v 14 t ho output hold time 0 ns note 1 15 t dis output disable time 80 ns 2.5v ?? vcc ? 3.6v ( note 1 ) 160 ns 1.8v ?? vcc ? 2.5v ( note 1 ) 16 t wc internal write cycle time 5 ms note 2 17 t fvcc v cc fall time 300 s note 1 18 t rvcc v cc rise time 0 s note 1 19 f osc oscillator frequency 32.768 khz 20 t osf oscillator timeout period 1 ms note 1 21 endurance 1m e/w cycles page mode, 25c v cc = 3.6v ( note 1 note 1: this parameter is not tested but ensured by characterization. 2: t wc begins on the rising edge of cs after a valid write sequence and ends when the internal write cycle is complete. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 7 mcp795w1x/mcp795w2x figure 1-1: serial input timing figure 1-2: serial output timing figure 1-3: power supply transition timing cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 4 2 10 9 cs sck so 10 9 13 msb out lsb out 3 15 dont care si 14 v cc v trip ( max ) v trip ( min ) 17 18 downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 8 ? 2011-2016 microchip technology inc. 2.0 typical performance curves figure 2-1: timekeeping backup current vs. backup supply voltage figure 2-2: timekeeping current vs. supply voltage note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data represented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.30 1.60 1.90 2.20 2.50 2.80 3.10 3.40 i batt current (a) v bat voltage (v) r 40 25 85 t a = -40c t a = 25c t a = 85c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.80 2.10 2.40 2.70 3.00 3.30 3.60 i cct current (a) v cc voltage (v) r 40 25 85 t a = -40c t a = 25c t a = 85c downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 9 mcp795w1x/mcp795w2x 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin function table 3.1 chip select (cs ) a low level on this pin selects the device, whereas a high level deselects the device. a nonvolatile memory programming cycle which is already initiated or in progress will be completed, regardless of the cs input signal. when the device is deselected, so goes into the high-impedance state, allowing multiple parts to share the same spi bus. after power-up, a high-to-low transition on cs is required prior to any sequence being initiated. 3.2 serial clock (sck) this pin is used to synchronize the communication between a master and the mcp795wxx. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 3.3 serial input (si) this pin is used to transfer data into the device. it receives instructions, addresses and data. data is latched on the rising edge of the serial clock. 3.4 serial output (so) this pin is used to transfer data out of the mcp795wxx. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.5 oscillator input/output (x1, x2) these pins are used as the connections for an external 32.768 khz quartz crystal and load capacitors. x1 is the crystal oscillator input and x2 is the output. the mcp795wxx is designed to allow for the use of external load capacitors in order to provide additional flexibility when choosing external crystals. the mcp795wxx is optimized for crystals with a specified load capacitance of 6-9 pf. x1 also serves as the external clock input when the mcp795wxx is configured to use an external oscilla- tor. 3.6 watchdog output (wdo ) this is an output pin for the watchdog timer and, optionally, the alarms. during normal operation, the pin remains high. if a watchdog timer overflow occurs, the pin outputs a low pulse. the width of the pulse is user-selectable. if an alarm output is assigned to the wdo pin, then the pin will output a low pulse when the alarm triggers. the wdo pin is an open-drain output and requires a pull-up resistor to v cc (typically 10 k ? ). this pin may be left floating if not used. name 14-pin soic 14-pin tssop pin function x1 1 1 quartz crystal input, external oscillator input x2 2 2 quartz crystal output v bat 3 3 battery backup supply input wdo 4 4 watchdog output irq 5 5 interrupt output cs 6 6 chip select input v ss 7 7 ground so 8 8 serial data output si 9 9 serial data input sck 10 10 serial clock input evhs 11 11 high-speed event detect input evls 12 12 low-speed event detect input clkout 13 13 square wave clock output v cc 14 14 primary power supply downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 10 ? 2011-2016 microchip technology inc. 3.7 interrupt output (irq ) this is an output pin for the event detect modules and, optionally, the alarms. if an event is detected by either module, then this pin will output a low signal until the interrupt flag has been cleared. if an alarm output is assigned to the irq pin, then the pin will output a low signal when the alarm triggers. the pin will remain low until the alarm interrupt flag has been cleared. the irq pin is an open-drain output and requires a pull-up resistor to v cc or v bat (typically 10 k ? ). this pin may be left floating if not used. 3.8 square wave clock output (clkout) this is the output pin for the square wave output function. this pin may be left floating if not used. 3.9 high-speed event detect input (evhs) this pin is used as the input for the high-speed event detect module. if the high-speed event detect module is not being used, the evhs pin should be connected to v cc or v ss . 3.10 low-speed event detect input (evls) this pin is used as the input for the low-speed event detect module. if the low-speed event detect module is not being used, the evls pin should be connected to v cc or v ss . 3.11 backup supply (v bat ) this is the input for a backup supply to maintain the rtcc and sram registers during the time when v cc is unavailable. power should be applied to v cc before v bat . if the battery backup feature is not being used, the v bat pin should be connected to v ss . downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 11 mcp795w1x/mcp795w2x 4.0 spi bus operation the mcp795wxx is designed to interface directly with the serial peripheral interface (spi) port of many of todays popular microcontroller families, including microchips pic ? microcontrollers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly in software to match the spi protocol. the mcp795wxx contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low for the entire operation. table 4-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb first, lsb last. data (si) is sampled on the first rising edge of sck after cs goes low. table 4-1: instruction set summary instruction name instruction format description eeread 0000 0011 read data from eeprom array beginning at selected address eewrite 0000 0010 write data to eeprom array beginning at selected address eewrdi 0000 0100 reset the write enable latch (disable write operations) eewren 0000 0110 set the write enable latch (enable write operations) srread 0000 0101 read status register srwrite 0000 0001 write status register read 0001 0011 read data from rtcc/sram array beginning at selected address write 0001 0010 write data to rtcc/sram array beginning at selected address unlock 0001 0100 unlock the protected eeprom block for a write operation idwrite 0011 0010 write data to the protected eeprom block beginning at selected address idread 0011 0011 read data from the protected eeprom block beginning at the selected address clrwdt 0100 0100 clear watchdog timer clrram 0101 0100 clear all sram data to 0 downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 12 ? 2011-2016 microchip technology inc. 5.0 functional description the mcp795wxx is a highly-integrated real-time clock/calendar (rtcc). using an on-board, low-power oscillator, the current time is maintained in hundredths of seconds, seconds, minutes, hours, day of week, date, month, and year. the mcp795wxx also features 64 bytes of general purpose sram, either 2 kbits (mcp795w2x) or 1 kbit (mcp795w1x) of eeprom, and 16 bytes of protected eeprom. two alarm modules allow interrupts to be generated at specific times with flexible comparison options. digital trimming can be used to compensate for inaccuracies inherent with crystals. using the backup supply input and an integrated power switch, the mcp795wxx will automatically switch to backup power when primary power is unavailable, allowing the current time and the sram contents to be maintained. the timestamp module captures the time when primary power is lost and when it is restored. the watchdog timer module can be used to reset an application that has become unresponsive. the high-speed event detect module can be used to detect pulse signals recovered from communication links, while the low-speed event detect module can be used to debounce switches and detect button presses. the rtcc configuration and status registers are used to access all of the modules featured on the mcp795wxx. 5.1 memory organization the mcp795wxx features four different blocks of memory: the rtcc registers, general purpose sram, 2 kbit eeprom (1 kbit for the mcp795w1x) with software write-protect, and protected eeprom. the rtcc registers and sram share the same address space and are accessed through the read and write instructions. the eeprom region is accessed using the eeread and eewrite instructions, and the protected eeprom is accessed using the idread and idwrite instructions. unused locations are not accessible. the mcp795wxx will not acknowledge if the address is out of range, as shown in the shaded region of the memory maps in figure 5-1 and figure 5-2 . the rtcc registers are contained in addresses 0x00-0x1f. ta bl e 5 - 1 shows the detailed rtcc register map. there are 64 bytes of user-accessible sram, located in the address range 0x20-0x5f. the sram is a separate block from the rtcc registers. all rtcc registers and sram locations are maintained while operating from backup power. figure 5-1: memory map for mcp795w1x time and date sram (64 bytes) power-fail/power-up timestamps alarm 1 alarm 0 configuration and trimming 0x00 0x07 0x08 0x0b 0x0c 0x11 0x12 0x17 0x18 0x1f 0x20 0x5f 0x60 0xff unimplemented; device does not respond rtcc registers/sram protected eeprom (16 bytes) 0x00 0xff 0x00 0x0f 0x10 0xff unimplemented; device does not respond eeprom eui-48/eui-64 node address unimplemented; mapped back to 0x00-0x7f 0x7f 0x80 eeprom (128 bytes) protected eeprom downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 13 mcp795w1x/mcp795w2x figure 5-2: memory map for mcp795w2x time and date sram (64 bytes) power-fail/power-up timestamps alarm 1 alarm 0 configuration and trimming 0x000x07 0x08 0x0b 0x0c 0x11 0x12 0x17 0x18 0x1f 0x20 0x5f 0x60 0xff unimplemented; device does not respond rtcc registers/sram protected eeprom (16 bytes) 0x00 0xff 0x00 0x0f 0x10 0xff unimplemented; device does not respond eeprom eui-48/eui-64 node address eeprom (256 bytes) protected eeprom downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 14 ? 2011-2016 microchip technology inc. table 5-1: detailed rtcc register map addr. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 section 5.3 ?timekeeping? 00h rtchsec hsecten3 hsecten2 hsecten1 hsecten0 hsecone3 hsecone2 hsecone1 hsec one0 01h rtcsec st secten2 secten1 secten0 secone3 secone2 secone1 secone0 02h rtcmin minten2 minten1 minten0 minone3 minone2 minone1 minone0 03h rtchour trimsign 12/24 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 04h rtcwkday oscrun pwrfail vbaten wkday2 wkday1 wkday0 05h rtcdate dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 06h rtcmth lpyr mthten0 mthone3 mthone2 mthone1 mthone0 07h rtcyear yrten3 yrten2 yrten1 yrten0 yrone3 yrone2 yrone1 yrone0 08h control out sqwen alm1en alm0en extosc crstrim sqwfs1 sqwfs0 09h osctrim trimval7 trimval6 trimval5 trimval4 trimval3 trimval2 trimval 1 trimval0 section 5.5 ?watchdog timer? 0ah wdtcon wdten wdtif wdtdlyen wdtpws wdtps3 wdtps2 wdtps1 wdtps0 section 5.6 ?event detection? 0bh evdtcon evhif evlif evhen evlen evwdten evlps evhcs1 evhcs0 section 5.4 ?alarms? 0ch alm0sec secten2 secten1 secten0 secone3 secone2 secone1 secone0 0dh alm0min minten2 minten1 minten0 minone3 minone2 minone1 minone0 0eh alm0hour 12/24 ( 2 ) am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 0fh alm0wkday alm0pin alm0msk2 alm0msk1 alm0msk0 alm0if wkday2 wkday1 wkday0 10h alm0date dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 11h alm0mth mthten0 mthone3 mthone2 mthone1 mthone0 section 5.4 ?alarms? 12h alm1hsec hsecten3 hsecten2 hsecten1 hsecten0 hsecone3 hsecone2 hsecone1 hsecone0 13h alm1sec secten2 secten1 secten0 secone3 secone2 secone1 secone0 14h alm1min minten2 minten1 minten0 minone3 minone2 minone1 minone0 15h alm1hour 12/24 ( 2 ) am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 16h alm1wkday alm1pin alm1msk2 alm1msk1 alm1msk0 alm1if wkday2 wkday1 wkday0 17h alm1date dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 section 5.10.1 ?power-fail timestamp? power-down timestamp 18h pwrdnmin minten2 minten1 minten0 minone3 minone2 minone1 minone0 19h pwrdnhour 1 2 / 2 4 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 1ah pwrdndate dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 1bh pwrdnmth wkday2 wkday1 wkday0 mthten0 mthone3 mthone2 mthone1 mthone0 power-up timestamp 1ch pwrupmin minten2 minten1 minten0 minone3 minone2 minone1 minone0 1dh pwruphour 1 2 / 2 4 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 1eh pwrupdate dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 1fh pwrupmth wkday2 wkday1 wkday0 mthten0 mthone3 mthone2 mthone1 mthone0 note 1: grey areas are unimplemented. 2: the 12/24 bits in the almxhour registers are read-only and reflect the value of the 12/24 bit in the rtchour register. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 15 mcp795w1x/mcp795w2x 5.2 oscillator configurations the mcp795wxx can be operated in two different oscillator configurations: using an external crystal or using an external clock input. 5.2.1 external crystal the crystal oscillator circuit on the mcp795wxx is designed to operate with a standard 32.768 khz tuning fork crystal and matching external load capacitors. by using external load capacitors, the mcp795wxx allows for a wide selection of crystals. suitable crystals have a load capacitance (c l ) of 6-9 pf. crystals with a load capacitance of 12.5 pf are not recommended. figure 5-3 shows the pin connections when using an external crystal. figure 5-3: crystal operation 5.2.1.1 choosing load capacitors c l is the effective load capacitance as seen by the crystal, and includes the physical load capacitors, pin capacitance, and stray board capacitance. equation 5-1 can be used to calculate c l . c x1 and c x2 are the external load capacitors. they must be chosen to match the selected crystals specified load capacitance. equation 5-1: load capacitance calculation 5.2.1.2 layout considerations the oscillator circuit should be placed on the same side of the board as the device. place the oscillator circuit close to the respective oscillator pins. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. the grounded copper pour should be routed directly to v ss . do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. layout suggestions are shown in figure 5-4 . in-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. with fine-pitch packages, it is not always possible to completely surround the pins and components. a suitable solution is to tie the broken guard sections to a mirrored ground layer. in all cases, the guard trace(s) must be returned to ground. for additional information and design guidance on oscillator circuits, please refer to these microchip application notes, available at the corporate website ( www.microchip.com ): an1365, recommended usage of microchip serial rtcc devices an1519, recommended crystals for microchip stand-alone real-time clock calendar devices note 1: the st bit must be set to enable the crystal oscillator circuit. 2: always verify oscillator performance over the voltage and temperature range that is expected for the application. note: if the load capacitance is not correctly matched to the chosen crystals specified value, the crystal may give a frequency outside of the crystal manufacturers specifications. c x 1 c x 2 quartz x1 st to internal logic crystal x2 mcp795wxx c l c x 1 c x 2 ? c x 1 c x 2 + -------------------------- c stray + = where: c l effective load capacitance = c x 1 capacitor value on x1 c osc + = c x 2 capacitor value on x2 c osc + = c stray pcb stray capacitance = downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 16 ? 2011-2016 microchip technology inc. figure 5-4: suggested placement of the oscillator circuit 5.2.2 external clock input a 32.768 khz external clock source can be connected to the x1 pin ( figure 5-5 ). when using this configuration, the x2 pin should be left floating. figure 5-5: extern al clock input operation 5.2.3 oscillator failure status the mcp795wxx features an oscillator failure flag, oscrun, that indicates whether or not the oscillator is running. the oscrun bit is automatically set after 32 oscillator cycles are detected. if no oscillator cycles are detected for more than t osf , then the oscrun bit is automatically cleared ( figure 5-6 ). this can occur if the oscillator is stopped by clearing the st bit or due to oscillator failure. figure 5-6: oscillator failur e status timing diagram table 5-2: summary of registers asso ciated with oscillator configuration gnd ` x1x2 device pins cx1 cx2 gnd x1x2 bottom layer copper pour oscillator crystal top layer copper pour cx1 cx2 device pins (tied to ground) (tied to ground) single-sided and in-line layouts: fine-pitch (dual-sided) layouts: oscillator crystal copper pour (tied to ground) note: the extosc bit must be set to enable an external clock source. x1 clock from ext. source mcp795wxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page rtcsec st secten2 secten1 secten0 secone3 secone2 secone1 secone0 18 rtcwkday oscrun pwrfail vbaten wkday2 wkday1 wkday0 20 control out sqwen alm1en alm0en extosc crstrim sqwfs1 sqwfs0 35 legend: = unimplemented location, read as 0 . shaded cells are not used by oscillator configuration. x1 oscrun bit < t osf t osf 32 clock cycles downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 17 mcp795w1x/mcp795w2x 5.3 timekeeping the mcp795wxx maintains the current time and date using an external 32.768 khz crystal or clock source. separate registers are used for tracking hundredths of seconds, seconds, minutes, hours, day of week, date, month, and year. the mcp795wxx automatically adjusts for months with less than 31 days and compensates for leap years from 2001 to 2399. the year is stored as a two-digit value. both 12-hour and 24-hour time formats are supported and are selected using the 12/24 bit. the day of week value counts from 1 to 7, increments at midnight, and the representation is user-defined (i.e., the mcp795wxx does not require 1 to equal sunday, etc.). all time and date values are stored in the registers as binary-coded decimal (bcd) values. the mcp795wxx will continue to maintain the time and date while operating off the backup supply. when reading from the timekeeping registers, the registers are buffered to prevent errors due to rollover of counters. the following events cause the buffers to be updated: when a read is initiated from the rtcc registers (addresses 0x00 to 0x1f) during an rtcc register read operation, when the register address rolls over from 0x1f to 0x00 the timekeeping registers should be read in a single operation to utilize the on-board buffers and avoid rollover issues. 5.3.1 digit carry rules the following list explains which timer values cause a digit carry when there is a rollover: time of day: from 11:59:59.99 pm to 12:00:00.00 am (12-hour mode) or 23:59:59.99 to 00:00:00.00 (24-hour mode), with a carry to the date and weekday fields date: carries to the month field according to table 5-3 weekday: from 7 to 1 with no carry month: from 12/31 to 01/01 with a carry to the year field year: from 99 to 00 with no carry table 5-3: day to month rollover schedule 5.3.2 generating hundredth of seconds a special algorithm is required to accurately generate hundredth of seconds. the circuitry utilizes the 4.096 khz clock signal and counts 41 clock pulses each for 24 increments of the hundredth of seconds count. the circuitry then counts 40 clock pulses for the next increment of the hundredth of second count. this results in every 25 hundredth of seconds increments equaling exactly 250 ms. long term, the hundredth of seconds frequency will average the desired 100 hz, while jitter is minimized short term. equation 5-2: hundredth of seconds generation note 1: loading invalid values into the time and date registers will result in undefined operation. 2: to avoid rollover issues when loading new time and date values, the oscillator/clock input should be disabled by clearing the st bit for external crystal mode and the extosc bit for external clock input mode. after waiting for the oscrun bit to clear, the new values can be loaded and the st or extosc bit can then be re-enabled. month name maximum date 01 january 31 02 february 28 or 29 ( 1 ) 03 march 31 04 april 30 05 may 31 06 june 30 07 july 31 08 august 31 09 september 30 10 october 31 11 november 30 12 december 31 note 1: 29 during leap years, otherwise 28. 41 clocks 24 counts ? ?? 40 clocks 1 count ? ?? + 4,096 hz ------------------------------------------------------------------------------------------------------------ --- 2 5 0 m s = downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 18 ? 2011-2016 microchip technology inc. register 5-1: rtchsec: timekeeping hundredth of seconds value register (address 0x00) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 hsecten3 hsecten2 hsecten1 hsecten0 hsecone3 hsecone2 hsecone1 hsecone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-4 hsecten<3:0>: binary-coded decimal value of hundredth of seconds tens digit contains a value from 0 to 9 bit 3-0 hsecone<3:0>: binary-coded decimal value of hundredth of seconds ones digit contains a value from 0 to 9 register 5-2: rtcsec: timekeeping seconds value register (address 0x01) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 st secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 st: start oscillator bit 1 = oscillator enabled 0 = oscillator disabled bit 6-4 secten<2:0>: binary-coded decimal value of seconds tens digit contains a value from 0 to 5 bit 3-0 secone<3:0>: binary-coded decimal value of seconds ones digit contains a value from 0 to 9 register 5-3: rtcmin: timekeeping minutes value register (address 0x02) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 minten<2:0>: binary-coded decimal value of minutes tens digit contains a value from 0 to 5 bit 3-0 minone<3:0>: binary-coded decimal value of minutes ones digit contains a value from 0 to 9 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 19 mcp795w1x/mcp795w2x register 5-4: rtchour: timekeeping ho urs value register (address 0x03) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trimsign 12/24 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown i f 12/ 24 = 1 (12-hour format): bit 7 trimsign: trim sign bit 1 = add clocks to correct for slow time 0 = subtract clocks to correct for fast time bit 6 12/24 : 12 or 24 hour time format bit 1 = 12-hour format 0 = 24-hour format bit 5 am /pm: am/pm indicator bit 1 = pm 0 = am bit 4 hrten0: binary-coded decimal value of hours tens digit contains a value from 0 to 1 bit 3-0 hrone<3:0>: binary-coded decimal value of hours ones digit contains a value from 0 to 9 if 12/ 24 = 0 (24-hour format): bit 7 trimsign: trim sign bit 1 = add clocks to correct for slow time 0 = subtract clocks to correct for fast time bit 6 12/24 : 12 or 24 hour time format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 hrten<1:0>: binary-coded decimal value of hours tens digit contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary-coded decimal value of hours ones digit contains a value from 0 to 9 downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 20 ? 2011-2016 microchip technology inc. register 5-5: rtcwkday: timekeeping weekday value register (address 0x04) u-0 u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 oscrun pwrfail vbaten wkday2 wkday1 wkday0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5 oscrun: oscillator status bit 1 = oscillator is enabled and running 0 = oscillator has stopped or has been disabled bit 4 pwrfail: power failure status bit ( 1 , 2 ) 1 = primary power was lost and the power-fail timestamp registers have been loaded (must be cleared in software). clearing this bit resets the power-fail timestamp registers to 0 . 0 = primary power has not been lost bit 3 vbaten: external battery backup supply (v bat ) enable bit 1 = v bat input is enabled 0 = v bat input is disabled bit 2-0 wkday<2:0>: binary-coded decimal value of day of week contains a value from 1 to 7. the representation is user-defined. note 1: the pwrfail bit must be cleared to log new timestamp data. this is to ensure previous timestamp data is not lost. 2: the pwrfail bit can be cleared by writing a 0 . once cleared, the pwrfail bit cannot be written to a 1 in software. register 5-6: rtcdate: timekeeping date value register (address 0x05) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 dateten<1:0>: binary-coded decimal value of dates tens digit contains a value from 0 to 3 bit 3-0 dateone<3:0>: binary-coded decimal value of dates ones digit contains a value from 0 to 9 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 21 mcp795w1x/mcp795w2x table 5-4: summary of registers associated with timekeeping register 5-7: rtcmth: timekeeping mo nth value register (address 0x06) u-0 u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 lpyr mthten0 mthone3 mthone2 mthone1 mthone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5 lpyr: leap year bit 1 = year is a leap year 0 = year is not a leap year bit 4 mthten0: binary-coded decimal value of months tens digit contains a value of 0 or 1 bit 3-0 mthone<3:0>: binary-coded decimal value of months ones digit contains a value from 0 to 9 register 5-8: rtcyear: timekeeping year value register (address 0x07) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 yrten3 yrten2 yrten1 yrten0 yrone3 yrone2 yrone1 yrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-4 yrten<3:0>: binary-coded decimal value of years tens digit contains a value from 0 to 9 bit 3-0 yrone<3:0>: binary-coded decimal value of years ones digit contains a value from 0 to 9 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page rtchsec hsecten3 hsecten2 hsecten1 hsecten0 hsecone3 hsecone2 hsecone1 hsecone0 18 rtcsec st secten2 secten1 secten0 secone3 secone2 secone1 secone0 18 rtcmin minten2 minten1 minten0 minone3 minone2 minone1 minone0 18 rtchour trimsign 12/24 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 19 rtcwkday oscrun pwrfail vbaten wkday2 wkday1 wkday0 20 rtcdate dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 20 rtcmth lpyr mthten0 mthone3 mthone2 mthone1 mthone0 21 rtcyear yrten3 yrten2 yrten1 yrten0 yrone3 yrone2 yrone1 yrone0 21 legend: = unimplemented location, read as 0 . shaded cells are not used in timekeeping. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 22 ? 2011-2016 microchip technology inc. 5.4 alarms the mcp795wxx features two independent alarms. each alarm can be used to either generate an interrupt at a specific time in the future, or to generate a periodic interrupt every second (alarm 1 only), minute, hour, day, day of week, or month. there is a separate interrupt flag, almxif, for each alarm. the interrupt flags are set by hardware when the chosen alarm mask condition matches ( ta b l e 5 - 5 and table 5-6 ). the interrupt flags must be cleared in software. each alarm can independently be assigned to either the irq pin or the wdo pin by configuring the almxpin bits. refer to section 5.8 ?interrupt outputs? for details. the alarm interrupt output is available while operating from the backup power supply, regardless of the output pin assignments. all time and date values are stored in the registers as binary-coded decimal (bcd) values. table 5-5: alarm 0 masks table 5-6: alarm 1 masks note: throughout this section, references to the register and bit names for the alarm modules are referred to generically by the use of x in place of the specific module number. thus, almxsec might refer to the seconds register for alarm 0 or alarm 1. alm0msk<2:0> alarm 0 asserts on match of 000 seconds 001 minutes 010 hours 011 day of week 100 date 101 reserved 110 reserved 111 seconds, minutes, hours, day of week, date, and month alm1msk<2:0> alarm 1 asserts on match of 000 seconds 001 minutes 010 hours 011 day of week 100 date 101 hundredth of seconds 110 reserved 111 seconds, minutes, hours, day of week, and date note 1: the alarm interrupt flags must be cleared by the user. 2: loading invalid values into the alarm reg- isters will result in undefined operation. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 23 mcp795w1x/mcp795w2x figure 5-7: alarm block diagram 5.4.1 configuring the alarm in order to configure the alarm modules, the following steps need to be performed: 1. load the timekeeping registers and enable the oscillator. 2. configure the almxmsk<2:0> bits to select the desired alarm mask. 3. set or clear the almxpin bit according to the desired output pin assignment. 4. ensure the almxif flag is cleared. 5. based on the selected alarm mask, load the alarm match value into the appropriate register(s). 6. enable the alarm module by setting the almxen bit. irq rtcsec rtcmin rtchour rtcwkday rtcdate rtcmth timekeeping registers alarm 0 registers alarm 0 mask alarm 1 mask comparator comparator interrupt set alm0if set alm1if alm0msk<2:0> alm1msk<2:0> rtchsec alm0min alm0hour alm0wkday alm0date alm0mth alm0sec alarm 1 registers alm1sec alm1min alm1hour alm1wkday alm1date alm1hsec wdo output logic downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 24 ? 2011-2016 microchip technology inc. register 5-9: alm1hsec: alarm 1 hundre dths of seconds value register (address 0x12) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 hsecten3 hsecten2 hsecten1 hsecten0 hsecone3 hsecone2 hsecone1 hsecone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-4 hsecten<3:0>: binary-coded decimal value of hundredth of seconds tens digit contains a value from 0 to 9 bit 3-0 hsecone<3:0>: binary-coded decimal value of hundredth of seconds ones digit contains a value from 0 to 9 note 1: hundredth of seconds matching is only available on alarm 1. register 5-10: almxsec: alarm 0/1 seconds value register (addresses 0x0c/0x13) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 secten<2:0>: binary-coded decimal value of seconds tens digit contains a value from 0 to 5 bit 3-0 secone<3:0>: binary-coded decimal value of seconds ones digit contains a value from 0 to 9 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 25 mcp795w1x/mcp795w2x register 5-11: almxmin: alarm 0/1 minu tes value register (addresses 0x0d/0x14) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 minten<2:0>: binary-coded decimal value of minutes tens digit contains a value from 0 to 5 bit 3-0 minone<3:0>: binary-coded decimal value of minutes ones digit contains a value from 0 to 9 register 5-12: almxhour: alarm 0/1 hour s value register (addresses 0x0e/0x15) u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 12/24 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown i f 12/ 24 = 1 (12-hour format): bit 7 unimplemented: read as 0 bit 6 12/24 : 12 or 24 hour time format bit ( 1 ) 1 = 12-hour format 0 = 24-hour format bit 5 am /pm: am/pm indicator bit 1 = pm 0 = am bit 4 hrten0: binary-coded decimal value of hours tens digit contains a value from 0 to 1 bit 3-0 hrone<3:0>: binary-coded decimal value of hours ones digit contains a value from 0 to 9 if 12/ 24 = 0 (24-hour format): bit 7 unimplemented: read as 0 bit 6 12/24 : 12 or 24 hour time format bit ( 1 ) 1 = 12-hour format 0 = 24-hour format bit 5-4 hrten<1:0>: binary-coded decimal value of hours tens digit contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary-coded decimal value of hours ones digit contains a value from 0 to 9 note 1: this bit is read-only and reflects the value of the 12/24 bit in the rtchour register. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 26 ? 2011-2016 microchip technology inc. register 5-13: almxwkday: alarm 0/1 weekday value register (addresses 0x0f/0x16) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 almxpin almxmsk2 almxmsk1 almxmsk0 almxif wkday2 wkday1 wkday0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 almxpin: alarm interrupt output pin assignment bit 1 = alarm output is assigned to wdo 0 = alarm output is assigned to irq bit 6-4 almxmsk<2:0>: alarm mask bits 000 = seconds match 001 = minutes match 010 = hours match (logic takes into account 12-/24-hour operation) 011 = day of week match 100 = date match 101 = hundredth of seconds ( 1 ) 110 = reserved; do not use 111 = seconds, minutes, hour, day of week, date and month ( 2 ) bit 3 almxif: alarm interrupt flag bit ( 3 ) 1 = alarm match occurred (must be cleared in software) 0 = alarm match did not occur bit 2-0 wkday<2:0>: binary-coded decimal value of day bits contains a value from 1 to 7. the representation is user-defined. note 1: hundredth of seconds matching is available on alarm 1 only. this setting is reserved on alarm 0. 2: month matching is available on alarm 0 only. 3: the almxif bit can be cleared by writing a 0 . once cleared, the almxif bit cannot be written to a 1 in software. register 5-14: almxdate: alarm 0/1 date value register (addresses 0x10/0x17) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 dateten<1:0>: binary-coded decimal value of dates tens digit contains a value from 0 to 3 bit 3-0 dateone<3:0>: binary-coded decimal value of dates ones digit contains a value from 0 to 9 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 27 mcp795w1x/mcp795w2x table 5-7: summary of regist ers associated with alarms register 5-15: alm0mth: alarm 0 mo nth value register (address 0x11) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 mthten0 mthone3 mthone2 mthone1 mthone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-5 unimplemented: read as 0 bit 4 mthten0: binary-coded decimal value of months tens digit contains a value of 0 or 1 bit 3-0 mthone<3:0>: binary-coded decimal value of months ones digit contains a value from 0 to 9 note 1: month matching is only available on alarm 0. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page alm0sec secten2 secten1 secten0 secone3 secone2 secone1 secone0 24 alm0min minten2 minten1 minten0 minone3 minone2 minone1 minone0 25 alm0hour 1 2 / 2 4 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 25 alm0wkday alm0pin alm0msk2 alm0msk1 alm0msk0 alm0if wkday2 wkday1 wkday0 26 alm0date dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 26 alm0mth mthten0 mthone3 mthone2 mthone1 mthone0 27 alm1hsec hsecten3 hsecten2 hsecten1 hsecten0 hsecone3 hsecone2 hsecone1 hsecone0 24 alm1sec secten2 secten1 secten0 secone3 secone2 secone1 secone0 24 alm1min minten2 minten1 minten0 minone3 minone2 minone1 minone0 25 alm1hour 1 2 / 2 4 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 25 alm1wkday alm1pin alm1msk2 alm1msk1 alm1msk0 alm1if wkday2 wkday1 wkday0 26 alm1date dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 26 control out sqwen alm1en alm0en extosc crstrim sqwfs1 sqwfs0 35 legend: = unimplemented location, read as 0 . shaded cells are not used by alarms. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 28 ? 2011-2016 microchip technology inc. 5.5 watchdog timer the mcp795wxx features a watchdog timer (wdt) module that can be used to enhance the robustness of an application. the wdt continuously counts up toward a specified time-out period. during normal operation, the application would clear the wdt before it times out. however, if a failure occurs, the application would not clear the wdt, causing it to time out, set the wdtif interrupt flag, and assert the wdo pin low for a specified pulse width. this can then be used to reset the application and recover from the failure. the wdt time-out period can be configured by setting the wdtps<3:0> bits according to ta b l e 5 - 8 . setting the wdtdlyen bit will enable a 64-second nominal start-up delay. with this enabled, every time the wdt is restarted or cleared, the wdt will wait for 64 seconds before starting the time-out period. once the wdtif flag has been set due to a wdt time-out, the wdtif flag must be cleared to restart the wdt. the wdt is driven by the oscillator. if the oscillator is not running, then the wdt time-out will not occur. table 5-8: watchdog timer time-out period selection 5.5.1 watchdog timer interrupt output when the wdt times out, the wdtif interrupt flag gets set and the wdo pin is asserted low for a short pulse. the width of the pulse is determined by the wdtpws bit according to ta bl e 5 - 9 . the wdt interrupt output will operate regardless of whether or not either alarm module interrupt output is assigned to the wdo pin. see section 5.8.2 ?wdo interrupt output? for additional details. table 5-9: watchdog timer output pulse width selection 5.5.2 configuring the watchdog timer in order to configure the wdt module, the following steps need to be performed: 1. enable the oscillator. 2. configure the wdtps<3:0> bits to select the desired time-out period. 3. if desired, set the wdtdlyen bit to enable the 64-second start-up delay. 4. configure the wdtpws bit to select the desired output pulse width. 5. ensure the wdtif flag is cleared. 6. enable the wdt module by setting the wdten bit. 5.5.3 clearing the watchdog timer the wdt must be cleared before the time-out period occurs in order to prevent it from timing out. the wdt can be cleared using any of the following methods: 1. executing a clrwdt instruction. 2. toggling the evhs pin with the evwdten bit set. 3. disabling/re-enabling the wdt module. 4. clearing the wdtif flag after it has been set. note 1: the wdt time-out period should only be changed while the wdt module is disabled. wdtps<3:0> time-out period ( f osc cycles) nominal time-out period ( 1 ) 0000 32 cycles 977 s 0001 512 cycles 15.6 ms 0010 2,048 cycles 62.5 ms 0011 4,096 cycles 125 ms 0100 32,768 cycles 1 second 0101 524,288 cycles 16 seconds 0110 1,048,576 cycles 32 seconds 0111 2,097,152 cycles 64 seconds 1xxx reserved note 1: nominal period assumes f osc is 32.768 khz. wdtpws pulse width ( f osc cycles) nominal pulse width ( 1 ) 0 4 cycles 122 s 1 4,096 cycles 125 ms note 1: nominal period assumes f osc is 32.768 khz. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 29 mcp795w1x/mcp795w2x figure 5-8: watchdog timer block diagram postscaler 2,097,152 1,048,576 524,288 32 mcp795wxx mux wdtps<3:0> 01110110 0101 0100 0011 0010 0001 0000 32,768 4,096 2,048 512 wdo output pulse gen wdtpws oscillator block f osc wdt counter 64-sec start-up delay 01 wdtdlyen wdten evhs set wdtif reset reset clrwdt clear wdt evhs block wdt time out wdtif downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 30 ? 2011-2016 microchip technology inc. register 5-16: wdtcon: watchdog time r control register (address 0x0a) table 5-10: summary of registers associated with watchdog timer r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wdten wdtif wdtdlyen wdtpws wdtps3 wdtps2 wdtps1 wdtps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 wdten: watchdog timer enable bit ( 1 ) 1 = watchdog timer enabled 0 = watchdog timer disabled bit 6 wdtif: watchdog timer interrupt flag bit 1 = watchdog timer has timed out (must be cleared in software) 0 = watchdog timer has not timed out bit 5 wdtdlyen: watchdog timer delay enable bit 1 = enable 2,097,152 oscillator cycle (64-second nominal) start-up delay before time-out period begins after wdt is reset 0 = disable start-up delay bit 4 wdtpws: watchdog timer output pulse width select bit 1 = 4,096 oscillator cycles (125 ms nominal) 0 = 4 oscillator cycles (122 s nominal) bit 3-0 wdtps<3:0>: watchdog timer time-out period select bits 0000 = 32 oscillator cycles (977 s nominal) 0001 = 512 oscillator cycles (15.6 ms nominal) 0010 = 2,048 oscillator cycles (62.5 ms nominal) 0011 = 4,096 oscillator cycles (125 ms nominal) 0100 = 32,768 oscillator cycles (1 second nominal) 0101 = 524,288 oscillator cycles (16 second nominal) 0110 = 1,048,576 oscillator cycles (32 second nominal) 0111 = 2,097,152 oscillator cycles (64 second nominal) 1xxx = reserved; do not use note 1: the wdten bit is automatically cleared when operating from the backup power su pply. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page wdtcon wdten wdtif wdtdlyen wdtpws wdtps3 wdtps2 wdtps1 wdtps0 30 legend: = unimplemented location, read as 0 . shaded cells are not used in watchdog timer configuration. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 31 mcp795w1x/mcp795w2x 5.6 event detection the mcp795wxx features two separate event detection modules: a high-speed event detect and a low-speed event detect. the high-speed event detect can be used to detect signal preambles, while the low-speed event detect is meant for debouncing mechanical switches. the event detection modules are not available while operating from the backup power supply. 5.6.1 high-speed event detect the high-speed event detect module is designed to detect a series of digital transitions (both low-to-high and high-to-low) on the evhs input, and then generate an interrupt. the number of transitions required to occur is determined by the evhcs<1:0> bits as shown in tab le 5 - 11 . once the specified number of transitions have occurred, the evhif interrupt flag is set and the irq pin is asserted low. the high-speed event detect has a time-out period of 8,192 oscillator cycles (250 ms nominal assuming a 32.768 khz clock frequency). if the total number of transitions specified by the evhcs<1:0> bits do not occur within the time-out period, then the transition count will be reset and count- ing will start over ( figure 5-10 ). the time-out period is driven by the oscillator. if the oscillator is not running, then the time-out will not occur. table 5-11: high-speed event count selection 5.6.1.1 clearing the wdt using evhs the evhs input can also be used to clear the watchdog timer on both low-to-high and high-to-low transitions by setting the evwdten bit. note that when this bit is set, the high-speed event detect module is disabled and the evhen bit is ignored. figure 5-9: high-speed e vent detect block diagram figure 5-10: high-speed even t detect waveform example evhcs<1:0> required transitions for interrupt 00 1 01 4 10 16 11 32 postscaler evhs mcp795wxx 1:8,192 reset set evhif evhen irq interrupt output logic prescaler 1, 4, 16, 32 and edge detect reset evhcs<1:0> s r q 01 evwdten clear wdt oscillator block f osc edge detected time out occurred evhs evhif bit < 8,192 osc. cycles 8,192 osc. cycles 1234 n - 1 ( 1 ) 12345 n ( 1 ) note 1: n refers to the required number of transitions as determined by the evhcs<1:0> bits. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 32 ? 2011-2016 microchip technology inc. 5.6.1.2 configuring high-speed event detect in order to configure the high-speed event detect module, the following steps need to be performed: 1. enable the oscillator. 2. configure the evhcs<1:0> bits to select the desired number of transitions. 3. ensure the evwdten bit is cleared. 4. ensure the evhif flag is cleared. 5. enable the high-speed event detect module by setting the evhen bit. 5.6.2 low-speed event detect the low-speed event detect module is designed to interface directly with mechanical switches to provide a debounced signal. the debounce period is selectable through the evlps bit as shown in ta bl e 5 - 1 2 . low speed events occur when the evls input toggles and remains stable for the selected debounce period. after a transition on the evls input, the mcp795wxx will begin counting the debounce period. either a high-to-low or a low-to-high transition will initiate counting. once the debounce period has expired, the evlif flag is set and the irq pin is asserted low ( figure 5-12 ). if the evls input returns to its original level before the debounce period expires, then counting is aborted and the evlif flag will not be set. the low-speed event detect module is driven by the oscillator. if the oscillator is not running, then the debounce period will not expire and the evlif flag will not be set. table 5-12: low-speed event debounce period selection 5.6.2.1 configuring low-speed event detect in order to configure the low-speed event detect module, the following steps need to be performed: 1. enable the oscillator. 2. configure the evlps bit to select the desired debounce period. 3. ensure the evlif flag is cleared. 4. enable the low-speed event detect module by setting the evlen bit. figure 5-11: low-speed event detect block diagram figure 5-12: low-speed event detect waveform example evlps debounce period ( f osc cycles) nominal debounce period ( 1 ) 0 1,024 cycles 31.25 ms 1 16,384 cycles 500 ms note 1: nominal period assumes f osc is 32.768 khz. postscaler evls 01 evlps mcp795wxx 1:1,024 31.25 ms 500 ms postscaler 1:16 reset dqck set evlif irq interrupt output logic oscillator block f osc evls matches latched state evlen latch new evls state evls evlif bit debounce period ( 1 ) note 1: the debounce period is determined by the evlps bit. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 33 mcp795w1x/mcp795w2x register 5-17: evdtcon: event detect control register (address 0x0b) table 5-13: summary of registers associated with event detection r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 evhif evlif evhen evlen evwdten evlps evhcs1 evhcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 evhif: high-speed event detect interrupt flag bit 1 = high-speed event detection occurred (must be cleared in software) 0 = high-speed event detection did not occur bit 6 evlif: low-speed event detect interrupt flag bit 1 = low-speed event detection occurred (must be cleared in software) 0 = low-speed event detection did not occur bit 5 evhen: high-speed event detect module enable bit if evwdten = 0 : 1 = high-speed event detect enabled 0 = high-speed event detect disabled if evwdten = 1 : unused. bit 4 evlen: low-speed event detect module enable bit 1 = low-speed event detect enabled 0 = low-speed event detect disabled bit 3 evwdten: evhs input wdt clear enable bit 1 = enable watchdog timer clear on evhs input transition. disables high-speed event detect module. 0 = disable evhs input clearing watchdog timer. bit 2 evlps: low-speed event detect debounce period select bit 1 = 16,384 oscillator cycles (500 ms nominal) 0 = 1,024 oscillator cycles (31.25 ms nominal) bit 1-0 evhcs<1:0>: high-speed event detect transition count select bits selects how many transitions must occur on the evhs input before an interrupt is triggered 00 = 1 transition 01 = 4 transitions 10 = 16 transitions 11 = 32 transitions name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page evdtcon evhif evlif evhen evlen evwdten evlps evhcs1 evhcs0 33 legend: = unimplemented location, read as 0 . shaded cells are not used in event detect configuration. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 34 ? 2011-2016 microchip technology inc. 5.7 clock output the mcp795wxx features square wave clock output and general purpose output modes through the clkout pin. if the sqwen bit is set, then clkout operates in square wave clock output mode. otherwise, clkout operates in general purpose output mode ( ta b l e 5 - 1 4 ). the clkout pin is disabled while operating from the backup power supply. table 5-14: clkout output modes figure 5-13: clkout output block diagram 5.7.1 square wave output mode the mcp795wxx can be configured to generate a square wave clock signal on clkout. the input clock frequency, f osc , is divided according to the sqwfs<1:0> bits as shown in ta bl e 5 - 15 . the square wave output is not available when operating from the backup power supply. table 5-15: clock output rates 5.7.2 general purpose output mode if the square wave clock output is disabled, clkout acts as a general purpose output. the output logic level is controlled by the out bit. the general purpose output is not available when operating from the backup power supply. sqwen out mode 00 logic low output 01 logic high output 1x square wave clock output x2 x1 st oscillator extosc postscaler mux 32.768 khz 8.192 khz 4.096 khz 1 hz sqwfs<1:0> 1110 01 00 digital trim 1 0 crstrim clkout 0 1 sqwen out mcp795wxx note: all of the clock output rates are affected by digital trimming except for the 1:1 postscaler value (sqwfs<1:0> = 00 ). sqwfs<1:0> postscaler nominal frequency 00 1:1 32.768 khz 01 1:4 8.192 khz 10 1:8 4.096 khz 11 1:32,768 1 hz note 1: nominal frequency assumes f osc is 32.768 khz. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 35 mcp795w1x/mcp795w2x table 5-16: summary of registers associ ated with clock ou tput configuration register 5-18: control: rtcc co ntrol register (address 0x08) r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 out sqwen alm1en alm0en extosc crstrim sqwfs1 sqwfs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 out: logic level for general purpose output square wave clock output mode (sqwen = 1 ): unused. general purpose output mode (sqwen = 0 ): 1 = clkout signal level is logic high 0 = clkout signal level is logic low bit 6 sqwen: square wave output enable bit 1 = enable square wave clock output mode 0 = disable square wave clock output mode bit 5 alm1en: alarm 1 module enable bit 1 = alarm 1 enabled 0 = alarm 1 disabled bit 4 alm0en: alarm 0 module enable bit 1 = alarm 0 enabled 0 = alarm 0 disabled bit 3 extosc: external oscillator input bit 1 = enable x1 pin to be driven by external 32.768 khz source 0 = disable external 32.768 khz input bit 2 crstrim: coarse trim mode enable bit coarse trim mode results in the mcp795wxx applying digital trimming every second. 1 = enable coarse trim mode. if sqwen = 1 , clkout will output trimmed 1 hz ( 1 ) nominal clock signal. 0 = disable coarse trim mode see section 5.9 ?digital trimming? for details bit 1-0 sqwfs<1:0>: square wave clock output frequency select bits if sqwen = 1 and crstrim = 0 : selects frequency of clock output on clkout 00 = 1 hz ( 1 ) 01 = 4.096 khz ( 1 ) 10 = 8.192 khz ( 1 ) 11 = 32.768 khz if sqwen = 0 or crstrim = 1 : unused. note 1: the 8.192 khz, 4.096 khz, and 1 hz square wave clock output frequencies are affected by digital trimming. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page control out sqwen alm1en alm0en extosc crstrim sqwfs1 sqwfs0 35 legend: = unimplemented location, read as 0 . shaded cells are not used in clock output configuration. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 36 ? 2011-2016 microchip technology inc. 5.8 interrupt outputs the mcp795wxx features interrupt outputs for the alarm and event detect modules. the alarm interrupt output can be assigned to either the irq pin or the wdo pin, based on the setting of the almxpin bit for each alarm module. setting almxpin to a 1 assigns the associated alarm module to the wdo pin and clear- ing almxpin to a 0 assigns the module to the irq pin. the event detect modules are always assigned to the irq pin. both the irq and the wdo pins are active-low. 5.8.1 irq interrupt output the interrupt outputs of modules that are enabled and assigned to the irq pin are ord together. if any of the interrupt flags are set, then the irq pin will assert low. in order to deassert the irq pin, all of the assigned interrupt flags must be cleared or the modules must be disabled. the irq interrupt output is available when operating from the backup power supply. figure 5-14: irq output block diagram 5.8.2 wdo interrupt output if an alarm module is enabled and assigned to the wdo pin, then when the alarm triggers and the interrupt flag, almxif, is set, the wdo pin will be asserted low for 8 oscillator cycles (244 s nominal assuming a 32.768 khz clock frequency) and then deasserted again. the almxif flag must then be cleared to rearm the wdo output and allow it to trigger again upon the next alarm interrupt. if both alarm modules are enabled and assigned to the wdo pin, then either module can trigger the wdo output pulse. however, both almxif flags must be cleared for the wdo output to trigger upon the next alarm interrupt. the watchdog timer output on the wdo pin is independent of the alarm modules and will occur regardless of the state of the alarm modules and their interrupt flags. the wdo interrupt output is available when operating from the backup power supply. figure 5-15: wdo output block diagram table 5-17: summary of registers associated with interrupt output configuration evlif evlen evhif evhen irq alm0if alm0en alm0pin alm1if alm1en alm1pin pulse gen wdo alm0if alm0en alm0pin alm1if alm1en alm1pin wdt output name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page evdtcon evhif evlif evhen evlen evwdten evlps evhcs1 evhcs0 tbd alm0wkday alm0pin alm0msk2 alm0msk1 alm0msk0 alm0if wkday2 wkday1 wkday0 26 alm1wkday alm1pin alm1msk2 alm1msk1 alm1msk0 alm1if wkday2 wkday1 wkday0 26 control out sqwen alm1en alm0en extosc crstrim sqwfs1 sqwfs0 35 legend: = unimplemented location, read as 0 . shaded cells are not used in interrupt output configuration. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 37 mcp795w1x/mcp795w2x 5.9 digital trimming the mcp795wxx features digital trimming to correct for inaccuracies of the external crystal or clock source, up to roughly 259 ppm when crstrim = 0 . in addition to compensating for intrinsic inaccuracies in the clock, this feature can also be used to correct for error due to temperature variation. this can enable the user to achieve high levels of accuracy across a wide temperature operating range. digital trimming consists of the mcp795wxx periodically adding or subtracting clock cycles, resulting in small adjustments in the internal timing. the adjustment occurs once per minute when crstrim = 0 . the trimsign bit specifies whether to add cycles or to subtract them. the trimval<7:0> bits are used to specify by how many clock cycles to adjust. each step in the trimval<7:0> value equates to adding or subtracting two clock pulses to or from the 32.768 khz clock signal. this results in a correction of roughly 1.017 ppm per step when crstrim = 0 . setting trimval<7:0> to 0x00 disables digital trimming. digital trimming also occurs while operating off the backup supply. register 5-19: osctrim: oscillator digital trim register (address 0x09) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trimval7 trimval6 trimval5 trimval4 trimval3 trimval2 trimval1 trimval0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-0 trimval<7:0>: oscillator trim value bits when crstrim = 0 : 11111111 = add or subtract 510 clock cycles every minute 11111110 = add or subtract 508 clock cycles every minute 00000010 = add or subtract 4 clock cycles every minute 00000001 = add or subtract 2 clock cycles every minute 00000000 = disable digital trimming when crstrim = 1 : 11111111 = add or subtract 510 clock cycles every second 11111110 = add or subtract 508 clock cycles every second 00000010 = add or subtract 4 clock cycles every second 00000001 = add or subtract 2 clock cycles every second 00000000 = disable digital trimming downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 38 ? 2011-2016 microchip technology inc. 5.9.1 calibration in order to perform calibration, the number of error clock pulses per minute must be found and the corresponding trim value must be loaded into trimval<7:0>. there are two methods for determining the trim value. the first method involves measuring an output frequency directly and calculating the deviation from ideal. the second method involves observing the number of seconds gained or lost over a period of time. once the osctrim register has been loaded, digital trimming will automatically occur every minute (crstrim = 0). 5.9.1.1 calibration by measuring frequency to calibrate the mcp795wxx by measuring the output frequency, perform the following steps: 1. enable the crystal oscillator or external clock input by setting the st bit or extosc bit, respectively. 2. ensure trimval<7:0> is reset to 0x00. 3. select an output frequency by setting sqwfs<1:0>. 4. set sqwen to enable the square wave output. 5. measure the resulting output frequency using a calibrated measurement tool, such as a frequency counter. 6. calculate the number of error clocks per minute (see equation 5-3 ). equation 5-3: calculating trim value from measured frequency if the number of error clocks per minute is negative, then the oscillator is faster than ideal and the trimsign bit must be cleared. if the number of error clocks per minute is positive, then the oscillator is slower than ideal and the trimsign bit must be set. 7. load the correct value into trimval<7:0>. 5.9.1.2 calibration by observing time deviation to calibrate the mcp795wxx by observing the deviation over time, perform the following steps: 1. ensure trimval<7:0> is reset to 0x00. 2. load the timekeeping registers to synchronize the mcp795wxx with a known-accurate reference time. 3. enable the crystal oscillator or external clock input by setting the st bit or extosc bit, respectively. 4. observe how many seconds are gained or lost over a period of time (larger time periods offer more accuracy). 5. calculate the ppm deviation (see equation 5-4 ). equation 5-4: calculating error ppm if the mcp795wxx has gained time relative to the reference clock, then the oscillator is faster than ideal and the trimsign bit must be cleared. if the mcp795wxx has lost time relative to the reference clock, then the oscillator is slower than ideal and the trimsign bit must be set. 6. calculate the trim value (see equation 5-5 ). equation 5-5: calculating trim value from error ppm 7. load the correct value into trimval<7:0>. note: using a lower output frequency and/or averaging the measured frequency over a number of clock pulses will reduce the effects of jitter and improve accuracy. trimval<7:0> f ideal f meas ? ?? 32768 f ideal ------------------ -60 ?? 2 --------------------------------------------------------------------------------- = where: f ideal ideal frequency based on sqwfs<1:0> = f meas measured frequency = note 1: choosing a longer time period for observing deviation will improve accuracy. 2: large temperature variations during the observation period can skew results. ppm secdeviation expectedsec ----------------------------------- 1 0 0 0 0 0 0 ? = where: expectedsec number of seconds in chosen period = secdeviation number of seconds gained or lost = trimval<7:0> ppm 32768 60 ?? 1000000 2 ? ------------------------------------------ - = downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 39 mcp795w1x/mcp795w2x 5.9.2 coarse trim mode when crstrim = 1 , coarse trim mode is enabled. while in this mode, the mcp795wxx will apply trimming every second. if sqwen is set, the clkout pin will output a trimmed 1 hz nominal clock signal. because trimming is applied every second rather than every minute, each step of the trimval<7:0> value has a larger effect on the resulting time deviation and output clock frequency. by monitoring the clkout output frequency while in this mode, the user can easily observe the trimval<7:0> value affecting the clock timing. table 5-18: summary of registers associated with digital trimming note 1: the 1 hz coarse trim mode square wave output is not available while operating from the backup power supply. 2: with coarse trim mode enabled, the trimval<7:0> value has a larger effect on timing. leaving the mode enabled during normal operation will likely result in inaccurate time. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page rtchour trimsign 12/24 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 19 control out sqwen alm1en alm0en extosc crstrim sqwfs1 sqwfs0 35 osctrim trimval7 trimval6 trimval5 trimval4 trimval3 trimval2 trimval1 t rimval0 37 legend: = unimplemented location, read as 0 . shaded cells are not us ed by digital trimming.l downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 40 ? 2011-2016 microchip technology inc. 5.10 battery backup the mcp795wxx features a backup power supply input (v bat ) that can be used to provide power to the timekeeping circuitry, rtcc registers, and sram while primary power is unavailable. the mcp795wxx will automatically switch to backup power when v cc falls below v trip , and back to v cc when it is above v trip . the vbaten bit must be set to enable the v bat input. the following functionality is maintained while operating on backup power: timekeeping alarms alarm outputs digital trimming rtcc register and sram contents the following features are not available while operating on backup power: spi communication watchdog timer event detect square wave clock output general purpose output 5.10.1 power-fail timestamp the mcp795wxx includes a power-fail timestamp module that stores the minutes, hours, date, and month when primary power is lost and when it is restored ( figure 5-16 ). the pwrfail bit is also set to indicate that a power failure occurred. to utilize the power-fail timestamp feature, a backup power supply must be available with the v bat input enabled, and the oscillator should also be running to ensure accurate functionality. 5.10.1.1 configuring battery backup in order to configure the battery backup feature, the following steps need to be performed: 1. enable the oscillator. 2. wait for the oscrun bit to be set, indicating the oscillator has started. 3. enable battery backup by setting the vbaten bit. figure 5-16: power-fa il timestamp timing note: the watchdog timer is automatically disabled when primary power is lost and is not automatically re-enabled when power is restored. note: throughout this section, references to the register and bit names for the power-fail timestamp module are referred to generically by the use of x in place of the specific module name. thus, pwrxxmin might refer to the minutes register for power-down or power-up. note 1: the pwrfail bit must be cleared to log new timestamp data. this is to ensure previous timestamp data is not lost. 2: clearing the pwrfail bit will clear all timestamp registers. power-down power-up timestamp timestamp v cc v trip downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 41 mcp795w1x/mcp795w2x register 5-20: pwrxxmin: power-down/power-up timestamp minutes value register (addresses 0x18/0x1c) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7 unimplemented: read as 0 bit 6-4 minten<2:0>: binary-coded decimal value of minutes tens digit contains a value from 0 to 5 bit 3-0 minone<3:0>: binary-coded decimal value of minutes ones digit contains a value from 0 to 9 register 5-21: pwrxxhour: power-down/power-up timestamp hours value register (addresses 0x19/0x1d) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 12/24 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown if 12/ 24 = 1 (12-hour format): bit 7 unimplemented: read as 0 bit 6 12/24 : 12 or 24 hour time format bit 1 = 12-hour format 0 = 24-hour format bit 5 am /pm: am/pm indicator bit 1 = pm 0 = am bit 4 hrten0: binary-coded decimal value of hours tens digit contains a value from 0 to 1 bit 3-0 hrone<3:0>: binary-coded decimal value of hours ones digit contains a value from 0 to 9 if 12/ 24 = 0 (24-hour format): bit 7 unimplemented: read as 0 bit 6 12/24 : 12 or 24 hour time format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 hrten<1:0>: binary-coded decimal value of hours tens digit contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary-coded decimal value of hours ones digit contains a value from 0 to 9 downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 42 ? 2011-2016 microchip technology inc. table 5-19: summary of registers associated with battery backup register 5-22: pwrxxdate: power-down/power-up timestamp date value register (addresses 0x1a/0x1e) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-6 unimplemented: read as 0 bit 5-4 dateten<1:0>: binary-coded decimal value of dates tens digit contains a value from 0 to 3 bit 3-0 dateone<3:0>: binary-coded decimal value of dates ones digit contains a value from 0 to 9 register 5-23: pwrxxmth: power-down/power-up timestamp month value register (addresses 0x1b/0x1f) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wkday2 wkday1 wkday0 mthten0 mthone3 mthone2 mthone1 mthone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-5 wkday<2:0>: binary-coded decimal value of day bits contains a value from 1 to 7. the representation is user-defined. bit 4 mthten0: binary-coded decimal value of months ones digit contains a value of 0 or 1 bit 3-0 mthone<3:0>: binary-coded decimal value of months ones digit contains a value from 0 to 9 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page rtcwkday oscrun pwrfail vbaten wkday2 wkday1 wkday0 20 pwrdnmin minten2 minten1 minten0 minone3 minone2 minone1 minone0 41 pwrdnhour 1 2 / 2 4 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 41 pwrdndate dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 42 pwrdnmth wkday2 wkday1 wkday0 mthten0 mthone3 mthone2 mthone1 mthone0 42 pwrupmin minten2 minten1 minten0 minone3 minone2 minone1 minone0 41 pwruphour 1 2 / 2 4 am /pm hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 41 pwrupdate dateten1 dateten0 dateone3 dateone2 dateone1 dateone0 42 pwrupmth wkday2 wkday1 wkday0 mthten0 mthone3 mthone2 mthone1 mthone0 42 legend: = unimplemented location, read as 0 . shaded cells are not used with battery backup. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 43 mcp795w1x/mcp795w2x 6.0 on-board memory the mcp795w2x has 2 kbits (256 bytes) of eeprom, while the mcp795w1x has 1 kbit (128 bytes) of eeprom. in addition, the devices have 16 bytes of protected eeprom for storing crucial information, and 64 bytes of sram for general purpose usage. the sram is retained when the primary power supply is removed if a backup supply is present and enabled. since the eeprom is nonvolatile, it does not require a supply for data retention. although the sram is a separate block from the rtcc registers, they are accessed using the same instructions, read and write . the eeprom is accessed using the eeread and eewrite instructions, and the protected eeprom is accessed using the idread and idwrite instructions. rtcc and sram can be accessed for reads or writes immediately after starting an eeprom write cycle. 6.1 sram/rtcc registers the rtcc registers are located at addresses 0x00 to 0x1f, and the sram is located at addresses 0x20 to 0x5f. the sram can be accessed while the rtcc registers are being internally updated. the sram is not initialized by a power-on reset (por). neither the rtcc registers nor the sram can be accessed when the device is operating off the backup power supply. 6.1.1 sram/rtcc register write sequence the device is selected by pulling cs low. the 8-bit write instruction is transmitted to the mcp795wxx followed by an 8-bit address. next, the data to be written is transmitted. there is no limit to the number of bytes that can be written in a single command. however, because the rtcc registers and sram are separate blocks, writing past the end of each block will cause the internal address pointer to roll over to the beginning of the same block. specifically, the address pointer will roll over from 0x1f to 0x00, and from 0x5f to 0x20. each data byte is latched into memory as it is received. once all data bytes have been transmitted, cs is driven high to end the operation ( figure 6-1 ). 6.1.2 sram/rtcc register read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the mcp795wxx followed by an 8-bit address. after the read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. the internal address pointer automatically increments to the next higher address after each byte of data is shifted out. the address pointer allows the entire memory block to be serially read during one operation. the read operation is terminated by driving cs high ( figure 6-2 ). because the rtcc registers and sram are separate blocks, reading past the end of each block will cause the address pointer to roll over to the beginning of the same block. specifically, the address pointer will roll over from 0x1f to 0x00, and from 0x5f to 0x20. figure 6-1: sram/rtcc write sequence si cs 91011 00 0 1 0 0 01 76543210 data byte 1 sck 0 234567 18 si cs 33 34 35 38 39 76543210 data byte n sck 24 26 27 28 29 30 31 25 32 76543210 data byte 3 76543210 data byte 2 36 37 instruction address byte a 7 a 6 a 5 a 4 a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23 downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 44 ? 2011-2016 microchip technology inc. figure 6-2: sram/rtcc read sequence 6.1.3 clear sram instruction the clrram instruction can be used to quickly clear the contents of sram to 0x00. the rtcc registers are not affected. the device is selected by pulling cs low. the 8-bit clrram instruction is transmitted to the mcp795wxx followed by an 8-bit dummy data byte. cs is driven high to end the operation ( figure 6-3 ). the value of the data byte is ignored. figure 6-3: clear sram sequence so si sck cs 0 234567891011 1 01 0 1 0 0 01 a 7 a 6 a 5 a 4 a 1 a 0 76543210 data out high-impedance a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction so si cs 91011 12131415 10 0 1 0 1 00 7654 210 instruction dummy data byte high-impedance sck 0 234567 18 3 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 45 mcp795w1x/mcp795w2x 6.2 status register the status register contains the bp<1:0>, wel and wip bits. the status register is accessed using the srread and srwrite instructions. the block protection (bp<1:0>) bits are used to set the block write protection for the eeprom array according to tab l e 6 - 1 . these bits are set by the user issuing the srwrite instruction. these bits are nonvolatile. the write enable latch (wel) bit indicates the status of the write enable latch. when set to a 1 , the latch allows writes to the nonvolatile memory, when set to a 0 , the latch prohibits writes to the nonvolatile memory. the state of this bit can be updated via the eewren or eewrdi instructions. this bit is read-only. the wip bit indicates whether the mcp795wxx is busy with a nonvolatile memory write operation. when set to a 1 , a write is in progress. when set to a 0 , no write is in progress. this bit is read-only. table 6-1: block protection register 6-1: status: eeprom write protection register 6.2.1 status register write sequence the write status register instruction ( srwrite ) allows the user to write to the nonvolatile bits in the status register. prior to any attempt to write data to the status register, the write enable latch must be set by issuing the eewren instruction. this is done by setting cs low and then clocking out the proper instruction into the mcp795wxx. after all eight bits of the instruction are transmitted, cs must be driven high to set the write enable latch. if the write operation is initiated immediately after the eewren instruction without cs driven high, data will not be written to the array since the write enable latch was not properly set. the device is selected by pulling cs low. the 8-bit srwrite instruction is transmitted to the mcp795wxx followed by the 8-bit data byte. cs is driven high to end the operation and initiate the nonvolatile write cycle ( figure 6-4 ). bp1 bp0 array addresses write-protected 00 none 01 upper 1/4 60h-7fh (mcp795w1x) c0h-ffh (mcp795w2x) 10 upper 1/2 40h-7fh (mcp795w1x) 80h-ffh (mcp795w2x) 11 all u-0 u-0 u-0 u-0 r/w r/w r-0 r-0 bp1 bp0 wel wip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is clear x = bit is unknown bit 7-4 unimplemented: read as 0 bit 3-2 bp<1:0>: eeprom array block protection bits selects which eeprom region is write-protected 00 = none 01 = upper 1/4 10 = upper 1/2 11 = all bit 1 wel: write enable latch bit indicates whether or not nonvolatile memory writes are enabled. it is automatically cleared at the end of a nonvolatile memory write cycle. 0 = writes to nonvolatile memory are not enabled 1 = writes to nonvolatile memory are enabled bit 0 wip: write-in-process bit indicates whether or not a nonvolatile memory write cycle is in process 0 = nonvolatile write cycle is not in process 1 = nonvolatile write cycle is in process downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 46 ? 2011-2016 microchip technology inc. figure 6-4: write status register sequence 6.2.2 status register read sequence the read status register instruction ( srread ) provides access to the status register. the status register may be read at any time, even during a write cycle. this allows the user to poll the wip bit to determine when a write cycle is complete. the device is selected by pulling cs low. the 8-bit srread instruction is transmitted to the mcp795wxx. the status register value is then shifted out on the so pin. the read operation is terminated by driving cs high ( figure 6-5 ). figure 6-5: read status register sequence so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 1 8 3 so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 18 3 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 47 mcp795w1x/mcp795w2x 6.3 eeprom the mcp795w2x features 2 kbits of eeprom, and the mcp795w1x features 1 kbit of eeprom. it is organized in 8-byte pages with software write protection configurable through the status register. 6.3.1 write enable and write disable the mcp795wxx contains a write enable latch. this latch must be set before any write operation will be completed internally. the eewren instruction will set the latch, and the eewrdi instruction will reset the latch. the following is a list of conditions under which the write enable latch will be reset: power-up wrdi instruction successfully executed eewrite instruction successfully executed srwrite instruction successfully executed idwrite instruction successfully executed unlock sequence for protected eeprom not followed correctly figure 6-6: write enable sequence figure 6-7: write disable sequence sck 0 234567 1 si high-impedance so cs 01 0000 0 1 sck 0 234567 1 si high-impedance so cs 01 0000 0 0 downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 48 ? 2011-2016 microchip technology inc. 6.3.2 eeprom read sequence the device is selected by pulling cs low. the 8-bit eeread instruction is transmitted to the mcp795wxx followed by an 8-bit address. see figure 6-8 for more details. after the correct eeread instruction and address are sent, the data stored in the eeprom at the selected address is shifted out on the so pin. data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. the internal address pointer automatically increments to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin ( figure 6-8 ). 6.3.3 eeprom write sequence prior to any attempt to write data to the mcp795wxx eeprom, the write enable latch must be set by issuing the eewren instruction. this is done by setting cs low and then clocking out the proper instruction into the mcp795wxx. after all eight bits of the instruction are transmitted, cs must be driven high to set the write enable latch. if the write operation is initiated immediately after the eewren instruction without cs driven high, data will not be written to the array since the write enable latch was not properly set. after setting the write enable latch, the user may proceed by driving cs low, issuing an eewrite instruction, followed by the address, and then the data to be written. up to 8 bytes of data can be sent to the device before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. additionally, a page address begins with xxxx x000 and ends with xxxx x111 . if the internal address counter reaches xxxx x111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and over-write any data that previously existed in those locations. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the n th data byte has been clocked in. if cs is driven high at any other time, the write operation will not be completed. refer to figure 6-9 and figure 6-10 for more detailed illustrations on the byte write sequence and the page write sequence respectively. while the write is in progress, the status register may be read to check the status of the wip, wel, bp1 and bp0 bits. attempting to read a memory array location will not be possible during a write cycle. polling the wip bit in the status register is recommended in order to determine if a write cycle is in progress. when the write cycle is completed, the write enable latch is reset. figure 6-8: eeprom read sequence note: eeprom write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and, end at addresses that are integer multiples of page size C 1. if an eewrite command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent eeprom write operations that would attempt to cross a page boundary. so si sck cs 0 234567891011 1 01 0 0 0 0 01 a 7 a 6 a 5 a 4 a 1 a 0 76543210 data out high-impedance a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 49 mcp795w1x/mcp795w2x figure 6-9: eeprom byte write sequence figure 6-10: eeprom page write sequence 6.4 protected eeprom the mcp795wxx features a 128-bit protected eeprom block, organized as two 8-byte pages, that requires a special unlock sequence to be followed in order to write to the memory. the protected eeprom can be used for storing crucial information such as a unique serial number. the mcp795wx1 and mcp795wx2 include an eui-48 and eui-64 node address, respectively, pre-programmed into the protected eeprom block. custom programming is also available. the protected eeprom block is located at addresses 0x00 to 0x0f and is accessed using the idread and idwrite instructions. 6.4.1 protected eeprom read sequence the device is selected by pulling cs low. the 8-bit idread instruction is transmitted to the mcp795wxx followed by an 8-bit address. see figure 6-11 for more details. after the correct idread instruction and address are sent, the data stored in the protected eeprom at the selected address is shifted out on the so pin. data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. the internal address pointer automatically increments to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin. so si cs 0 234567891011 1 00 0 0 0 0 01 a 6 a 5 a 4 a 1 a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction data byte a 0 6 7 5 43 2 1 0 high-impedance twc sck a 7 si cs 91011 00 0 0 0 0 01 76543210 data byte 1 sck 0 234567 1 8 si cs 33 34 35 38 39 76543210 data byte n (8 max) sck 24 26 27 28 29 30 31 25 32 76543210 data byte 3 76543210 data byte 2 36 37 instruction address byte a 7 a 6 a 5 a 4 a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23 note: attempts to access addresses outside of 0x00 to 0x0f will result in the mcp795wxx ignoring the instruction. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 50 ? 2011-2016 microchip technology inc. 6.4.2 protected eeprom unlock sequence the protected eeprom block requires a special unlock sequence to prevent unintended writes, utilizing the unlock instruction. before performing the unlock sequence, the wel bit must first be set by executing an eewren instruction (see section 6.3.1 ?write enable and write disable? for details). to unlock the block, the following sequence must be followed after setting the wel bit: 1. execute an unlock instruction with a data byte of 0x55 2. execute an unlock instruction with a data byte of 0xaa 3. write the desired data bytes to the protected eeprom using the idwrite instruction figure 6-12 illustrates the sequence. an entire protected eeprom page does not have to be written in a single operation. however, the block is locked after each write operation and must be unlocked again to start a new write command. 6.4.3 protected eeprom write sequence prior to any attempt to write data to the mcp795wxx protected eeprom block, the write enable latch must be set by issuing the eewren instruction, and then the protected eeprom unlock sequence must be performed. the eewren instruction is issued by setting cs low and then clocking out the proper instruction into the mcp795wxx. after all eight bits of the instruction are transmitted, cs must be driven high to set the write enable latch. after setting the write enable latch and performing the unlock sequence, the user may proceed by driving cs low, issuing an idwrite instruction, followed by the address, and then the data to be written. up to 8 bytes of data can be sent to the device before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. additionally, a page address begins with xxxx x000 and ends with xxxx x111 . if the internal address counter reaches xxxx x111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and over-write any data that previously existed in those locations. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the n th data byte has been clocked in. if cs is driven high at any other time, the write operation will not be completed. refer to figure 6-12 for more detailed illustrations on the page write sequence. while the write is in progress, the status register may be read to check the status of the wip, wel, bp1 and bp0 bits. attempting to read a memory array location will not be possible during a write cycle. polling the wip bit in the status register is recommended in order to determine if a write cycle is in progress. when the write cycle is completed, the write enable latch is reset. if an attempt is made to write to an address outside of the 0x00 to 0x0f range, the mcp795wxx will not execute the write instruction, no data will be written, and the device will immediately accept a new command. note 1: diverging from any step of the unlock sequence may result in the eeprom remaining locked, the write operation being ignored, and the wel bit being reset. 2: unlocking the eeprom is not required in order to read from the memory. note: protected eeprom write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and, end at addresses that are integer multiples of page size C 1. if an idwrite command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent protected eeprom write operations that would attempt to cross a page boundary. downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 51 mcp795w1x/mcp795w2x figure 6-11: protected eeprom read sequence figure 6-12: protected eeprom unlock and page write sequence so si sck cs 0 234567891011 1 01 0 1 1 0 01 a 1 a 0 76543210 data out high-impedance a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction 0000 si cs 91011 00 0 1 1 0 01 76543210 data byte 1 sck 0 234567 18 si cs 33 34 35 38 39 76543210 data byte n (8 max) sck 24 26 27 28 29 30 31 25 32 76543210 data byte 3 76543210 data byte 2 36 37 instruction address byte a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23 si cs 91011 10 0 1 0 0 00 sck 0 234567 1 8 instruction data byte 12 13 14 15 01 000 1 1 1 1. unlock instruction with 0x55 data byte si cs 91011 10 0 1 0 0 00 sck 0 234567 18 instruction data byte 12 13 14 15 10 111 0 0 0 2. unlock instruction with 0xaa data byte 3. idwrite instruction 0000 downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 52 ? 2011-2016 microchip technology inc. 6.5 pre-programmed eui-48 or eui-64 node address the mcp795wx1 and mcp795wx2 are programmed at the factory with a globally unique node address stored in the protected eeprom block. 6.5.1 eui-48 node address (mcp795wx1) the 6-byte eui-48? node address value of the mcp795wx1 is stored in protected eeprom locations 0x02 through 0x07, as shown in figure 6-13 . the first three bytes are the organizationally unique identifier (oui) assigned to microchip by the ieee registration authority. the remaining three bytes are the extension identifier, and are generated by microchip to ensure a globally-unique, 48-bit value. 6.5.1.1 eui-64 support using the mcp795wx1 the pre-programmed eui-48 node address of the mcp795wx1 can easily be encapsulated at the application level to form a globally unique, 64-bit node address for systems utilizing the eui-64 standard. this is done by adding 0xfffe between the oui and the extension identifier, as shown below. 6.5.2 eui-64 node address (mcp795wx2) the 8-byte eui-64? node address value of the mcp795wx2 is stored in array locations 0x00 through 0x07, as shown in figure 6-14 . the first three bytes are the organizationally unique identifier (oui) assigned to microchip by the ieee registration authority. the remaining five bytes are the extension identifier, and are generated by microchip to ensure a globally-unique, 64-bit value. figure 6-13: eui-48 node address physical memory map example (mcp795wx1) note: currently, microchips ouis are 0x0004a3, 0x001ec0, 0xd88039 and 0x5410ec, though this will change as addresses are exhausted. note: as an alternative, the mcp795wx2 features an eui-64 node address that can be used in eui-64 applications directly without the need for encapsulation, thereby simplifying system software. see section 6.5.2 ?eui-64 node address (mcp795wx2)? for details. note: currently, microchips ouis are 0x0004a3, 0x001ec0, 0xd88039 and 0x5410ec, though this will change as addresses are exhausted. note: in conformance with ieee guidelines, microchip will not use the values 0xfffe and 0xffff for the first two bytes of the eui-64 extension identifier. these two values are specifically reserved to allow applications to encapsulate eui-48 addresses into eui-64 addresses. 02h 07h 24-bit organizationally unique identifier 24-bit extension identifier 00h 04h a3h 12h 34h 56h corresponding eui-48? node address: 00-04-a3-12-34-56 description data array address corresponding eui-64? node address after encapsulation: 00-04-a3-ff-fe-12-34-56 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 53 mcp795w1x/mcp795w2x figure 6-14: eui-64 node address physic al memory map example (mcp795wx2) 00h 07h 24-bit organizationally unique identifier 40-bit extension identifier 00h 04h a3h 12h 34h 56h corresponding eui-64? node address: 00-04-a3-12-34-56-78-90 description data array address 78h 90h downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 54 ? 2011-2016 microchip technology inc. 7.0 packaging information 7.1 package marking information part number 1st line marking codes soic tssop mcp795w20 mcp795w20 795w20t mcp795w10 mcp795w10 795w10t mcp795w21 mcp795w21 795w21t mcp795w11 mcp795w11 795w11t mcp795w22 mcp795w22 795w22t mcp795w12 mcp795w12 795w12t note: t = temperature grade legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code jedec ? designator for matte tin (sn) * this package is rohs compliant. the jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 14-lead soic (3.90 mm) example 14-lead tssop example mcp795w20 i/sl 1621256 3 e 795w20i 1621 256 downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 55 mcp795w1x/mcp795w2x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 56 ? 2011-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 57 mcp795w1x/mcp795w2x downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 58 ? 2011-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 59 mcp795w1x/mcp795w2x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 60 ? 2011-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 61 mcp795w1x/mcp795w2x appendix a: revision history revision a (11/2011) initial release of this document. revision b (03/2012) added detailed descriptions for registers. revision c (06/2012) revised data sheet for 3v operation. revision d (06/2016) removed preliminary status; updated overall content for improved clarity; added detailed descriptions of registers; expanded descriptions of peripheral features; updated block diagram and application schematic; defined names for all bits and registers, and renamed the bits shown in tab l e 1 for clarification; renamed the dc characteristics shown in tab le 2 for clarification. table -1: bit name changes table -2: dc characteristic name changes old bit name new bit name calsgn trimsign oscon oscrun vbat pwrfail lp lpyr sqwe sqwen alm0 alm0en alm1 alm1en rs0 sqwfs0 rs1 sqwfs1 rs2 crstrim calibration trimval<7:0> wddel wdtdlyen wdtpls wdtpws wd<3:0> wdtps<3:0> even0 evlen even1 evhen evwdt evwdten evldb evlps evhs<1:0> evhcs<1:0> alm0c<2:0> alm0msk<2:0> alm1c<2:0> alm1msk<2:0> old name old symbol new name new symbol operating current i cc read eeprom operating current i cceerd i dd write i cceewr v bat current i bat timekeeping backup current i batt standby current i ccs v cc data retention current (oscillator off) i ccdat downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 62 ? 2011-2016 microchip technology inc. notes: downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 63 mcp795w1x/mcp795w2x the microchip website microchip provides online support via our website at www.microchip.com . this website is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the website contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip website at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the website at: http://microchip.com/support downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 64 ? 2011-2016 microchip technology inc. notes: downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 65 mcp795w1x/mcp795w2x product identification system to order or obtain information, e.g., on pric ing or delivery, refer to the factory or the listed sales office. not every possib le ordering combination is listed below . part no. /xx package tem p. range device device: mcp795w 1.8v - 3.6v spi serial rtcc with watchdog timer and event detection eeprom density: 1 = 1 kbit eeprom 2 = 2 kbit eeprom protected eeprom: 0 = blank 1 = pre-programmed eui-48? address 2 = pre-programmed eui-64? address tape & reel option: blank = tube t = tape & reel temperature range: i= - 4 0 ? c to +85 ? c package: sl = 14-lead plastic small outline (3.90 mm body) st = 14-lead plastic thin shrink small outline (4.4 mm body) examples: a) mcp795w20-i/sl: 2 kbit eeprom, industrial temperature, soic package. b) mcp795w10-i/st: 1 kbit eeprom, industrial temperature, tssop package. c) mcp795w21-i/sl: 2 kbit eeprom, pre-programmed eui-48? address, industrial temperature, soic package. d) mcp795w22-i/st: 2 kbit eeprom, pre-programmed eui-64? address, industrial temperature, tssop package. x eeprom protected tape & reel eeprom ? density x [x] (1) x option note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. downloaded from: http:///
mcp795w1x/mcp795w2x ds20002280d-page 66 ? 2011-2016 microchip technology inc. notes: downloaded from: http:///
? 2011-2016 microchip technology inc. ds20002280d-page 67 mcp795w1x/mcp795w2x information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2011-2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0726-3 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
ds20002280d-page 68 ? 2011-2016 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - guangzhou tel: 86-20-8755-8029 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 06/17/16 downloaded from: http:///

▲Up To Search▲

Price & Availability of MCP795W10-ISL

	To Download MCP795W10-ISL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .