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this is information on a product in full production. october 2015 docid028428 rev 1 1/35 m34e04b 4-kbit serial presence dete ct (spd) eeprom compatible with jedec ee1004 datasheet - production data features ? 512-byte serial presence detect eeprom compatible with jedec ee1004 specification ? compatible with smbu s serial interface: ? up to 1 mhz transfer rate ? eeprom memory array: ? 4 kbits organized as two pages of 256 bytes each ? each page is composed of two 128-byte blocks ? no hardware write protection ? software data protection for each 128-byte block ? write: ? byte write within 5 ms ? 16 bytes page write within 5 ms ? noise filtering: ? schmitt trigger on bus inputs ? noise filter on bus inputs ? single supply voltage: ? 1.7 v to 3.6 v ? operating temperature range: ? from 0 c up to +95 c ? enhanced esd/latch-up protection ? more than 4million write cycles ? more than 200-year data retention ? rohs-compliant and halogen-free 8-lead ultra thin fine pitch dual flat no lead package (ecopack2 ? ) ufdfpn8 (mc) 2 x 3 mm www.st.com
contents m34e04b 2/35 docid028428 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 slave address (sa2, sa1, sa0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.3 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . 14 3.7 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7.4 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8.1 set and clear the write protection (swpn and cwp) . . . . . . . . . . . . . . 17 3.8.2 read the protection status (rpsn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8.3 set the page address (span) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8.4 read the page address (rpa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
docid028428 rev 1 3/35 m34e04b contents 3 4 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 use within a ddr4 dram module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 programming the m34e04b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.1 isolated dram module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.2 dram module inserted in the applicat ion motherboard . . . . . . . . . . . . 20 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 ufdfn8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables m34e04b 4/35 docid028428 rev 1 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. device type identifier code (dti c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. dram dimm connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. acknowledge when writing data or defining the write-protection status (instructions with r/w bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5. acknowledge when reading the pr otection status (instructions with r/w bit = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. operating conditions (for temperature range 9 device s) . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. ufdfn8 - 8-lead, 2 3 mm, 0.5 mm pitc h ultra thin profile fine pitch dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid028428 rev 1 5/35 m34e04b list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 7. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. serial presence detect block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. ufdfn8 - 8-lead, 2 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
description m34e04b 6/35 docid028428 rev 1 1 description the m34e04b is a 512-b yte eeprom device designed to operate the smbus bus in the 1.7 v - 3.6 v voltage range, with a maximum of 1 mhz transfer rate in the 2.2 v - 3.6 v voltage range, over the jedec defined ambient temperature of 0c / 95c. the m34e04b includes a 4-kbit serial eeprom organized as two pages of 256 bytes each, or 512 bytes of total memory. each page is composed of two 128-byte blocks. the device is able to selectively lock the data in any or all of the four 128-byte blocks. designed specifically for use in dram dimms (dual inline memory modules) with serial presence detect, all the information concerning the dram module configuration (such as its access speed, its size, its organization) can be kept write-protected in one or more memory blocks. the m34e04b device is protocol -compatible with the previous g eneration of 2-kbit devices, m34e02. the page selection method allows co mmands used with lega cy devices such as m34e02 to be applied to the lower or upper pages of the eeprom. individually locking a 128-byte block may be accomplished using a software write protection mechanism in conjunction with a high input voltage v hv on input sa0. by sending the device a specific smbus sequence, each block may be protected from writes until the write protection is electrically reversed using a separate smbus sequence which also requires v hv on input sa0. the write protection for all four blocks is cleared simultaneously. figure 1. logic diagram figure 2. 8-pin package connections (top view) 1. see the package information section for package dimensions, and how to identify pin 1. 2. nc: not connected 06y9 6$6$6$ 6'$ 9 && 1& 6&/ 9 66 0(% 06y9 0(% 6'$ 9 66 6&/ 1& 6$ 6$ 9 && 6$
docid028428 rev 1 7/35 m34e04b description 34 table 1. signal names signal names description sa2, sa1, sa0 slave address sda serial data scl serial clock v cc supply voltage v ss ground
signal description m34e04b 8/35 docid028428 rev 1 2 signal description 2.1 serial clock (scl) the signal applied on this input is used to stro be the data available on sda(in) and to output the data on sda(out). if scl is driven low for ttimeout (see table 13 ) or longer, the m34e04b is set back in standby mode, ready to receive a new start condition. 2.2 serial data (sda) sda is an input/output used to transfer data in or out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be connected from serial data (sda) to v cc . ( figure 12 indicates how the value of the pull-up resistor can be calculated). 2.3 slave address (sa2, sa1, sa0) (sa2,sa1,sa0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7- bit device type identifier code (dtic, see table 2 ). these inputs must be tied to v cc or v ss , as shown in figure 3 . when not connected (left floating), these inputs are read as low (0). the sa0 input is used to detect the v hv voltage, when decoding an swp or cwp instruction. figure 3. device select code 2.4 supply voltage (v cc ) 2.4.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see table 8 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. d^??e?s 6$ l 0(% 6$ 0(% l 9 66 9 66 9 && 9 &&
docid028428 rev 1 9/35 m34e04b signal description 34 this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 2.4.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined in table 8 . 2.4.3 device reset in order to prevent inadvertent write operations during power-up, a power-on reset (por) circuit is included. at power- up, the device does not respon d to any instruction until v cc reaches the internal reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in table 8 ). when v cc passes over the por threshold, the de vice is reset and enters the standby power mode. however, the device must not be accessed until v cc reaches a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range. in a similar way, during power-down (continuous decrease in v cc ), as soon as v cc drops below the power-on reset threshold voltage, t he device stops responding to any instruction sent to it. 2.4.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
signal description m34e04b 10/35 docid028428 rev 1 figure 4. bus protocol 3#, 3$! 3#, 3$! 3$! 3tart condition 3$! )nput 3$! #hange !)c 3top condition -3" !#+ 3tart condition 3#, -3" !#+ 3top condition
docid028428 rev 1 11/35 m34e04b device operation 34 3 device operation the device supports the i 2 c protocol. this is summarized in figure 4 . any device that sends data onto the bus is defined to be a transm itter, and any device t hat reads the data is defined to be a receiver. the device that cont rols the data transfer is known as the bus master, and the other device is known as the slave device. a data transfer can only be initiated by the bu s master, which will also provide the se rial clock for synchronization. the memory device is always a slave in all communication. 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 3.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write command triggers the internal eeprom write cycle. 3.3 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether a bus master or a slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 3.4 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 3.5 memory addressing to start a communication between the bus ma ster and the slave device, the bus master must initiate a start condition. following this, the bus master sends the device select code, shown in table 2 (on serial data (sda), most significant bit first). the device type identifier code (dtic) consists of a 4-bit device type identifier, and a 3-bit slave address (sa2, sa1, sa0). to address the memory array, the 4-bit device type identifier is 1010b; to access the writ e-protection settings, it is 0110b.
device operation m34e04b 12/35 docid028428 rev 1 up to eight memory devices can be connected on a single serial bus. each one is given a unique 3-bit code on the slave address (sa2, sa1, sa0) inputs. when the device select code is received, the device onl y responds if the slave address is the same as the value on the slave address (sa2, sa1, sa0) inputs. the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the de vice does not match the device select code, it de selects itself from the bus, and goes into standby mode. 3.6 write operations following a start condition, the bus master sends a device select code with the r w bit reset to 0. the device acknowledges this, as shown in figure 5 , and waits for an address byte. table 2. device type identifier code (dtic) abbr device type identifier (1) select address (2) (3) r_w_n sa0 pin (4) b7 b6 b5 b4 b3 b2 b1 b0 read rspd 1 0 1 0 lsa2 lsa1 lsa0 1 0 or 1 write wspd 0 set write protection, block 0 swp0 0110 001 0 v hv set write protection, block 1 swp1 1 0 0 0 v hv set write protection, block 2 swp2 1 0 1 0 v hv set write protection, block 3 swp3 0 0 0 0 v hv clear all write protection cwp 0 1 1 0 v hv read protection status, block 0 (5) rps0 0 0 1 1 0, 1 or v hv read protection status, block 1 (5) rps1 1 0 0 1 0, 1 or v hv read protection status, block 2 (5) rps2 1 0 1 1 0, 1 or v hv read protection status, block 3 (5) rps3 0 0 0 1 0, 1 or v hv set page address to 0 (6) spa0 1 1 0 0 0, 1 or v hv set page address to 1 (6) spa1 1 1 1 0 0, 1 or v hv read page address (7) rpa 110 10, 1 or v hv reserved - all other encodings 1. the most significant bit, b7, is sent first. 2. logical serial addresses (lsa) are generated by the combination of inputs on the sa pins. 3. for backward compatibility with m34e02 devices, the order of block select bits (b3 and b1) is not a simple binary encoding of the block number. 4. sa0 pin is driven to vss, vcc or vhv. 5. reading the block protection status results in ack. 6. setting the ee page address to 0 selects the lower 256 bytes of eeprom; setting it to 1 selects the upper 256 bytes of eeprom. subsequent read ee or write ee commands operate on the selected ee page. 7. reading the ee page address results in ack when the current page is 0, and noack when the current page is 1.
docid028428 rev 1 13/35 m34e04b device operation 34 the device responds to the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a by te write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) and serial clock (scl) are ignored, and the device does not respond to any requests. 3.6.1 byte write after the device select code and the address byte, the bus master sends one data byte. the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 5 . figure 5. write mode sequences in a non write-protected area 3.6.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same . if more bytes are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device. after each byte is tr ansferred, the internal byte address counter (the 4 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition. 3top 3tart "yte7rite $eviceselect "yteaddress $atain 3tart 0age7rite $eviceselect "yteaddress $atain $atain !)b 3top $atain. !#+ !#+ !#+ 27 !#+ !#+ !#+ 27 !#+ !#+
device operation m34e04b 14/35 docid028428 rev 1 3.6.3 minimizing system delays by polling on ack the sequence, as shown in figure 6 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 6. write cycle polling flowchart using ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its intern al latches to the memory ce lls. the maximum write time (t w ) is shown in table 13 , but the typical time is shorter. to make use of this, a polling sequence $,g :ulwhf\foh lqsurjuhvv 1h[w 2shudwlrqlv dgguhvvlqjwkh phpru\ 6wduwfrqglwlrq 'hylfhvhohfw zlwk5: $&. uhwxuqhg <(6 12 <(6 12 5h6wduw 6wrs 'dwdiruwkh :ulwhrshudwlrq 6hqg$gguhvv dqg5hfhlyh$&. <(6 12 6wduw&rqglwlrq &rqwlqxhwkh :ulwhrshudwlrq &rqwlqxhwkh 5dqgrp5hdgrshudwlrq 'hylfhvhohfw zlwk5: )luvwe\whrilqvwuxfwlrq zlwk5: douhdg\ ghfrghge\wkhghylfh
docid028428 rev 1 15/35 m34e04b device operation 34 can be used by the bus master. 3.7 read operations read operations are performed independentl y of software protection has been set. the device has an internal address counter which is incremented each time a byte is read. 3.7.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 7 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the r w bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 3.7.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r w bit set to 1. the device acknowledges this, and outputs the byte addressed by the inter nal address counter. the counter is then incremented. the bus master terminates the tran sfer with a stop condition, as shown in figure 7 , without acknowledging the byte.
device operation m34e04b 16/35 docid028428 rev 1 figure 7. read mode sequences 3.7.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next by te in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 7 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 3.7.4 acknowledge in read mode for all read commands, after each byte read, the device waits for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode. 3tart $evselect
"yteaddress 3tart $evselect $ataout !)b $ataout. 3top 3tart #urrent !ddress 2ead $evselect $ataout 2andom !ddress 2ead 3top 3tart $evselect
$ataout 3equential #urrent 2ead 3top $ataout. 3tart $evselect
"yteaddress 3equential 2andom 2ead 3tart $evselect
$ataout 3top !#+ 27 ./!#+ !#+ 27 !#+ !#+ 27 !#+ !#+ !#+ ./!#+ 27 ./!#+ !#+ !#+ 27 !#+ !#+ 27 !#+ ./!#+
docid028428 rev 1 17/35 m34e04b device operation 34 note: the seven most significant bits of the device select code of a random read (in the 1 st and 3 rd bytes) must be identical. 3.8 setting the write protection there are four independent memory blocks, and each block may be independently protected. the memory blocks are: ? block 0 = memory addresses 0x00 to 0x7f (decimal 0 to 127), page address = 0 ? block 1 = memory addresses 0x80 to 0xff (decimal 128 to 255), page address = 0 ? block 2 = memory addresses 0x00 to 0x7f (decimal 0 to 127), page address = 1 ? block 3 = memory addresses 0x80 to 0xff (decimal 128 to 255), page address = 1 the device has three software commands for setting, clearing, or interrogating the write- protection status. ? swpn: set write protection for block n ? cwp: clear write protection for all blocks ? rpsn: read protection status for block n the level of write protection (set or cleared), that has been defined using these instructions, remains defined even after a power cycle. the dtics of the swp, cwp and rps instructions are defined in table 2 . 3.8.1 set and clear the writ e protection (swpn and cwp) if the software write protection has been set with the swpn instruction, it may be cleared again with a cwp instruction. swpn acts on a single block as specified in the swpn command, but cwp clears the write protection for all blocks. when decoded, swpn and cwpn trigger a write cycle lasting t w (see table 13 ). the dtics of the swp and cwp instructions are defined in table 2 . figure 8. setting the write protection 34!24 3$!,).% !)" !#+ 7/2$ !$$2%33 6!,5% $/.g4#!2% !#+ $!4! 6!,5% $/.g4#!2% 34/0 !#+ #/.42/, "94% "53!#4)6)49 -!34%2 "53!#4)6)49
device operation m34e04b 18/35 docid028428 rev 1 3.8.2 read the protection status (rpsn) the serial bus master issues an rpsn command specifying which block to report upon. if the software write protection has not been set, the device replies to the data byte with an ack. if it has been set, the device replies to the data byte with a noack. the dtic of the rpsn instruction is defined in table 2 . 3.8.3 set the page address (span) the span command selects the lower 256 bytes (spa0) or upper 256 bytes (spa1). after a cold or warm power-on reset, the page address is always 0, selecting the lower 256 bytes. the dtic of the span instruction is defined in table 2 . 3.8.4 read the page address (rpa) the rpa command determines if the currently selected page is 0 (device returns ack) or 1 (device returns noack). the dtic of the rpa instruction is defined in table 2 .
docid028428 rev 1 19/35 m34e04b initial deli very state 34 4 initial delivery state the device is delivered with all bits in the memo ry array set to ?1? (each byte contains ffh).
use within a ddr4 dram module m34e04b 20/35 docid028428 rev 1 5 use within a ddr4 dram module in the application, the m34e04b is soldered di rectly in the printed ci rcuit module. the three slave address inputs (sa2, sa1, sa0) must be connected to v ss or v cc directly (that is without using a serial resistor) through the dram module connector (see table 3 and figure 3 ). the pull-up resistor on sda is connected on the smbus of the motherboard (as shown in figure 9 ). 5.1 programming the m34e04b the situations in which the m34e04b is programmed can be considered under two headings: ? when the ddr4 dram is isolated (not inserted on the pcb motherboard) ? when the ddr4 dram is inserted on the pcb motherboard 5.1.1 isolated dram module with a specific programming equipment, it is possible to define the m34e04b content, using byte and page write instructions, and the writ e-protection swp(n) and cwp instructions. to issue the swp(n) and cwp instructions, the signal applied on sa0 must be driven to v hv during the whole instruction. 5.1.2 dram module inserted in the application motherboard table 4 and table 5 show how the ack bits can be us ed to identify the write-protection status. table 3. dram dimm connections dimm position sa2 sa1 sa0 0 v ss v ss v ss 1 v ss v ss v cc 2 v ss v cc v ss 3 v ss v cc v cc 4 v cc v ss v ss 5 v cc v ss v cc 6 v cc v cc v ss 7 v cc v cc v cc
docid028428 rev 1 21/35 m34e04b use within a ddr4 dram module 34 table 4. acknowledge when writing data or defining the write-protection status (instructions with r/w bit = 0) status instruction ack address ack data byte ack write cycle (t w ) protected swpn noack not significant noack not significant noack no cwp ack not significant ack not significant ack yes page or byte write in protected block ack address ack data noack no not protected swpn or cwp ack not significant ack not significant ack yes page or byte write ack address ack data ack yes table 5. acknowledge when reading the protection status (instructions with r/w bit = 1) swpn status instruction ack address ack data byte ack set rpsn noack not significant noack not significant noack not set rpsn ack not significant noack not significant noack
use within a ddr4 dram module m34e04b 22/35 docid028428 rev 1 figure 9. serial presence detect block diagram 1. sa0, sa1 and sa2 are wired at each dram module sl ot in a binary sequence for a maximum of 8 devices. 2. common clock and common data are shared across all the devices. z?oor? /?? zdu}o?o}?vu? ^ ^> ^ ^ ^? s zdu}o?o}?vu? ^ ^> ^ ^ ^? zdu}o?o}?vu?? ^ ^> ^ ^ ^? zdu}o?o}?vu?e ^ ^> ^ ^ ^? zdu}o?o}?vu?? ^ ^> ^ ^ ^? zdu}o?o}?vu?? ^ ^> ^ ^ ^? s zdu}o?o}?vu? ^ ^> ^ ^ ^? zdu}o?o}?vu? ^ ^> ^ ^ ^? s^^ s^^ s^^ s s^^ s^^ s s s^^ s s s^^ s^^ s ^>o]v ^o]v &?}u?zu}?z?}?/ ? u
docid028428 rev 1 23/35 m34e04b maximum rating 34 6 maximum rating stressing the device above t he rating listed in the absolute maximum ratings table may cause permanent damage to the device. th ese are stress ratings only and the device operation at these conditions or at any othe r conditions above those indicated in the operating sections of this spec ification is not implied. an exposure to absolute maximum rating conditions for ex tended periods may affect the device reliability. table 6. absolute maximum ratings symbol parameter min. max. unit ambient temperature with power applied -55 130 c t stg storage temperature -65 150 c v io input or output range sa0 others -0.50 -0.50 11.0 6.5 v i ol dc output current (sda = 0) - 20 ma v cc supply voltage -0.5 6.5 v v esd electrostatic discharge vo ltage (human body model) (1) 1. ansi/esda/jedec js-001-2012 (c1 = 100 pf, r1 = 1500 , and r2 = 500 ). - 3500 (2) 2. positive and negative pulses applied on differen t combinations of pin connections, according to aecq100-002 (compliant with ansi/esda/jedec js-001-2012, c1 = 100 pf, r1 = 1500 ). v
dc and ac parameters m34e04b 24/35 docid028428 rev 1 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. figure 10. ac measurement i/o waveform table 7. operating conditions (f or temperature range 9 devices) symbol parameter min. max. unit v cc supply voltage 1.7 3.6 v t a ambient operating temperature 0 +95 c table 8. ac measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf scl input rise and fall time, sda input fall time -50ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v -36 6 ## 6 ## 6 ## 6 ## )nputandoutput 4imingreferencelevels )nputvoltagelevels
docid028428 rev 1 25/35 m34e04b dc and ac parameters 34 table 9. input parameters symbol parameter (1) 1. characterized, not tested in production. test condition min. max. unit c in input capacitance (sda) - - 8 pf c in input capacitance (other pins) - - 6 pf z eil sa0, sa1, sa2 input impedance v in < 0.3v cc 30 - k z eih sa0, sa1, sa2 input impedance v in > 0.7v cc 800 - k t ns pulse width ignored (input filter on scl and sda) - - 100 ns table 10. cycling performance symbol parameter test condition max. unit ncycle write cycle endurance t a 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycle t a = 85 c, v cc (min) < v cc < v cc (max) 1,200,000 table 11. memory cell data retention parameter test condition min. unit data retention (1) 1. the data retention behavior is checked in producti on, while the 200-year limit is defined from characterization and qualification results. t a = 55 c 200 year
dc and ac parameters m34e04b 26/35 docid028428 rev 1 table 12. dc characteristics symbol parameter test condition (in addition to those in table 7 ) min max unit i li input leakage current (scl, sda, sa0, sa1, sa2) v in = v ss or v cc - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) f c = 400 khz or 1 mhz - 1 ma i cc0 supply current (write) during t w, v in = v ss or v cc -1 (1) 1. measured during characterization, not tested in production. ma i cc1 standby supply current device not selected (2) , v in = v ss or v cc , v cc 2.2 v 2. the device is not selected after a power-up, after a read command (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write command). -2a device not selected (2) , v in = v ss or v cc , v cc < 2.2 v -1a v il input low voltage (scl, sda) - -0.45 0.3 v cc v v ih input high voltage (scl, sda) -0.7v cc v cc +1 v v hv sa0 high voltage detect v cc < 2.2 v 7 10 v v cc 2.2 v v cc +4.8 v 10 v v ol output low voltage i ol = 20 ma, v cc 2.2 v - 0.4 v i ol = 6 ma, v cc 2 v - 0.6 v i ol = 3 ma, v cc 2 v - 0.4 v v por power on reset threshold - - 1.4 (1) v v pdr power down reset threshold - 0.7 (1) -v
docid028428 rev 1 27/35 m34e04b dc and ac parameters 34 table 13. ac characteristics symbol parameter v cc < 2.2 v v cc 2.2 v unit 100 khz 400 khz 1000 khz min. max. min. max. min. max. f scl f c clock frequency 10 100 10 400 10 1000 khz t high t chcl clock pulse width high time 4000 - 600 - 260 - ns t low (1) t clch clock pulse width low time 4700 - 1300 - 500 - ns t timeout (2) detect clock low timeout 25 35 25 35 25 35 ms t r (3) t xh1xh2 sda rise time - 1000 20 300 - 120 ns t f (3) t ql1ql2 sda(out) fall time - 300 20 300 - 120 ns t su:dat t dxch data in setup time 250 - 100 - 50 - ns t hd:di t cldx data in hold time 0 - 0 - 0 - ns t hd:dat t clqx data out hold time 200 3450 200 900 0 350 ns t su:sta (4) t chdl start condition setup time 4700 - 600 - 260 - ns t hd:sta t dlcl stop condition hold time 4000 - 600 - 260 - ns t su:sto t chdh stop condition setup time 4000 - 600 - 260 - ns t buf t dhdl time between stop condition and next start condition 4700 - 1300 - 500 - ns t w write time - 5 - 5 - 5 ms t poff (3) time ensuring a reset when v cc drops below v pdr (min) 100 - 100 - 100 - s t init (3) time from v cc (min) to the first command 0-0-0-s 1. initiate clock stretching, which is an optional smbus bus feature. 2. a timeout condition can only be ensured if scl is driven low for t timeout (max) or longer; then the m34e04b is set in standby mode and is ready to receive a new start condition. if scl is driven low for less than t timeout( min), the m34e04b internal state remains unchanged. 3. measured during characteriza tion, not tested in production. 4. to avoid spurious start and stop c onditions, a minimum delay is placed between the falling edge of scl and the falling or rising edge of sda.
dc and ac parameters m34e04b 28/35 docid028428 rev 1 figure 11. ac waveforms ^> ^k? ^> ^/v ?o] ?>ys ?>yy ?,, ^?}? }v]?]}v ?,> ^??? }v]?]}v t?]??o ?t /??i ?o] ?y>y>? ^/v ?,> ^??? }v]?]}v ?y, ?>y ^ /v?? ^ zvp ?,, ?,> ^?}? }v]?]}v ^??? }v]?]}v ?y,y,? ^> ?,> ?>> ?>, ?y,y,? ?y>y>? ?y>y>? ?,>
docid028428 rev 1 29/35 m34e04b dc and ac parameters 34 figure 12. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz figure 13. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz %xvolqhsxooxsuhvlvwrun 06y9 ,e&exv pdvwhu 6&/ 6'$ +huh 5 exv [ & exv qv & exv 9 && 5 exv 5 exv [ & exv qv 0(% 7kh5 exv [& exv wlphfrqvwdqw 0xvwehehorzwkhqv 7lphfrqvwdqwolqduhsuhvhqwhg rqwkhohiw %xvolqhfdsdflwrus) dli %xvolqhsxooxsuhvlvwrun %xvolqhfdsdflwrus) 7kh5 exv [& exv wlphfrqvwdqw pxvwehehorzwkhqv 7lphfrqvwdqwolqh uhsuhvhqwhgrqwkhohiw , &exv pdvwhu 5 exv [& exv qv +huh 5 exv [& exv qv 0(% 5 exv & exv 6&/ 6'$ 9 ff
package information m34e04b 30/35 docid028428 rev 1 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 8.1 ufdfn8 package information figure 14. ufdfn8 - 8-lead, 2 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline 1. max. package warpage is 0.05 mm. 2. exposed copper is not systematic and can appear parti ally or totally according to the cross section. 3. drawing is not to scale. 4. the central pad (the area e2 by d2 in the above illustrat ion) must be either connected to vss or left floating (not connected) in the end application =:eb0(b9 7rsylhz 3lq ,'pdunlqj 6lghylhz 6hdwlqjsodqh hhh fff & & & & % $ 1 ' ( ddd ddd $ $ $ [ [ 'dwxp$ 7huplqdowls 'hwdlo3$ (yhqwhuplqdo / / / h h 3lq ,'pdunlqj %rwwrpylhz 6hh'hwdlo3$ h h 1'[ ' / / ( . / e
docid028428 rev 1 31/35 m34e04b package information 34 table 14. ufdfn8 - 8-lead, 2 3 mm, 0.5 mm pitc h ultra thin profile fine pitch dual flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.450 0.550 0.600 0.0177 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b (2) 2. dimension b applies to plated terminal and is meas ured between 0.15 and 0.30 mm from the terminal tip. 0.200 0.250 0.300 0.0079 0.0098 0.0118 d 1.900 2.000 2.100 0.0748 0.0787 0.0827 d2 1.200 - 1.600 0.0472 - 0.0630 e 2.900 3.000 3.100 0.1142 0.1181 0.1220 e2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - 0.0197 k 0.300 - - 0.0118 - - l 0.300 - 0.500 0.0118 - 0.0197 l1 - - 0.150 - - 0.0059 l3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee (3) 3. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. - - 0.080 - - 0.0031
part numbering m34e04b 32/35 docid028428 rev 1 9 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 15. ordering information scheme example: m34e04b - f mc 9 t g h device type m34 = application specific i 2 c serial access eeprom device function e04b = 4 kbit (512 8) spd (serial presence detect) operating voltage f = v cc = 1.7 to 3.6 v over 0 c to 95 c package (1) 1. all package are ecopack2 ? (rohs-compliant and free of brominated, chlorinated and antimony-oxide flame retardants) mc= ufdfpn8 (mlp8) temperature range 9 = 0 c to 95 c option t = tape and reel packing blank = tube packing plating technology g = ecopack2 ? wire bonding h = gold
docid028428 rev 1 33/35 m34e04b part numbering 34 engineering sample parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity.
revision history m34e04b 34/35 docid028428 rev 1 10 revision history table 16. document revision history date revision changes 21-oct-2015 1 initial release
docid028428 rev 1 35/35 m34e04b 35 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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