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? semiconductor component s industries, llc, 2016 1 publication order number : september 2016 - rev. p2 STK5U4UFE0D-E/d this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. STK5U4UFE0D-E product preview intelligent power module (ipm) 1200 v, 50 a the STK5U4UFE0D-E is a fully-integrated inverter power module consisting of an independent gate driver, six igbt?s and a thermistor, suitable for driving permanent magnet synchronous (pmsm) motors, brushless dc (bldc) motors and ac asynchronous motors. the igbt?s are configured in a three-phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. the power stage has undervoltage lockout protection (uvp) and v ce desaturation protection (desatp) w ith a fault detection output flag. internal boost diodes are provided for high side gate boost drive. features ? three-phase 1200 v, 50 a igbt module with independent drivers. ? negative logic interface. ? built-in undervoltage protection (uvp) and v ce desaturation protection (desatp) with a fault detection output flag. ? integrated bootstrap di odes and resistors. ? separate low-side igbt emitter connections for individual current sensing of each phase. ? thermistor typical applications ? industrial drives ? industrial pumps ? industrial fans ? industrial automation figure 1. functional diagram www.onsemi.com package picture marking diagram stk5u4ufe0d = specific device code a = year b = month c = production site dd = factory lot code ordering information device package shipping (qty / packing) STK5U4UFE0D-E tbd tbd hinu fou vdu vp nw nv nu u v w desatp uh uh uh vh wh ul vl wl gate driver with desaturation protection gndu hinv fov vdv gate driver with desaturation protection gndv hinw fow vdw gate driver with desaturation protection gndw linu linv vdn 3x gate driver with desaturation protection linw fon gnd desatp vh vh desatp wh wh ul vl wl desatp ul desatp vl desatp wl th1 th2 stk5u4ufe0d abcdd 1 32 64 33
STK5U4UFE0D-E www.onsemi.com 2 figure 2. application schematic ga te driver with desaturation prot ectio n gate driver with desaturation prot ectio n gate driver with desaturation prot ectio n ga te driver with desaturation prot ectio n gate driver with desaturation prot ection ga te driver with desaturation prot ectio n cs + motor cbulk interface circuit (see detail) interface circuit (see detail) interface circuit (see detail) interface circuit (see detail) interface circuit (see detail) interface circuit (see detail) sensing, isolation mcu u v w vp nu nv nw vdu fou hinu gndu vdv fov hinv gndv vdw fow hinw gndw vdn gnd li nu to op-amp circuit li nv li nw fon th1 th2 sample interface circuit detail vdx fox hinx /linx gndx mcu to desat circuit to igbt gate drive gnd
STK5U4UFE0D-E www.onsemi.com 3 figure 3. equivalent block diagram gndu (32) gate driver with desaturation protection hinu (30) fou (31) vdu (29) gndv (25) vdv (22) gndw (18) hinw (16) fow (17) vdw (15) linu (8) vdn (10) linv (7) linw (6) fon (5) gnd (11) th1 (3) th2 (2) gate driver with desaturation protection gate driver with desaturation protection gate driver with desaturation protection hinv (23) fov (24) gate driver with desaturation protection gate driver with desaturation protection u (39,40,41) vp (33,34,35) v (45,46,47) w (51,52,53) nu (57,58) nv (60,61) nw (63,64)
STK5U4UFE0D-E www.onsemi.com 4 pin function description pin name description 2 th1 thermistor connection 3 th2 thermistor connection 5 fon fault output low side 6 linw logic input low side gate driver - phase w 7 linv logic input low side gate driver - phase v 8 linu logic input low side gate driver - phase u 10 vdn control power supply low side 11 gnd control power gnd low side 15 vdw control power supply high side ? phase w 16 hinw logic input high side ? phase w 17 fow fault output high side ? phase w 18 gndw control power gnd high side ? phase w 22 vdv control power supply high side ? phase v 23 hinv logic input high side ? phase v 24 fov fault output high side ? phase v 25 gndv control power gnd high side ? phase v 29 vdu control power supply high side ? phase u 30 hinu logic input high side ? phase u 31 fou fault output high side ? phase u 32 gndu control power gnd high side ? phase u 33,34,35 vp positive bus input voltage 39,40,41 u u phase output 45,46,47 v v phase output 51,52,53 w w phase output 57,58 nu low side emitter connection - phase u 60,61 nv low side emitter connection - phase v 63,64 nw low side emitter connection - phase w note : pins 1, 4, 9, 12, 13, 14, 19, 20, 21, 26, 27, 28, 36, 37, 38, 42, 43, 44, 48, 49, 50, 54, 55, 56, 59 and 62 are not pres ent
STK5U4UFE0D-E www.onsemi.com 5 absolute maximum ratings at tc = 25c (notes 1, 2) 1. stresses exceeding those listed in the maximum ratings tabl e may damage the device. if any of these limits are exceeded, dev ice functionality should not be assumed, damage may occur and reliability may be affected. 2. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 3. this surge voltage developed by the switching operation due to the wiring inductance between vp and nu, nv, nw terminal. 4. vd1 = vdu to gndu, vd2 = vdv to gndv, vd3 = vdw to gndw, vd4 = vdn to gnd 5. flatness tolerance of the heatsink should be within ? 50 ? m to +100 ? m. recommended operating ranges (note 6) 6. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. rating symbol conditions value unit supply voltage v cc vp to nu, nv, nw, surge < 1000 v (note 3) 900 v collector-emitter voltage v ce vp to u, v, w; u to nu, v to nv, w to nw 1200 v self-protection supply voltage limit (desatp capability) v cc (sc) vd1, 2, 3, 4 = between 13.5 v and 16.5 v, tj 150c, up to ?tdesatbl?, non-repetitive 800 v output current io vp, nu, nv, nw, u, v, w terminal current 50 a output peak current iop vp, nu, nv, nw, u, v, w terminal current pulse width 1 ms 100 a gate driver supply voltages vd vdu to gndu, vdv to gndv, vdw to gndw, vdn to gnd (note 4) ? 0.3 to vd v input signal voltage vin hinu to gndu, hinv to gndv, hinw to gndw; linu, linv, linw to gnd ? 0.3 to vd v fault terminal voltage vfo fou to gndu, fov to gndv, fow to gndw, fon to gnd ? 0.3 to vd v fault output ifo fou, fov, fow, fon source current 25 ma fou, fov, fow, fon sink current 10 maximum power dissipation pd igbt per channel tbd w junction temperature tj igbt, frd 150 ? c storage temperature tstg ? 40 to +125 ? c operating case temperature tc ipm case temperature ? 40 to +100 ? c package mounting torque case mounting screw m4 (note 5) 1.17 nm isolation voltage vis 50 hz sine wave ac 1 minute 2500 v rms rating symbol conditions min typ max unit supply voltage v cc vp to nu, nv, nw 0 - 800 v gate driver supply voltage vd1, 2, 3 vdu to gndu, vdv to gndv, vdw to gndw 12.6 15 17.5 v vd4 v dd to gnd 13.5 15 16.5 v on-state input voltage vin(on) hinu to gndu, hinv to gndv, hinw to gndw; linu, linv, linw to gnd 0 - 0.7 v off-state input voltage vin(off) 3.3 - 15 v pwm frequency fpwm 1 - 20 khz dead time dt turn-off to turn-on (external) 2 - - s allowable input pulse width pwin on and off 1 - - s package mounting torque m4 type screw 0.79 - 1.17 nm
STK5U4UFE0D-E www.onsemi.com 6 7. product parametric performance is indicat ed in the electrical characteristics fo r the listed test conditions, unless otherwi se noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. electrical characteristics at tc = 25 ? c, vd = 15 v (note 7) parameter test conditions symbol min typ max unit power output section collector-emitter leakage current v ce = 1200 v i ce - - 1 ma collector to emitter saturation voltage ic = 50 a, tj = 25 ? c v ce (sat) - (2.4) tbd v ic = 50 a, tj = 100 ? c - (2.5) - v diode forward voltage if = 50 a, tj = 25 ? c vf - (2.2) tbd v if = 50 a, tj = 100 ? c - (2.5) - v junction to case thermal resistance igbt j-c(t) - (0.67) tbd ? c/w fwd j-c(d) - (0.85) tbd ? c/w switching time ic = 50 a, v cc = 600 v, tj = 25c t on - (0.3) - s t off - (0.6) - s turn-on switching loss ic = 50 a, v cc = 600 v, tj = 25c e on - (6.0) - mj turn-off switching loss e off - (2.2) - mj total switching loss e tot - (8.2) - mj turn-on switching loss ic = 50 a, v cc = 600 v, tj = 100c e on - (6.5) - mj turn-off switching loss e off - (2.5) - mj total switching loss e tot - (9.0) - mj diode reverse recovery energy ic = 50 a, v cc = 600 v, tj = 100c (di/dt set by internal driver) e rec - (1.2) - mj diode reverse recovery time trr - (0.2) - s driver section gate driver power dissipation vd1, 2, 3 = 15 v id - 8 17 ma vd4 = 15 v - 24 51 ma high level input voltage hinu to gndu, hinv to gndv, hinw to gndw; linu, linv, linw to gnd vin h 3.2 - - v low level input voltage vin l - - 1.2 v logic 1 input current vin = 3.0 v i in+ - - 500 a logic 0 input current vin = 1.2 v i in- - - 100 a fault terminal output voltage fou, fov, fow, fon sink: 5 ma vfl - 0.2 1 v fou, fov, fow, fon source: 20 ma vfh 12 13.3 - v desaturation protection blanki ng time tdeasatbl - 2 - s vd supply undervoltage positive going input threshold v duvp+ 11.3 12 12.6 v vd supply undervoltage negative going input threshold v duvp- 10.4 11 11.7 v bootstrap diode reverse current vr(bd) = 1200 v ir(bd) - - 1 ma bootstrap diode forward voltage if(bd) = 0.1 a including voltage drop by resistor vf(bd) - (2.6) - v bootstrap current controlling resistor rb - 15 - ?
STK5U4UFE0D-E www.onsemi.com 7 applications information logic and protection timing chart figure 4. logic and protection timing chart notes 1. the vd supply undervoltage protection the module when the pr e-driver supply voltage falls due to an operating malfunction. it will typically start up at 12 v (typical). the uvp circuit has typically 1 v of hysteresis and will disable the output if th e supply voltage falls below 11 v (typical). the driver powe r supply low voltage protection turns off the gate and will automatically reset when recovering to normal voltage. it does not depend on input signal voltage. 2. the three high-side and three low-side gate driver ics hav e their own separate undervoltage protection which functions independently of the other phases. for the low-side drivers, ther e is one combined fault output; it is therefore not possible t o determine which output has caused the desatur ation fault. the fault condition is clear ed as soon as the input signal is set high (off state, negative logic levels). 3. when using the over-current protection with an external shunt resistor, pleas e set the current protection level to be less t han or equal to the peak output current rating (iop). input / output logic table protected operation igbt output fault output high side low side high side low side u v w u v w u v w high side - u uvp off - - - - - low low low low desatp off - - - - - high low low low high side - v uvp - off - - - - low low low low desatp - off - - - - low high low low high side - w uvp - - off - - - low low low low desatp - - off - - - low low high low low side - u uvp - - - off off off low low low low desatp - - - off - - low low low high low side - v uvp - - - off off off low low low low desatp - - - - off - low low low high low side - w uvp - - - off off off low low low low desatp - - - - - off low low low high *) - (hyphen) follows the actual input signals using negativ e logic (e.g. linu = low turns on the low-side u phase igbt). on off /vin internal desat voltage output current off on desatp protection reset signal vd supply undervoltage positive going threshold (reset) vd fault output desatp threshold desaturation protection blanking time
STK5U4UFE0D-E www.onsemi.com 8 thermistor characteristics parameter symbol condition min typ max unit resistance r 25 tc = 25 ? c 97 100 103 k ? resistance r 100 tc = 100 ? c 5.07 5.38 5.71 k ? b-constant (25-50 ? c) - b 4208 4250 4293 k temperature range - - ? 40 - +125 ? c figure 5. thermistor resistance versus case temperature 1 10 100 1000 10000 -40-30-20-10 0 102030405060708090100110120130 thermistor resistance [k ? ] case temperature tc [ ? c] thermistor resistance versus case temperature tc min typ max
STK5U4UFE0D-E www.onsemi.com 9 undervoltage lockout protection (uvp) if vd goes below the vd supply undervoltage negative going input threshold, the igbt gate drives will be turned off. if vd rises above the positive going input threshold, the igbt ga te drivers will return to normal operation. the fox signal outputs stay low during the uvp state. the uvp does not depend on input signal voltage. desaturation protecti on function (desatp) the desaturation protection function (desatp) is implemented by comparing the voltage between the collector and the emitter of igbt with an internal reference of 6.5 v (typ). if a short circuit occurs after the igbt is turned on and saturated, there will be a delay while the blanking capacitor is charged from the v ce (sat) level of the igbt to the trip voltage of the comparator. if the collector voltage exceeds the trip level, a desatp fault is triggered and the fox signal (fou, fov, fow, fon) is set high. the fault condition is cleared after the input signal is set to inactive (high due to negative logic on input). additional protection against abnormal current levels such as a protection circuit using external shunt resistors, and a fuse on the input voltage line is strongly recommended. capacitors on high voltage and vd supplies both the high voltage and vd supplies require an electrolytic capacitor and an additional high frequency capacitor. disconnection of u, v and w terminals disconnection of terminals u, v, or w during normal motor operation will cause damage to ipm, use caution with this connection. minimum input pulse width when input pulse width is less than 1 s, an output may not react to the pulse. (both on and off signal) layout the traces between the ipm terminals and each optocoupler must be as short as possible, and the stray capacitance between the primary and the secondary must be considered in order to select a layout pattern. it is essential that trace length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge voltage s. recommended value of ?cs? is in the range of 0.1 to 10 f. this capacitor should be a high frequency capacitor. thermistor inside the ipm, a thermistor used as the temperature monitor for internal substr ate is connected between ?th1? and ?th2?. the variation of thermistor resistance with temperature is shown in this datasheet. dimensioning of bootstrap capacitor the module includes an internal bootstrap circuit requiring one bootstrap capacitor for each phase, each with a value cb. the recommended value of cb is in the range of 1 to 47 f, however, this value needs to be verified prior to production. when not using the bootstrap circuit, each high side driver power supply requires an external independent floating power supply. if the selected capacitance is more than 47 f (20%), connect a resistor (about 40 ? ) in series between each three-phase upper side power supply terminals (vdu, vdv, vdw) and each bootstrap capacitor. when not using the bootstrap circuit, each upper side gate driver power supply requires an external independent floating power supply. also we recommend adopting safety measures such as using zener diodes for surge absorption or low impedance capacitors around each power supply terminal to suppress voltage transients. cb value calculation for bootstrap circuit calculate condition item symbol value unit high-side power supply. vd1,2,3 15 v total gate charge of output power igbt at 15 v. qg 311 nc high-side power supply undervoltage protection. uduvp- 12 v high-side power dissipation. id max 17 ma on time required for cb voltage to fall from 15 v to uvp ton-max - s capacitance calculation formula cb must not be discharged below to the upper limit of the uvp - the maximum allowable on-time (ton-max) of the upper side is calculated as follows: vd1, 2, 3 * cb ? qg ? id max * ton-max = uvp * cb cb = (qg + id max * ton-max) / (vd1, 2, 3 ? uvp) cb is recommended to be approximately 3 times the value calculated above. the recommended value of cb is in the range of 1 to 47 f, however, the value needs to be verified prior to production. figure 6. bootstrap selection as a function of maximum on time 0.01 0.1 1 10 100 0.01 0.1 1 10 boot strap capacitance cb [uf] ton-max [ms] cb vs. ton-max
STK5U4UFE0D-E www.onsemi.com 10 mounting instructions item recommended condition pitch 67.8 0.1 mm (please refer to package outline diagram) screw diameter : m4 bind machine screw, truss machin e screw, pan machine screw washer plane washer the size is d : 9 mm, d : 4.8 mm and t : 0.8 mm jis b 1256 heat sink material : aluminum or copper warpage (the surface that contacts ipm) : ? 50 to 100 m screw holes must be countersunk. no contamination on the heat sink surface that contacts ipm. torque temporary tightening : 20 to 30% of final tightening on first screw temporary tightening : 20 to 30% of final tightening on second screw final tightening : 0.79 to 1.17 nm on first screw final tightening : 0.79 to 1.17 nm on second screw grease silicone grease. thickness : 100 to 200 m uniformly apply silicone grease to whole back. thermal foils are only recommended after care ful evaluation. thickness, stiffness and compressibility parameters have a strong influence on performance. figure 7. module mounting details: components; washer drawing; need for even spreading of thermal grease recommended not recommended
STK5U4UFE0D-E www.onsemi.com 11 typical characteristics figure 8. ic versus v ce for different vd figure 9. ic versus v ce for different vd figure 10. if versus vf for different temperatures figure 11. igbt thermal impedance plot figure 12. ton versus ic for different temperatures figure 13. toff versus ic for different temperatures figure 14. eon versus ic for different temperatures figure 15. eoff versus ic for different temperatures 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 102030405060 e off , switching loss (mj) i c , collector current (a) v cc = 600v v d = 15v t j = 25 c t j = 100 c 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0 102030405060 e on , switching loss (mj) i c , collector current (a) v cc = 600v v d = 15v t j = 25 c t j = 100 c 0 50 100 150 200 250 300 0 102030405060 t on , switching time (ns) i c , collector current (a) v cc = 600v v d = 15v t j = 25 c t j = 100 c 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 i c , collector current (a) v ce , collector-emitter voltage (v) t j = 25 c vd = 15v vd = 13v vd = 17v 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 i c , collector current (a) v ce , collector-emitter voltage (v) t j = 100 c vd = 13v vd = 15v vd = 17v 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 i f , forward current (a) v f , forward voltage (v) t j = 25 c t j = 100 c 0 100 200 300 400 500 600 700 800 900 1000 0 102030405060 t off , switching time (ns) i c , collector current (a) v cc = 600v v d = 15v t j = 25 c t j = 100 c 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 standardized square-wave peak r(t) on-pulse width (s)
STK5U4UFE0D-E www.onsemi.com 12 figure 16. turn-on waveform tj = 25c, v cc = 600 v figure 17. turn-off waveform tj = 25c, v cc = 600 v figure 18. turn-on waveform tj = 100c, v cc = 600 v figure 19. turn-off waveform tj = 100c, v cc = 600 v io: 25a/div t: 100ns/div vce: 250v/div io: 25a/div t: 100ns/div vce: 250v/div t:100ns/div io: 25a/div t: 100ns/div vce: 250v/div io: 25a/div vce: 250v/div
STK5U4UFE0D-E www.onsemi.com 13 package dimensions unit : mm [tentative] missing pins : 1, 4, 9, 12, 13, 14, 19, 20, 21, 26, 27, 28, 36, 37, 38, 42, 43, 44, 48, 49, 50, 54, 55, 56, 59 and 62 to
STK5U4UFE0D-E www.onsemi.com 14 on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and othe r intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety require ments or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life sup port systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended fo r implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer sh all indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, d amages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resal e in any manner.

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