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IRPP3637-12A powir+ chipset reference design 12amp single phase synchronous buck powir+ tm chipset reference design using ir3637spbf pwm & driver ic and irf7823pbf & irf7832zpbf so-8 mosfets by steve oknaian, senior applications engineer table of contents page introducti on ..........................................................................................2 design de tails ......................................................................................2 start-up pr ocedure ..............................................................................3 layout consi derati ons .........................................................................4 circuit sche matic .................................................................................5 complete bill of materi als.....................................................................6 pcb layout s .........................................................................................7-8 electrical efficien cy & power loss .......................................................9 thermal performanc e & bode plot.......................................................10 input & output ri pple wave forms........................................................11 load step wave forms..........................................................................12 power up & power down wave forms..................................................13 short circuit waveform s ......................................................................14 irpp3637-xxa reference de sign selector table ................................14 www.irf.com 1 rd# downloaded from: http:///
introduction the irpp3637- 12a is an optimized powir+ tm chipset reference design, targeted at low cost, low-to-medium power synchronous buck applications up to 12a output current. the IRPP3637-12A uses international rectifiers ir3637spbf single channel pwm controller in an 8-pin soic and irf7823pbf & irf7832zpbf so-8 mosfets. the irf7823pbf is utilized as a high side control fet, and the irf7832zpbf is utilized as a low side synchronous fet. there is an option to also populate the mosfet sockets with small can directfet? mosfets to meet different design goal objectives. this reference design has built-in power design expertise regarding component selection and pcb layout, and is representative of a realistic final embedded synchronous buck design, intended to simplify the design in effort without unnecessary design iterations. the design is optimized for 12v input and 1.8v output @ 12a and 400khz switching frequency, including considerations on layout and passive & magnetic component selection. the IRPP3637-12A delivers the complete 12a design in less than 1.5in 2 board area at up to 84.2% full load electrical efficiency and up to 85.1% peak efficiency. international rectifier also offers the powir+ chipset on-line design tool (http://powirplus.irf.com) allowing the customization of the IRPP3637-12A reference design to meet individual requirements. based on specific inputs, the powir+ chipset on-line design tool will provide a tailored schematic and bill of materials, from which the engineer can run a full suite of on-line design simulations, and then order the fully assembled and tested customized reference design (see details on page 14). design details the IRPP3637-12A reference design is optimized for an input voltage range of 12v+/-10% and an output voltage of 1.8v at a maximum of 12a load current, using the irf7823pbf and irf7832zpbf so-8 mosfets. this chipset is operated at 400khz switching frequency to allow a good trade off with size and performance at the specified operating conditions. all the essential components that contribute to a low cost compact solution are enclosed by the rectangular box shown on the pcb, showing a total solution size of 1.3 x 1.2 (1.5 sq). the electrical connection diagram is shown in figure 1 and the corresponding circuit schematic is shown in figure 2. figure 1: IRPP3637-12A elec trical connection diagram input/output connections j1: input power connection terminal j2: input power return preferred connection terminal j3: output power return preferred connection terminal j4: output power connection terminal +12v (j1) +12v rtn (j2) +1.8v vout (j4) +1.8v vout rtn (j3) +12v external vc bias. (optional) (j5) +12v external vc bias rtn (j6) www.irf.com 2 rd# downloaded from: http:///
j5: external bias power connection terminal. this terminal is unused for standard reference design configuration. j6: external bias power return preferred connection terminal. this terminal is unused for standard reference design configuration. start-up procedure the 12v input power is connected between terminals j1 and j2 and the 1.8v, 12a output power is obtained through terminals j3 and j4. the v cc and v c pins are the low side driver and high side driver power input pins respectively. the v cc pin also includes the housekeeping power of the pwm controller. an under-voltage lockout (uvlo) feature is associated with each of these pins, which is set to 4.2v for v cc and 3.3v for v c . a charge pump circuit comprised of c14, d1, and c16 applies adequate voltage to the v c pin to allow fast driving capability, hence reducing the switching losses of the control fet (q1). a 25 ? resistor (r11 in parallel with r12) is added in series with the charge pump circuit to maintain the v c voltage below 20v to reduce the temperature of the pwm controller ic. upon application of the input power, the output starts ramping up to regulation within 4ms. the ramping time can be adjusted through the soft start capacitor c5. the output voltage of the synchronous buck regulator is set to 1.8v using the internal 0.8v reference voltage. the following equations are used to calculate the mosfet power loss. refer to the irf7823pbf and irf7832zpbf datasheets to select the parametric values of the power loss equations terms. control fet losses: eq (1): sw in ossq dd gq in g sw o dn dq q q f v q v q v i q i r r rms i p ).. . . .( . . 1 1 1 1 1 2 1 1 + + + = synchronous fet losses: eq (2): sw in rrq dd gq in ossq dn dq q q f v q v q v q r r rms i p . . . . 2 . . 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? + + + = deadtime losses: eq (3): sw do sd td f ti v p ... = total fet losses: eq (4): td q q total fet p p p p + + = 2 1 _ where, i q1rms and i q2rms are the rms currents for control and sync fets respectively, in amps i o is the output load current in amps r d is the r dson in ohms of the fets and r dn is the normalized r dson factor vs. temperature extracted from the mosfet datasheets. q sw is the fet switch charge in nc v in is the input voltage of the sync buck converter q g is the total gate charge in nc. v dd is the fet drive voltage, which is 8v. i g is the drive current which is 0.25a. q oss is the fet output charge in nc. q rr is the sync fet internal body diode reverse recovery charge in nc v sd is the sync fet internal body diode forward voltage drop in volts. if an external schottky diode is used, then v sd needs to be the forward voltage drop of the schottky diode. f sw is the switching frequency of the sync buck converter in hertz. td is the dead time caused by the pwm controller ic in seconds. this parameter is specified in ir3637spbf datasheet. www.irf.com 3 rd# downloaded from: http:///
for design calculations related to programming the output voltage and the soft start time, selection of input/output capacitors and output inductor and control loop compensation, refer to the guidelines outlined in the ir3637spbf pwm controller datasheet. ir's online design tool powir + should be used to customize a design for applications outside the standard 12v+/- 10% input range and 1.8v output, and for varied design goal objectives. layout considerations the IRPP3637-12A reference design pcb layout offers compact design with minimum parasitics at 400khz switching frequency. the board is designed with 4 layers using 1 oz copper weight per layer. figures 3a through 3d represent the layout of each layer. to minimize the parasitics, the following was observed: 1. the switch node connection path is made as short as possible by placing the output inductor l1 close to the drain of the synchronous fet. 2. the input decoupling 10uf ceramic capacitors c3 & c4, are placed across the drain of the control fet and the ground plane. the 680f electrolytic capacitor c1 represents the input bulk capacitance of the synchronous buck regulator. 3. a solid ground plane is furnished in mid-layer 2. the connection of the signal ground to power ground is done at a single point in the bottom layer as shown in figure 3d. 4. the feedback track from the output v out to fb pin of the ic is routed as far away from noise generating traces as possible in mid-layer 2 as shown in figure 3c. www.irf.com 4 rd# downloaded from: http:///
figure 2: schematic diagram for IRPP3637-12A reference design www.irf.com 5 rd# downloaded from: http:///
qty ref designator description size mfr part number 1c 6 capacitor, ceramic, 68pf, 50v,npo, 5% 0603 koa npo0603httd680j 1c 7 capacitor, ceramic, 6.8nf,50v,x7r 0603 koa x7r0603httd682k 3 c5, c14, c16 capacitor, ceramic, 0.1f, 50v, x7r, 10% 0603 tdk c1608x7r1h104k 1c 1 5 capacitor, ceramic, 1.0f, 16v, x5r, 10% 0603 tdk c1608x7r1c105k 2 c3, c4 capacitor, ceramic, 10uf, 16v, x5r, 20% 1206 tdk c3216x7r1c106m 2 c11, c12 capacitor, ceramic, 10uf, 6.3v, x5r, 20% 1206 tdk c3216x5r0j106m 1c 1 capacitor, aluminum electrolytic,680uf,16v 8mm x 16mm sanyo 16me680wgl 2c 9 , c 1 0 capacitor, aluminum electrolytic,1200uf,6.3v 8mm x 16mm sanyo 6me1200wg 1 d3 schottky diode, 30v,200ma sot23 irf bat54 1 d1 schottky diode, 30v,200ma sot23 irf bat54s 1 d2 schottky diode, 40v,1.5a d64 irf 10mq040n 3j 1 , j 4 , j 5 red banana jacks-insulated solder terminal 4.44mm johnson 108-0902-001 3j 2 , j 3 , j 6 black banana jacks-insulated solder terminal 4.44mm johnson 108-0903-001 4 j1, j4, j5, j6 pan head slotted,screw 1/2" - mcmaster-carr 91792a081 2 j2, j3 pan head slotted,screw 1/4" - mcmaster-carr 91792a077 6 j1, j2, j3, j4, j5, j6 machine screw hex nuts - mcmaster-carr 91841a003 1l 1 1.2uh,22a,2.5m ? 11.5mmx10mmx5.5mm delta electronics mpl1055-1r2ir 1r 8 resistor,thick film, 0 ? 0805 rohm mcr10ezhj000 1r 1 0 resistor,thick film, 0 ? 0603 rohm mcr03ezhj000 1r 5 resistor,thick film,10 ?, 5% 1206 dale crcw1206-100jrt1 1r 6 resistor,thick film,20 ? , 1% 0603 koa rk73h1jltd20r0f 2 r11,r12 resistor,thick film,49.9 ? , 1% 1206 koa rk73h2b49r9f 1r 1 resistor,thick film,11.5k ? , 1% 0603 koa rk73h1jltd1152f 1r 3 resistor,thick film,11k ? , 1% 0603 koa rk73h1jltd1102f 1r 2 resistor,thick film,14k ? , 1% 0603 koa rk73h1jltd1402f 1q 1 n-fet,30v,8.7m ?,9.1 nc so-8 ir irf7823pbf 1q 2 n-fet,30v,3.8m ?, 30nc so-8 ir irf7832z 1 u1 pwm controller so-8 ir ir3637spbf 6 c2, c8, c13, r4, r7, not installed table 1 C complete bill of materials for IRPP3637-12A reference design www.irf.com 6 rd# downloaded from: http:///
figure 3a: IRPP3637-12A reference design top layer placement and layout. figure 3b: IRPP3637-12A reference design mid-layer1 ground plane www.irf.com 7 rd# downloaded from: http:///
figure 3c: IRPP3637-12A reference design mid-layer2 layout. directfet s-can pads placed on the bottom layer figure 3d: IRPP3637-12A reference design bottom layer layout. www.irf.com 8 rd# downloaded from: http:///
demoboard efficiency irpp3637s-12a 12vin, 1.8vout, 400khz, 25 0 c, 150lfm 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 024681 0 load current (amps) efficiency 1 2 figure 4a: IRPP3637-12A reference design electrical efficiency demoboard power loss irpp3637s-12a 12vin, 1.8vout, 400khz, 25 0 c, 150lfm 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 024681 0 load current (amps) power loss (watts) 1 2 figure 4b: IRPP3637-12A reference design power loss curve www.irf.com 9 rd# downloaded from: http:///
sync fet irf7832zpbf t c = 72 0 c u1 ic -ir3637s t c =75 0 c output inductor control fet irf7823pbf t c = 57 0 c vin=12v, vo=1.8v, io=12a t a = 25 0 c 150 lfm figure 5: IRPP3637-12A reference design thermograph at 12a load phase ph margin =61 0 f o = 40khz gain figure 6: IRPP3637-12A reference design bode plot of the control loop at 12a load. www.irf.com 10 rd# downloaded from: http:///
figure 7: input ripple, i o =12a figure 8: output ripple, i o =12a www.irf.com 11 rd# downloaded from: http:///
figure 9: output voltage undershoot due to 1a to 12a load step, di/dt=2.5a/s figure 10: output voltage overshoot due to 12a to 1a load step, di/dt=2.5a/s www.irf.com 12 rd# downloaded from: http:///
figure 11: power up. ch1=v , ch2=v out , ch3=soft start in out in figure 12: power down. ch1=v , ch2=v , ch3=soft start www.irf.com 13 rd# downloaded from: http:///
figure 13: output short circuit protection. ch1=v out , ch4=i out 10a/div v in v out i out max power efficiency inripple v outripple line regulation load regulation v (v) (v) (a) (w) ( %), 25 0 c, 150 lfm (mvp-p) (mvp-p) (%) (%) 12v 1.8v 12a 22w 510mv 34mv 0.05% 0.125% 85% table 2 C IRPP3637-12A reference design performance summary (all values are typical) part number input voltage output voltage output current switching frequency power semi bom delivery time comments irpp3637-06a 5v 1.25v 6a 600khz ir3637as (so-8), irf8910 (dual so-8) IRPP3637-12A 12v 1.8v 12a 400khz ir3637s (so-8), irf7823 (so-8), irf7832z (so-8) option to populate s-can directfets irpp3637-18a 12v 3.3v 18a 400khz ir3637s (so-8), irlr8713 (d-pak), irlr7843 (d-pak) custom irpp3637-06a up to 6a custom IRPP3637-12A up to 12a custom irpp3637-18a up to 18a standard reference designs fixed bom customizable reference designs via powir+ chipset on-line design tool at http://powirplus.irf.com various 3.0v to 13.2v 0.8v to 5.0v 400khz or 600khz 24-48hrs 1-2wks table 3 C complete irpp3637-xxa reference design selector table www.irf.com 14 rd# downloaded from: http:///

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