supertex inc. supertex inc. www.supertex.com hv7620 doc.# dsfp-hv7620 c112213 features ? hvcmos ? technology ? 5.0v logic and 12v supply rail ? output voltage up to +200v ? low power level shifting ? source/sink current minimum 50ma ? 40mhz equivalent data rate ? latched data outputs ? forward and reverse shifting options (dir pin) ? chip select ? polarity function functional block diagram 40mhz, 32-channel serial to parallel converter with push-pull outputs general descriptionthe hv7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. this device has been designed for use as a driver for color ac plasma displays. the device has 4 parallel 8-bit shift registers permitting data rates four times the speed of one. the data is clocked in simultaneously on all four data inputs with a single clock. data is shifted in on a low to high transition of the clock. the latches and control logic perform the output enable function. the dir pin causes clockwise (cw) shifting of the data when connected to vdd1, and counterclockwise (ccw) shifting when connected to lvgnd. operation of the shift register is not affected by the le (latch enable) input. transfer of data from the shift registers to the latches occurs when the le input is high. data is stored in the latches when le is low. the current source on the logic inputs provides active pull up when the input pins are open. 8 8 8 8 le bla cs pol clk hv out a1 hv out b1 hv out c1 hv out d1 d in a d out a blb dir blc bld hv out a8 hv out b8 hv out c8 hv out d8 d in b d out b d in c d out c d in d d out d qa1 8-bit latches qa8 qb1 8-bit latches qb8 qc1 8-bit latches qc8 8-bi t shift register 8-bi t shift register 8-bi t shift register 8-bi t shift register qd1 8-bit latches qd8 downloaded from: http:///
2 hv7620 supertex inc. www.supertex.com doc.# dsfp-hv7620 c112213 absolute maximum ratings parameter value supply voltage, v dd1 -0.5v to +14v supply voltage, v dd2 -0.5v to +14v supply voltage, v pp -0.5v to +225v logic input levels -2.0v to v dd1 + 2.0v continuous total power dissipation 1 1200mw operating temperature range -40c to +85c storage temperature range -65c to +150c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. notes: 1. for operation above 25c ambient derate linearly to maximum operating temperature at 20mw/c. recommended operating conditions sym parameter min max units v dd1 logic supply voltage 4.5 v dd2 v v dd2 12v supply voltage 10.8 13.2 v v pp high voltage supply voltage 50 200 v v ih high-level input voltage v dd1 -0.5v v dd1 v v il low-level input voltage 0 0.5 v f clk clock frequency v dd1 = 5.0v - 10 mhz v dd1 = 12v - 5 mhz t a operating temperature range -40 +85 c i od allowable pulsed current through output diodes 1 - 500 ma i gnd(vpp) allowable pulsed v pp or hvgnd current 1 - 16 a v pp(slew) slew rate of v pp - 340 v/s notes: 1. the current pulse width = 500ns, duty cycle = 5%. pin configuration 1 64 product marking l = lot number yy = year sealed ww = week sealed c = country of origin a = assembler id = ?green? packaging top marking hv7620pg llllllllll yyww cccccccc aaa 64-lead pqfp (3-sided) 64-lead pqfp (3-sided) (top view) package may or may not include the following marks: si or ordering information / availability part number package option packing HV7620PG-G 64-lead pqfp (3-sided) 66/tray typical thermal resistance package ja 64-lead pqfp 41 o c/w -g denotes a lead (pb)-free / rohs compliant package downloaded from: http:///
3 hv7620 supertex inc. www.supertex.com doc.# dsfp-hv7620 c112213 dc electrical characteristics(over operating supply voltages and temperature, unless otherwise noted, v dd1 = 5.0v, v dd2 = 12v, v pp = 200v and t j = 25c) sym parameter min max units conditions i dd1 v dd1 supply current - 5.0 ma f clk = 10mhz i dd2 v dd2 supply current - 20 ma v dd2 = 13.2v, f clk = 10mhz i pp high voltage supply current - 2.0 ma all outputs high or low i dd1q quiescent v dd1 supply current - 100 a all input = v dd1 i dd2q quiescent v dd2 supply current - 100 a all input = v dd1 v oh high-level output hv out 185 - v i o = -50ma data out v dd -1 - i o = -100a v ol low-level output hv out - 20 v i o = +50ma data out - 1.0 i o = +100a i ih high-level logic input current - 1.0 a v in = v dd1 i il low-level logic input current - -10 a v in = 0v v gg hvgnd to lvgnd voltage difference -1.0 1.0 v --- ac electrical characteristics(logic signal inputs and data inputs have t r , t f 5ns. v dd1 = 5.0v or 12v, v dd2 = 12v, v pp = 200v and t j = 25c) sym parameter min max units conditions f clk clock frequency v dd1 = 5.0v - 10 mhz per register, c l = 15pf v dd1 = 12v - 5.0 t wl , t wh clock width high or low 40 - ns --- t su data set-up time before clock rises 20 - ns --- t h data hold time after clock rises 20 - ns --- t on , t off time from latch enable to hv out - 275 ns c l = 15pf t wle le pulse width 25 - ns --- t dle delay time clock to le low to high 50 - ns --- t sle le set-up time before clock rises 20 - ns --- t dlf, t dln bl or cs low to high to hv out - 250 ns --- t cof, t con clock to hv out - 275 ns --- t dlh delay time clock to data low to high v dd1 = 5.0v - 250 ns c l = 15pf v dd1 = 12v - 100 t dhl delay time clock to data high to low v dd1 = 5.0v - 250 ns c l = 15pf v dd1 = 12v - 100 downloaded from: http:///
4 hv7620 supertex inc. www.supertex.com doc.# dsfp-hv7620 c112213 input and output equivalent circuits switching waveforms vdd1 input logic inputs vdd1 vpp hv out vdd2 lvgnd lvgnd hvgnd data out logic data output high voltage outputs clk data input 50% 50% 50% 50% t su t h t wl t f t wh t r 90% 10% 50% 90% 10% 50% t dle t wle t sle 10% 90% t off le t on v ih v il v ih v il v ih v il v oh v ol v oh v ol hv out hv out 50% 50% 50% 50% t dhl t cof t con t dlh data valid v oh v ol v oh v ol data output 10% t dlf 90% t dln v ih v il v oh v ol bla, blb, blc, bld, or cs hv out 50% downloaded from: http:///
5 hv7620 supertex inc. www.supertex.com doc.# dsfp-hv7620 c112213 function table function inputs hv out d in a d in b d in c d in d clk le dir bla blb blc bld cs pol a b c d all o/p high x x x x x x x x x x x l l h h h h all o/p low x x x x x x x x x x x l h l l l l a ? outputs low x x x x x x x l x x x x h l * * * normal polarity x x x x x x x h h h h h h no inversion outputs inverted x x x x x x x h h h h h l inversion transparent mode h l l l h x h h h h h h h l l l data stored x x x x x l x h h h h h h stored data shift cw a x x x x h h h h h h h x a n a n+1 b n b n+1 c n c n+1 d n d n+1 shift ccw b x x x x h l h h h h h x a n a n-1 b n b n-1 c n c n-1 d n d n-1 notes: h = high level, l = low level, x = irrelevant, = low to high transition. * = dependent on previous stages state before the last clk for last le high. ? = blb, blc and bld will have similar effect on their respective output.power-up sequence: 1. gnd (hv, lv) 2. v dd1 3. v dd2 4. v pp 5. logic input signals to power down reverse the sequence above. downloaded from: http:///
6 hv7620 supertex inc. www.supertex.com doc.# dsfp-hv7620 c112213 pin function pin # function 1 hvgnd 2 vpp 3 hv out d8 4 hv out c8 5 hv out b8 6 hv out a8 7 hv out d7 8 hv out c7 9 hv out b7 10 hv out a7 11 hv out d6 12 hv out c6 13 hv out b6 14 hv out a6 15 hv out d5 16 hv out c5 pin # function 17 hv out b5 18 hv out a5 19 vpp 20 hvgnd 21 hvgnd 22 vdd2 23 blc 24 bld 25 le 26 d out d 27 d in d 28 d in c 29 d out c 30 pol 31 lvgnd 32 dir pin # function 33 cs 34 d out b 35 d in b 36 d in a 37 d out a 38 clk 39 bla 40 blb 41 vdd1 42 lvgnd 43 n/c 44 hvgnd 45 hvgnd 46 vpp 47 hv out d4 48 hv out c4 pin # function 49 hv out b4 50 hv out a4 51 hv out d3 52 hv out c3 53 hv out b3 54 hv out a3 55 hv out d2 56 hv out c2 57 hv out b2 58 hv out a2 59 hv out d1 60 hv out c1 61 hv out b1 62 hv out a1 63 vpp 64 hvgnd downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 7 hv7620 (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv7620 c112213 64-lead pqfp (3-sided) package outline (pg) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint symbol a a1 a2 b d d1 e e1 e l l1 l2 l3 1 dimen- sion (mm) min 2.80 0.25 2.55 0.30 22.25 19.80 17.65 13.80 0.80 bsc 0.73 1.95 ref 0.25 bsc 0.55 ref 0 o 5 o nom - - 2.80 - 22.50 20.00 17.90 14.00 0.88 3.5 o - max 3.40 0.50 3.05 0.45 22.75 20.20 18.15 14.20 1.03 7 o 16 o drawings not to scale.supertex doc. #: dspd-64pqfppg, version a080812. note: 1. a pin 1 identifier must be located in the index area indicated. the pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. the leads on this side are trimmed. 1 64 vi ew b side view top vi ew note 1 (index area d1/4 x e1/4) l3 note 2 seating plane gauge plane l l1 l2 view b seating plane a2 a a1 d e e1 d1 b e 1 downloaded from: http:///
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