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rev. 1.0 4/14 copyright ? 2014 by silicon laboratories SI53304 SI53304 1:6 l ow j itter u niversal b uffer /l evel t ranslator with 2:1 i nput m ux and i ndividual oe features applications description the SI53304 is an ultra low jitter six out put differential buffer with pin-selectable output clock signal format and individual oe. the SI53304 features a 2:1 mux with glitchless switching, making it ideal for redundant clocking applications. the SI53304 utilizes silicon laboratories' advanced cmos technology to fanout clocks from 1 to 725 mhz wit h guaranteed low ad ditive jitter, low skew, and low propagation delay variability. the SI53304 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. independent core and output bank supply pins provide integrated level translation without the need for external circuitry. functional block diagram ? 6 differential or 12 lvcmos outputs ? ultra-low additive jitter: 45 fs rms ? wide frequency range: 1 to 725 mhz ? any-format input with pin selectable output formats: lvpecl, low power lvpecl, lvds, cml, hcsl, lvcmos ? 2:1 mux with hot-swappable inputs ? glitchless input clock switching ? synchronous output enable ? individual output enable ? independent v dd and v ddo : 1.8/2.5/3.3 v ? 1.2/1.5 v lvcmos output support ? excellent power supply noise rejection (psrr) ? selectable lvcmos drive strength to tailor jitter and emi performance ? small size: 32-qfn (5x5 mm) ? rohs compliant, pb-free ? industrial temperature range: ?40 to +85 c ? high-speed clock distribution ? ethernet switch/router ? optical transport network (otn) ? sonet/sdh ? pci express gen 1/2/3 ? storage ? telecom ? industrial ? servers ? backplane clock distribution vdd power supply filtering vddo b oe[5:3] sfout b [1:0] oe[2:0] vddo a sfout a [1:0] clk_sel switching logic v ref vref generator /clk0 clk0 /clk1 clk1 bank a bank b patents pending ordering information: see page 28. pin assignments SI53304 gnd pad 21 20 19 18 17 23 22 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 7 8 5 6 4 2 3 1 clk_sel clk0 clk0 clk1 clk1 oe 4 v ref q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 v ddoa q5 oe 2 q5 gnd sfout a [1] sfout a [0] oe 3 sfout b [1] sfout b [0] v dd oe 0 oe 1 v ddob oe 5
SI53304 2 rev. 1.0 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1. universal, any-format i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2. input bias resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3. input clock voltage refere nce (vref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4. universal, any-format output buff er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5. glitchless clock i nput switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6. synchronous output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7. input mux and outp ut enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8. power supply (v dd and v ddox ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9. output clock terminati on options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.10. ac timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11. typical phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12. input mux noise isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.13. power supply noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1. 5x5 mm 32-qfn package di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.1. 5x5 mm 32-qfn package land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1. SI53304 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SI53304 rev. 1.0 3 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature t a ?40 ? 85 c supply voltage range* v dd lvds, cml 1.71 1.8 1.89 v 2.38 2.5 2.63 v 2.97 3.3 3.63 v lvpecl, low power lvpecl, lvcmos 2.38 2.5 2.63 v 2.97 3.3 3.63 v hcsl 2.97 3.3 3.63 v output buffer supply voltage* v ddox lvds, cml, lvcmos 1.71 1.8 1.89 v 2.38 2.5 2.63 v 2.97 3.3 3.63 v lvpecl, low power lvpecl 2.38 2.5 2.63 v 2.97 3.3 3.63 v hcsl 2.97 3.3 3.63 v *note: core supply v dd and output buffer supplies v ddo are independent. lvcmos clock input is not supported for v dd = 1.8v but is supported for lvcmos clock output for v ddox = 1.8v. lvcmos outputs at 1.5v and 1.2v can be supported via a simple resistor divider network. see ?2 .9.1. lvcmos output termination to support 1.5v and 1.2v? table 2. input clock specifications (v dd =1.8 v ? 5%, 2.5 v ? 5%, or 3.3 v ? 10%, t a =?40 to 85 c) parameter symbol test condition min typ max unit differential input common mode voltage v cm v dd =2.5v ? 5%, 3.3 v ? 10% 0.05 ? ? v differential input swing (peak-to-peak) v in 0.2 ? 2.2 v lvcmos input high volt- age v ih v dd =2.5v ? 5%, 3.3 v ? 10% v dd x 0.7 ? ? v lvcmos input low volt- age v il v dd =2.5v ? 5%, 3.3 v ? 10% ? ? v dd x 0.3 v input capacitance c in clk0 and clk1 pins with respect to gnd ?5?pf
SI53304 4 rev. 1.0 table 3. dc common characteristics (v dd =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit supply current i dd ?65100ma output buffer supply current (per clock output) @100 mhz (diff) @200 mhz (cmos) i ddox lvpecl (3.3 v) ? 35 ? ma low power lvpecl (3.3 v)* ? 35 ? ma lvds (3.3 v) ? 20 ? ma cml (3.3 v) ? 35 ? ma hcsl, 100 mhz, 2 pf load (3.3 v) ? 35 ? ma cmos (1.8 v, sfout = open/0), per output, c l =5pf, 200mhz ?5?ma cmos (2.5 v, sfout = open/0), per output, c l =5pf, 200mhz ?8?ma cmos (3.3 v, sfout = 0/1), per output, c l =5pf, 200mhz ?15?ma input clock voltage reference v ref v ref pin i ref = +/-500 ? a ? vdd/2 ? v input high voltage v ih sfoutx, clk_sel, oex 0.8 x vdd ??v input mid voltage v im sfoutx, 3-level input pins 0.45 x vdd 0.5 x vdd 0.55 x vdd v input low voltage v il sfoutx, clk_sel, oex ? ? 0.2 x vdd v internal pull-down resistor r down clk_sel, sfoutx ? 25 ? k ? internal pull-up resistor r up oex, sfoutx ? 25 ? k ? *note: low-power lvpecl mode supports an output termination scheme that will reduce overall system power.
SI53304 rev. 1.0 5 table 4. output characteristics (lvpecl) (v ddox = 2.5 v 5%, or 3.3 v 10%,ta = ?40 to 85 c) parameter symbol test condition min typ max unit output dc common mode voltage v com v ddox ?1.595 ? v ddox ?1.245 v single-ended output swing* v se 0.55 0.80 1.050 v *note: unused outputs can be left floating. do not short unused outputs to ground. table 5. output characteristics (low power lvpecl) (v ddox = 2.5 v 5%, or 3.3 v 10%,ta = ?40 to 85 c) parameter symbol test condition min typ max unit output dc common mode voltage v com r l = 100 ?? across qn and qn v ddox ? 1.895 v ddox ?1.275 v single-ended output swing v se r l = 100 ?? across qn and qn 0.25 0.60 0.85 v table 6. output characteristics?cml (v ddox =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit single-ended output swing v se terminated as shown in figure 9 (cml termination). 300 400 550 mv table 7. output characteristics?lvds (v ddox =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit single-ended output swing v se r l =100 ? across q n and q n 247 ? 490 mv output common mode voltage (v ddo =2.5v or 3.3v) v com1 v ddox = 2.38 to 2.63 v, 2.97 to 3.63 v, r l =100 ? across q n and q n 1.10 1.25 1.35 v output common mode voltage (v ddo =1.8v) v com2 v ddox = 1.71 to 1.89 v, r l =100 ? across q n and q n 0.85 0.97 1.25 v
SI53304 6 rev. 1.0 table 8. output characteristics?lvcmos (v ddox =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit output voltage high * v oh 0.75 x v ddox ?? v output voltage low * v ol ? ? 0.25 x v ddox v *note: i oh and i ol per the output signal format table for specific v ddox and sfoutx settings. table 9. output characteristics?hcsl (v ddox =3.3v 10%, t a = ?40 to 85 c)) parameter symbol test condition min typ max unit output voltage high v oh r l =50 ? to gnd 550 700 900 mv output voltage low v ol r l =50 ? to gnd ?150 0 150 mv single-ended output swing v se r l =50 ? to gnd 550 700 850 mv crossing voltage v c r l =50 ? to gnd 250 350 550 mv table 10. ac characteristics (v dd = v ddox =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit frequency f lvpecl, low power lvpecl, lvds, cml, hcsl 1?725mhz lvcmos 1 ? 200 mhz duty cycle note: 50% input duty cycle. d c 200 mhz, 20/80% ? t r /t f <10% of period (lvcmos) (12 ma drive) 40 50 60 % 20/80% t r /t f <10% of period (differential) 48 50 52 % minimum input clock slew rate sr required to meet prop delay and additive jitter specifications (20?80%) 0.75 ? ? v/ns notes: 1. hcsl measurements were made with receiv er termination. see figure 9 on page 18. 2. output to output skew specified for outputs with an identical configuration. 3. defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. measured for 156.25 mhz carrier frequency. sine-wave noise added to v ddox (3.3 v = 100 mv pp ) and noise spur amplitude measured. see ?a n491: power supply rejection for low- jitter clocks? for further details.
SI53304 rev. 1.0 7 output rise/fall time t r /t f lvds, 20/80% ? ? 325 ps lvpecl, 20/80% ? ? 350 ps hcsl 1 , 20/80% ? ? 280 ps cml, 20/80% ? ? 350 ps low-power lvpecl, 20/80% ? ? 325 ps lvcmos 200 mhz, 20/80%, 2pf load ??750ps minimum input pulse width t w 500 ? ? ps propagation delay t plh, t phl lvcmos (12ma drive with no load) 1250 2000 2750 ps lvpecl 600 800 1000 ps lvds 600 800 1000 ps output enable time t en f=1mhz ? 2500 ? ns f = 100 mhz ? 30 ? ns f = 725 mhz ? 5 ? ns output disable time t dis f=1mhz ? 2000 ? ns f = 100 mhz ? 30 ? ns f = 725 mhz ? 5 ? ns output to output skew 2 t sk lvcmos (12 ma drive to no load) ? 50 120 ps lvpecl ? 35 70 ps lvds ? 35 70 ps part to part skew 3 t ps differential ? ? 150 ps power supply noise rejection 4 psrr 10 khz sinusoidal noise ? ?65 ? dbc 100 khz sinusoidal noise ? ?63 ? dbc 500 khz sinusoidal noise ? ?60 ? dbc 1 mhz sinusoidal noise ? ?55 ? dbc table 10. ac characteristics (continued) (v dd = v ddox =1.8v ?? 5% , 2.5 v ? 5%, or 3.3 v ?? 10%,t a = ?40 to 85 c) parameter symbol test condition min typ max unit notes: 1. hcsl measurements were made with receiv er termination. see figure 9 on page 18. 2. output to output skew specified for outputs with an identical configuration. 3. defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. measured for 156.25 mhz carrier frequency. sine-wave noise added to v ddox (3.3 v = 100 mv pp ) and noise spur amplitude measured. see ?a n491: power supply rejection for low- jitter clocks? for further details.
SI53304 8 rev. 1.0 table 11. additive jitter, differential clock input v dd input 1,2 output additive jitter (fs rms, 12 khz to 20 mhz) 3 freq (mhz) clock format amplitude v in (single-ended, peak-to-peak) differential 20%-80% slew rate (v/ns) clock format typ max 3.3 725 differential 0.15 0.637 lvpecl 45 65 3.3 725 differential 0.15 0.637 lvds 50 65 3.3 156.25 differential 0.5 0.458 lvpecl 160 185 3.3 156.25 differential 0.5 0.458 lvds 150 200 2.5 725 differential 0.15 0.637 lvpecl 45 65 2.5 725 differential 0.15 0.637 lvds 50 65 2.5 156.25 differential 0.5 0.458 lvpecl 145 185 2.5 156.25 differential 0.5 0.458 lvds 145 195 notes: 1. for best additive jitter results, use the fastest slew rate possible. see ?an766: understanding and optimizing clock buffer?s additive jitter perf ormance? for more information. 2. ac-coupled differential inputs. 3. measured differentially using a balun at the phase noise analyzer input. see figure 1.
SI53304 rev. 1.0 9 figure 1. differential measurement method using a balun table 12. additive jitter, single-ended clock input v dd input 1,2 output additive jitter (fs rms, 12 khz to 20 mhz) 3 freq (mhz) clock format amplitude v in (single-ended, peak to peak) se 20%-80% slew rate (v/ns) clock format typ max 3.3 200 single-ended 1.70 1 lvcmos 4 120 160 3.3 156.25 single-en ded 2.18 1 lvpecl 160 185 3.3 156.25 single-ended 2.18 1 lvds 150 200 3.3 156.25 single-ended 2.18 1 lvcmos 4 130 180 2.5 200 single-ended 1.70 1 lvcmos 5 120 160 2.5 156.25 single-en ded 2.18 1 lvpecl 145 185 2.5 156.25 single-ended 2.18 1 lvds 145 195 2.5 156.25 single-ended 2.18 1 lvcmos 5 140 180 notes: 1. for best additive jitter results, use the fastest slew ra te possible. see ?an766: understanding and optimizing clock buffer?s additive jitter perfo rmance? for more information. 2. dc-coupled single-ended inputs. 3. measured differentially using a balun at the phase noise analyzer input. see figure 1. 4. drive strength: 12 ma, 3.3 v (sfout = 11). lvcmos jitter is measured single-ended. 5. drive strength: 9 ma, 2.5 v (sfout = 11). lvcmos jitter is measured single-ended. pspl 5310a clkx /clkx 50 50 balun 50ohm ag e5052 phase noise analyzer si533xx dut pspl 5310a clk synth sma103a balun
SI53304 10 rev. 1.0 table 13. thermal conditions parameter symbol test condition value unit thermal resistance, junction to ambient ? ja still air 49.6 c/w thermal resistance, junction to case ? jc still air 32.3 c/w table 14. absolute maximum ratings parameter symbol test condition min typ max unit storage temperature t s ?55 ? 150 ? c supply voltage v dd ?0.5 ? 3.8 v input voltage v in ?0.5 ? v dd + 0.3 v output voltage v out ??v dd + 0.3 v esd sensitivity hbm hbm, 100 pf, 1.5 k ? ? ? 2000 v esd sensitivity cdm ? ? 500 v peak soldering reflow temperature t peak pb-free; solder reflow profile per jedec j-std-020 ? ? 260 ? c maximum junction temperature t j ? ? 125 ? c note: stresses beyond those listed in this table may caus e permanent damage to the device. functional operation specification compliance is not implied at these conditi ons. exposure to maximum rating conditions for extended periods may affect device reliability.
SI53304 rev. 1.0 11 2. functional description the SI53304 is a low jitter, low skew 1:6 differential buffer with an integrated 2:1 input mux and individual oe control. the device has a universal input that accepts most common differential or lvcmos input signals. a clock select pin control is used to select th e active input clock. the selected clock input is routed to two independent banks of outputs. each output bank features control pi ns to select signal format setting and lvcmos drive strength. in addition, each clock ou tput has an independent oe pin for individual clock enable/disable. 2.1. universal, any-format input the universal input stage enab les simple interfacing to a wide variety of clock form ats, including lvpecl, low- power lvpecl, lvcmos, lvds, hcsl, and cml. tables 15 and 16 summarize the various ac- and dc-coupling options supported by the device. for the best high-sp eed performance, the use of differential formats is recommended. for both single-ended and differential input clocks, the fastest possible slew rate is recommended as low slew rates can increase the noise floor and de grade jitter performance. though not required, a minimum slew rate of 0.75 v/ns is recommended for differential fo rmats and 1.0 v/ns for single-ended formats. see ?an766: understanding and optimizing clock buffer?s additi ve jitter performance? for more information. figure 2. differential hcsl, lvpecl, low-pow er lvpecl, lvds, cml ac-coupled input termination figure 3. lvcmos dc-coupled input termination table 15. lvpecl, lvcmos, and lvds input clock options lvpecl lvcmos lvds ac-couple dc-couple ac-couple d c-couple ac-couple dc-couple 1.8 v n/a n/a no no yes no 2.5/3.3 v yes yes no yes yes yes table 16. hcsl and cml input clock options hcsl cml ac-couple dc-couple ac-couple dc-couple 1.8 v no no yes no 2.5/3.3 v yes (3.3 v) yes (3.3 v) yes no si533xx 0.1 f 0.1 f clkx /clkx 100 ? si533xx v dd 1 k ? cmos driver v term = v dd /2 clkx = 3.3 v or 2.5 v v ddo /clkx 50 rs 1 k ? v ref
SI53304 12 rev. 1.0 figure 4. differential dc-coupled input terminations v dd si533xx r 1 v ddo r 2 r 1 r 2 ?standard? lvpecl driver v term = v ddo ? 2v r 1 // r 2 = 50 ohm clkx = 3.3v or 2.5v v ddo 3.3v lvpecl: r 1 = 127 ohm, r 2 = 82.5 ohm 2.5v lvpecl: r 1 = 250 ohm, r 2 = 62.5 ohm dc coupled lvpecl termination scheme 1 /clkx 50 50 v dd si533xx 50 50 v term = v ddo ? 2v = 3.3v or 2.5v v ddo 50 50 ?standard? lvpecl driver clkx /clkx dc coupled lvpecl termination scheme 2 v dd si533xx 50 50 dc coupled lvds termination = 3.3v or 2.5v v ddo 100 standard lvds driver clkx /clkx v dd si533xx 50 50 dc coupled hcsl source termination scheme = 3.3v v ddo standard hcsl driver 50 50 33 33 clkx /clkx note: 33 ohm series termination is optional depending on the location of the receiver.
SI53304 rev. 1.0 13 2.2. input bias resistors internal bias resistors ensure a differential output low co ndition in the event that the clock inputs are not connected. the non-inverting input is biased with a 18.75 k ? pull-down to gnd and a 75 k ? pull-up to v dd . the inverting input is biased with a 75 k ? pull-up to v dd . figure 5. input bias resistors 2.3. input clock voltage reference (v ref ) the v ref pin is used to bias the input receiver when a di fferential input clock is terminated as a single-ended reference clock to the device. connect the single-ended input to either clk0 or clk1. use the recommended input termination and bias circuit as shown in figure 3. note that the vref pin should be left floating when lvcmos or differential clocks are used. figure 6. using voltage reference with single-ended input clock r pu clk0 or clk1 r pu r pu = 75 k ? r pd = 18.75 k ? r pd + ? v dd si533xx clkx /clkx v ref 100 nf
SI53304 14 rev. 1.0 2.4. universal, an y-format output buffer the highly flexible ou tput drivers supp ort a wide range of clock signal fo rmats, including lvpecl, low power lvpecl, lvds, cml, hcsl, and lvcmos. sfoutx[1] an d sfoutx[0] are 3-level inputs that can be pin- strapped to select the bank a and bank b clock signal fo rmats independently. this feature enables the device to be used for format translation in addition to clock distributi on, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. for emi reduction applications, four lvcmos drive strength options are available for each v ddo setting. table 17. output signal format selection sfoutx[1] sfoutx[0] v ddox =3.3v v ddox =2.5v v ddox =1.8v open* open* lvpecl lvpecl n/a 0 0 lvds lvds lvds 0 1 lvcmos, 24 ma drive lvcmos, 18 ma drive lvcmos, 12 ma drive 1 0 lvcmos, 18 ma drive lvcmos, 12 ma drive lvcmos, 9 ma drive 1 1 lvcmos, 12 ma drive lvcmos, 9 ma drive lvcmos, 6 ma drive open* 0 lvcmos, 6 ma drive lvcmos, 4 ma drive lvcmos, 2 ma drive open* 1 lvpecl low power lvpecl low power n/a 0 open* cml cml cml 1 open* hcsl n/a n/a *note: sfout x are 3-level input pins. tie low for ?0? setting. tie high for ?1? setting. when left open, the pin floats to v dd /2.
SI53304 rev. 1.0 15 2.5. glitchless cl ock input switching the input clock mux features glitchless switching between two valid input clocks. figure 7 illustrates that switching between input clocks does not generate ru nt pulses or glitches at the output. figure 7. glitchless input clock switch glitchless switching between 2 input clocks that are up to 10x different in frequency is supported. when a switchover to a new clock is made, th e output will disable low after two or three clock cycles of the previously- selected input clock. the outputs will re main low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newl y-selected input. in the case a switch over to an absent clock is made, the output will glitchlessly stop low and wait for edges of the newly selected cl ock. a switchover from an absent clock to a live clock will also be glitchless. no te that the clk_sel inpu t should not be toggled faster than 1/250th the frequency of the slower input clock. 2.6. synchronous output enable this buffer features a synchronous output enable (disable ) feature. output enable is sampled and synchronized on the falling edge of the input clock. this feature prevents runt pulses from being generated when the outputs are enabled or disabled. when oe is low, q is held low and q is held high for differential output formats. for lvcmos output format options, both q and q are held low when oe is set low. the device outputs are enabled when the output enable pin is unconnected. see table 10, ?ac ch aracteristics,? on page 6 for output enable and output disable times. clk1 clk0 clk_sel qn note 1 note 2 notes: 1. q n continues with clk0 for 2-3 falling edges of clk0. 2. q n is disabled low for 2-3 falling edges of clk1 . 3. q n starts on the first rising edge after 1 + 2. note 3
SI53304 16 rev. 1.0 2.7. input mux and output enable logic two clock inputs for applications that need to select be tween one of two clock source s. the clk_sel pin selects the active clock input. the table below summarizes the in put and output clock based on the input mux and output enable pin settings. 2.8. power supply (v dd and v ddo x ) the device includes separate core (v dd ) and output driver supplies (v ddox ). this feature allows the core to operate at a lower voltage than v ddo , reducing current consumption in mixed supply applications. the core v dd supports 3.3 v, 2.5 v, or 1.8 v. each output bank has its own v ddox supply, supporting 3.3 v, 2.5 v, or 1.8 v. table 18. input mux and output enable logic clk_sel clk0 clk1 oe 1 q 2 llxhl lhxhh hxlhl hxhhh xxxll 3 notes: 1. output enable active high 2. on the next negative transition of clk0 or clk1. 3. single-end: q = low, q =low differential: q = low, q =high
SI53304 rev. 1.0 17 2.9. output clo ck termination options the recommended output clock termination options are shown below. figure 8. lvpecl output termination si533xx r 1 v ddo r 2 r 1 r 2 50 50 lvpecl receiver v term = v ddo ? 2v r 1 // r 2 = 50 ohm q qn = 3.3v or 2.5v v ddo 3.3v lvpecl: r 1 = 127 ohm, r 2 = 82.5 ohm 2.5v lvpecl: r 1 = 250 ohm, r 2 = 62.5 ohm dc coupled lvpecl termination scheme 1 v dd = v ddo si533xx 50 50 lvpecl receiver v term = v ddo ? 2v q qn = 3.3v or 2.5v v ddo 50 50 v dd = v ddo dc coupled lvpecl termination scheme 2 si533xx r 1 v ddo r 2 r 1 r 2 50 50 v bias = v dd ? 1.3v r 1 // r 2 = 50 ohm rb rb 0.1 uf ac coupled lvpecl termination scheme 1 q qn 0.1 uf = 3.3v or 2.5v v ddo lvpecl receiver = 3.3v or 2.5v v dd 3.3v lvpecl: r 1 = 82.5 ohm, r 2 = 127 ohm, rb = 120 ohm 2.5v lvpecl: r 1 = 62.5 ohm, r 2 = 250 ohm, rb = 90 ohm si533xx 50 50 rb rb 0.1 uf ac coupled lvpecl termination scheme 2 q qn 0.1 uf = 3.3v or 2.5v v ddo lvpecl receiver = 3.3v or 2.5v v dd 50 3.3v lvpecl: rb = 120 ohm 2.5v lvpecl: rb = 90 ohm v bias = v dd ? 1.3 v 50
SI53304 18 rev. 1.0 figure 9. lvds, cml, hcsl, and low-power lvpecl output termination 50 50 0.1 uf ac coupled lvds and low-power lvpecl termination 0.1 uf v dd 100 si533xx q qn v ddo = 3.3 v or 2.5 v or 1.8 v (lvds only) standard lvds receiver 50 50 dc coupled hcsl source termination v dd standard hcsl receiver 86.6 86.6 42.2 42.2 si533xx q qn = 3.3v v ddo 50 50 0.1 uf ac coupled cml termination 0.1 uf v dd 100 si533xx q qn = 3.3v or 2.5v or 1.8v v ddo standard cml receiver 50 50 dc coupled hcsl receiver termination v dd standard hcsl receiver 50 50 si533xx q qn = 3.3v v ddo 50 50 dc coupled lvds and low-power lvpecl termination v dd 100 standard lvds receiver si533xx q qn v ddo = 3.3 v or 2.5 v, or 1.8 v (lvds only)
SI53304 rev. 1.0 19 figure 10. lvcmos output termination 2.9.1. lvcmos output termination to support 1.5v and 1.2v lvcmos clock outputs are natively supp orted at 1.8, 2.5, and 3.3v. howe ver, 1.2v and 1.5v lvcmos clock outputs can be supported via a simple resi stor divider network that will translate the buffer?s 1.8v output to a lower voltage as shown in figure 11 below. figure 11. 1.5v and 1.2v lvcmos low-voltage output termination table 19. recommended lvcmos r s series termination sfoutx[1] sfoutx[0] r s (ohms) 3.3v 2.5v 1.8v 0 1 33 33 33 1 0 33 33 33 1 1 33 33 0 open0000 50 rs si533xx cmos driver zout cmos receivers zo 50 r 1 v ddox = ? 1.8v 1.5v lvcmos : r 1 = 43 ohms, r 2 = 300 ohms, i out = 12ma 1.2v lvcmos : r 1 = 58 ohms, r 2 = 150 ohms, i out = 12ma 50 r 1 lvcmos r 2 r 2
SI53304 20 rev. 1.0 2.10. ac timing waveforms figure 12. ac waveforms q n q m t sk t sk t plh t r t f q q clk q t phl output-output skew propagation delay rise/fall time vpp/2 vpp/2 vpp/2 vpp/2 20% vpp 80% vpp 80% vpp 20% vpp
SI53304 rev. 1.0 21 2.11. typical phase noise performance each of the following three figures shows three p hase noise plots superimpos ed on the same diagram. source jitter : reference clock phase noise. total jitter (se) : combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 khz to 20 mhz. total jitter (diff) : combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 khz to 20 mhz. the differential measurement as shown in each figure is made using a balun. see figure 1 on page 9. note: to calculate the total rms phase jitter when adding a buffer to your clock tree, use the root-sum-square (rss). the total jitter is a measure of the source plus the buffer's additive phase jitter. the addi tive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). figure 13. source jitter (156.25 mhz)
SI53304 22 rev. 1.0 figure 14. single-ended total jitter (312.5 mhz)
SI53304 rev. 1.0 23 figure 15. differential total jitter (625 mhz)
SI53304 24 rev. 1.0 2.12. input mux noise isolation the buffer?s input clock mux is designed to minimize cr osstalk between the clk0 and clk1. this improves phase jitter performance when clocks are pr esent at both the clk0 and clk1 in puts. figure 16 below is a measurement the input mux?s noise isolation. figure 16. input mux noise isolation 2.13. power supply noise rejection the device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world envir onments. this feature enables robust operation alongside fpgas, asics and socs and may reduce board-level filtering requirements. for more information, see ?an491: power supply rejection for low jitter clocks?. lvpecl output@ 156.25mhz; selected clk is active unselected clk is static lvpecl output@156.25mhz; selected clk is static unselected clk is active mux isolation = 61db
SI53304 rev. 1.0 25 table 20. pin description pin name type* description 1 oe0 i output enable?output 0 when oe = high, the q0 is enabled. when oe = low, q is held low and q is held high for differential formats. for lvcmos, both q and q are held low when oe is set low. this pin contains an internal pull-up resistor. 2 sfouta[1] i output signal format control pin for bank a three level input control. internally biased at v dd /2. can be left floating or tied to ground or v dd . 3 sfouta[0] i output signal format control pin for bank a three level input control. internally biased at v dd /2. can be left floating or tied to ground or v dd . 4q0 o output clock 0 (complement) 5 q0 o output clock 0 6 gnd o ground 7v dd p core voltage supply bypass with 1.0 f capacitor and place as close to the v dd pin as possi- ble. gnd pad 21 20 19 18 17 23 22 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 7 8 5 6 4 2 3 1 clk_sel clk0 clk0 clk1 clk1 oe4 vref q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 vddoa q5 oe2 q5 gnd sfouta[1] sfouta[0] oe3 sfoutb[1] sfoutb[0] vdd oe0 oe1 vddob oe5
SI53304 26 rev. 1.0 8 clk_sel i mux input select pin (lvcmos) clock inputs are switched without the introduction of glitches. when clk_sel is high, clk1 is selected. when clk_sel is low, clk0 is selected. clk_sel contains an internal pull-down resistor. 9 oe1 i output enable?output 1 when oe = high, the q1 is enabled. when oe = low, q is held low and q is held high for differential formats. for lvcmos, both q and q are held low when oe is set low. this pin contains an internal pull-up resistor. 10 clk0 i input clock 0 11 clk0 i input clock 0 (complement) when the clk0 is driven by a single-end input, connect clk0 to v dd /2. 12 oe2 i output enable?output 2 when oe = high, the q2 is enabled. when oe = low, q is held low and q is held high for differential formats. for lvcmos, both q and q are held low when oe is set low. oe2 contains an internal pull-up resistor. 13 oe3 i output enable?output 3 when oe = high, the q3 is enabled. when oe = low, q is held low and q is held high for differential formats. for lvcmos, both q and q are held low when oe is set low. oe3 contains an internal pull-up resistor. 14 clk1 i input clock 1 15 clk1 i input clock 1 (complement) when the clk1 is driven by a single-end input, connect clk1 to v dd /2. 16 oe4 i output enable?output 4 when oe = high, the q4 is enabled. when oe = low, q is held low and q is held high for differential formats. for lvcmos, both q and q are held low when oe is set low. this pin contains an internal pull-up resistor. 17 v ref o input clock reference voltage used to bias clk0 or clk1 clock input pins. v ref is required when a differential input clock is applied to the device and terminated as a single-ended reference. v ref may be left unconnected for lvcmos or differential clock inputs. see ?2.3. input clock voltage reference (vref)? for details. 18 v ddoa p output voltage supply?bank a (outputs: q0 to q2) bypass with 1.0 f capacitor and place as close to the v ddoa pin as possible. table 20. pin description (continued) pin name type* description
SI53304 rev. 1.0 27 19 v ddob p output voltage supply?bank b (outputs: q3 to q5) bypass with 1.0 f capacitor and place as close to the v ddob pin as possible. 20 q5 o output clock 5 (complement) 21 q5 o output clock 5 22 sfoutb[0] i output signal fo rmat control pin for bank b three level input control. internally biased at v dd /2. can be left floating or tied to ground or v dd . 23 sfoutb[1] i output signal fo rmat control pin for bank b three level input control. internally biased at v dd /2. can be left floating or tied to ground or v dd . 24 oe5 i output enable?output 5 when oe = high, the q5 is enabled. when oe = low, q is held low and q is held high for differential formats. for lvcmos, both q and q are held low when oe is set low. this pin contains an internal pull-up resistor. 25 q4 o output clock 4 (complement) 26 q4 o output clock 4 27 q3 o output clock 3 (complement) 28 q3 o output clock 3 29 q2 o output clock 2 (complement) 30 q2 o output clock 2 31 q1 o output clock 1 (complement) 32 q1 o output clock 1 gnd pad gnd gnd ground pad power supply ground and thermal relief. *pin types are: i = input, o = output, p = power, gnd = ground. table 20. pin description (continued) pin name type* description
SI53304 28 rev. 1.0 3. ordering guide part number package pb-f ree, rohs-6 temperature SI53304-b-gm 32-qfn yes ?40 to 85 ? c si53301/4-evb evaluation board yes ? notes: 1. to buy, go to http://www.supplier-direct.com/silabs/cart.as px?supplieruvid=63410000&partnumber=SI53304-b- gm&quantity=1&issample=0. 2. to sample, go to http://www.supplier-direct.com/silabs/cart.asp x?supplieruvid=63410000&partnumber=SI53304-b- gm&quantity=1&issample=1.
SI53304 rev. 1.0 29 4. package outline 4.1. 5x5 mm 32-qfn package diagram figure 17. SI53304 5x5 mm package diagram table 21. package dimensions dimension min nom max a 0.800.851.00 a1 0.00 0.02 0.05 b 0.180.250.30 c 0.200.250.30 d 5.00 bsc d2 2.00 2.15 2.30 e 0.50 bsc e 5.00 bsc e2 2.00 2.15 2.30 l 0.300.400.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. ?
SI53304 30 rev. 1.0 5. pcb land pattern 5.1. 5x5 mm 32-qfn package land pattern figure 18. SI53304 5x5 mm package land pattern table 22. pcb land pattern dimension min max dimension min max c1 4.52 4.62 x2 2.20 2.30 c2 4.52 4.62 y1 0.59 0.69 e 0.50 bsc y2 2.20 2.30 x1 0.20 0.30 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). cl earance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-pol ished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 2x2 array of 0.75 mm square openings on 1.15 mm pitch should be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components. ?
SI53304 rev. 1.0 31 6. top marking 6.1. SI53304 top marking 6.2. top marking explanation mark method: laser font size: 2.0 point (28 mils) center-justified line 1 marking: device part number 53304 line 2 marking: device revision/type b-gm line 3 marking: yy = year ww = work week corresponds to the year and work week of the mold date. r = die rev f=wafer fab manufacturing code. line 4 marking circle = 0.5 mm diameter lower-left justified pin 1 identifier a = assembly site i = internal code xx = serial lot number last four characters of the manu- facturing code from the assembly purchase order form. ?
SI53304 32 rev. 1.0 d ocument c hange l ist revision 0.4 to revision 1.0 ?? corrected front-page buffer block diagram. ?? improved performance specifications with more detail. ?? added additional information to clarify the use of the voltage reference feature. ?? added pin type description to table 20, ?pin description,? on page 25. ?? added low-voltage termination options for 1.2 v and 1.5 v lvcmos support. ?? clarified output cloc k bank a and bank b assignments.
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