? semiconductor components industries, llc, 2012 november, 2012 ? rev. 1 1 publication order number: nvd5490nl/d nvd5490nl power mosfet 60 v, 64 m , 17 a, single n ? channel features ? low r ds(on) to minimize conduction losses ? high current capability ? avalanche energy specified ? aec ? q101 qualified and ppap capable ? these devices are pb ? free, halogen free/bfr free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 60 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent r jc (notes 1 & 3) steady state t c = 25 c i d 17 a t c = 100 c 12 power dissipation r jc (note 1) t c = 25 c p d 49 w t c = 100 c 24 continuous drain cur- rent r ja (notes 1, 2 & 3) steady state t a = 25 c i d 5.0 a t a = 100 c 3.0 power dissipation r ja (notes 1 & 2) t a = 25 c p d 3.4 w t a = 100 c 1.7 pulsed drain current t a = 25 c, t p = 10 s i dm 71 a current limited by package (note 3) t a = 25 c i dmaxpkg 30 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 41 a single pulse drain ? to ? source avalanche energy (t j = 25 c, v dd = 30 v, v gs = 10 v, i l(pk) = 9.0 a, l = 1.0 mh, r g = 25 ) e as 41 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance maximum ratings parameter symbol value unit junction ? to ? case ? steady state (drain) r jc 3.1 c/w junction ? to ? ambient ? steady state (note 2) r ja 44 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 3. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. dpak case 369aa style 2 marking diagrams & pin assignment 60 v 64 m @ 10 v r ds(on) 17 a i d v (br)dss 85 m @ 4.5 v http://onsemi.com 1 2 3 4 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information n ? channel d (2,4) s (3) g (1) 1 gate 2 drain 3 source 4 drain yww 54 90nlg y = year ww = work week 5490l = device code g = pb ? free package
nvd5490nl http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 60 v zero gate voltage drain current i dss v gs = 0 v, v ds = 60 v t j = 25 c 1.0 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 9 a 46 64 m v gs = 4.5 v, i d = 9 a 66 85 forward transconductance g fs v ds = 15 v, i d = 20 a 15 s charges, capacitances & gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 25 v 365 pf output capacitance c oss 91 reverse transfer capacitance c rss 46 total gate charge q g(tot) v ds = 48 v, i d = 9 a v gs = 4.5 v 7.8 nc v gs = 10 v 14 threshold gate charge q g(th) v ds = 48 v, i d = 9 a v gs = 10 v 0.4 nc gate ? to ? source charge q gs 1.5 nc gate ? to ? drain charge q gd 5.4 nc gate resistance r g 7 switching characteristics (note 5) turn ? on delay time t d(on) v ds = 48 v, v gs = 4.5 v, i d = 9 a, r g = 10 9.4 ns rise time t r 57 turn ? off delay time t d(off) 24 fall time t f 35 turn ? on delay time t d(on) v ds = 48 v, v gs = 10 v, i d = 9 a, r g = 10 6.7 ns rise time t r 17 turn ? off delay time t d(off) 34 fall time t f 34 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 9 a t j = 25 c 0.97 1.2 v t j = 125 c 0.87 reverse recovery time t rr i s = 20.5 a dc , v gs = 0 v dc , di s /dt = 100 a/ s 25 ns charge time t a 20 discharge time t b 5.0 reverse recovery stored charge q rr 27 nc 4. pulse test: pulse width 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperatures.
nvd5490nl http://onsemi.com 3 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 5 4 3 2 1 0 0 5 10 15 20 25 30 5 4 3 2 0 5 10 15 20 25 30 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 10 9 8 7 6 5 4 0.04 0.05 0.06 0.07 0.09 0.10 0.12 0.13 20 15 10 5 0.04 0.05 0.06 0.07 0.08 0.09 0.10 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 150 125 100 50 25 0 ? 25 ? 50 0.5 1.0 1.5 2.0 2.5 60 50 40 30 20 10 10 100 1000 10,000 100,000 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 0.08 0.11 75 175 v gs = 0 v t j = 175 c t j = 125 c t j = 25 c v gs = 10 v v gs = 7.5 v v gs = 4.5 v v gs = 4.0 v v gs = 3.6 v v gs = 3.0 v t j = 25 c v ds 5 v t j = 100 c t j = ? 55 c i d = 17 a t j = 25 c t j = 25 c v gs = 10 v v gs = 4.5 v i d = 9 a v gs = 10 v
nvd5490nl http://onsemi.com 4 typical characteristics q gs figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 40 30 20 10 0 0 200 400 600 800 15 10 5 0 0 2 4 6 8 10 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1000 1.5 1.0 0.5 0 0 5 10 15 20 25 30 figure 11. maximum rated forward biased safe operating area figure 12. maximum avalanche energy vs. starting junction temperature v ds , drain ? to ? source voltage (v) t j , starting junction temperature ( c) 100 10 1 0.1 0.001 0.01 0.1 1 10 100 175 150 125 100 75 50 25 0 5 10 15 20 25 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) e as , single pulse drain ? to ? source avalanche energy (mj) v gs = 0 v t j = 25 c c iss c oss c rss v ds = 48 v i d = 9 a t j = 25 c v ds , drain ? to ? source voltage (v) q t q gd v dd = 48 v i d = 9 a v gs = 4.5 v t r t f t d(off) t d(on) v gs = 0 v t j = 25 c v gs = 10 v single pulse t c = 25 c 10 s 100 s 1 ms 10 ms dc r ds(on) limit thermal limit package limit i d = 17 a
nvd5490nl http://onsemi.com 5 typical characteristics figure 13. thermal response pulse time (sec) 1 0.1 10 0.01 100 0.00001 1000 0.000001 0.01 0.1 1 10 r(t) ( c/w) 0.001 0.0001 single pulse 50% duty cycle 20% 10% 5% 2% 1% ordering information order number package shipping ? NVD5490NLT4G dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nvd5490nl http://onsemi.com 6 package dimensions dpak case 369aa issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. nvd5490nl/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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