1. general description the 74hc1g04-q100; 74hct1g04-q100 is a single inverter. inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 2.0 v to 6.0 v ? input levels: ? for 74hc1g04-q100: cmos level ? for 74hct1g04-q100: ttl level ? symmetrical output impedance ? high noise immunity ? low power dissipation ? balanced propagation delays ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 74hc1g04-q100; 74hct1g04-q100 inverter rev. 1 ? 25 september 2013 product data sheet table 1. ordering information type number package temperature range name description version 74hc1g04gw-q100 ? 40 ? c to +125 ? c tssop5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm sot353-1 74hct1g04gw-q100 74HC1G04GV-Q100 ? 40 ? c to +125 ? c sc-74a plastic surface-mounted package; 5 leads sot753 74hct1g04gv-q100
74hc_hct1g04_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 25 september 2013 2 of 12 nxp semiconductors 74hc1g04-q100; 74hct1g04-q100 inverter 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram 6. pinning information 6.1 pinning 6.2 pin description table 2. marking codes type number marking [1] 74hc1g04gw-q100 hc 74hct1g04gw-q100 tc 74HC1G04GV-Q100 h04 74hct1g04gv-q100 t04 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram mna108 ay 2 4 mna109 4 1 2 mna110 a y fig 4. pin configuration + & |