 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| this is information on a product in full production. september 2013 doc id 13517 rev 8 1/32 1 l4993 low drop voltage regulator datasheet ? production data features operating dc supply voltage range 5.6v to 31v reset circuit sensing the output voltage down to 1v programmable reset pulse delay with external capacitor watchdog programmable watchdog timer with external capacitor enable input for en abling/disabling the watchdog functionality thermal shutdown and short circuit protection wide temperature range (t j = -40c to 150c) description the l4993 is a monolithic integrated 5v voltage regulator with a low drop voltage at currents up to 150 ma.the output voltage regulating element consists in a p-channel mos and the regulation is performed regardless of input voltage transients up to 40v. the high precision of the output voltage is obtained with a pre-trimmed reference voltage. the l4993 is protected against short circuit and an over-temperature protection switches off the device in case of extremely high power dissipa- tion. the l4993 watchdog is active when the enable is high. state of the art features like reset and watchdog make this device particularly suitable to supply micr oprocessor systems in automotive applications. max dc supply voltage v s 40v max output voltage tolerance ? v 0 +/-2% max dropout voltage v dp 400 mv output current i 0 150 ma quiescent current i qn 79 a (1) 1. typical value wi th watchdog disabled. ' ! 0 ' # & 4 so-8 ' ! 0 ' # & 4 so-20 table 1. device summary package order codes tube tape & reel so-8 l4993d l4993dtr so-20 (16+2+2) l4993md L4993MDTR www.st.com
contents l4993 2/32 doc id 13517 rev 8 contents 1 block diagram and pins descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 so-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 so-20 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 so-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 so-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 so-20 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 l4993 list of tables doc id 13517 rev 8 3/32 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. watchdog enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. so-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. so-20 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. so-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. so-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 list of figures l4993 4/32 doc id 13517 rev 8 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. output voltage vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. output voltage vs. vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. drop voltage vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. current consumption vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. current consumption vs. input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 8. current limitation vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. current limitation vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. short circuit current vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. short circuit current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. v wen_high vs. tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 13. v wen_low vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 14. vrhth vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15. vrlth vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16. vwhth vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 17. vwlth vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 18. icr & icwc vs. tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 19. idr & icwd vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 20. twop vs. tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 21. psrr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 22. load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 23. maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 24. l4993 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 25. behavior of output current versus regulated voltage vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 26. reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 27. watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 28. so-8 pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 29. rthj-amb vs. pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 19 figure 30. so-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 31. thermal fitting model of vreg in so-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 32. so-20 pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 33. rthj-amb vs. pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 22 figure 34. so-20 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 35. thermal fitting model of vreg in so-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 36. so-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 37. so-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 38. so-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 39. so-8 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 figure 40. so-20 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 41. so-20 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 l4993 block diagram and pins description doc id 13517 rev 8 5/32 1 block diagram and pins description figure 1. block diagram 7 k h u p d o s u r w h f w l r q : d w f k g r j 5 h v h w 9 r o w d j h u h i h u h q f h 7 k h u p d o s u r w h f w l r q 7 k h u p d o s u r w h f w l r q : d w f k g r j 5 h v h w 9 r o w d j h u h i h u h q f h 9 r o w d j h u h i h u h q f h 9 r o w d j h u h i h u h q f h 6 2 e s 6 / 6 c r 6 3 6 # 7 6 7 % n ) / ) 3 ) # 7 6 m ! 6 7 i ' n d ) w i ) 7 % n ) c r ) 2 e s ( " 1 ( 3 * block diagram and pins description l4993 6/32 doc id 13517 rev 8 figure 2. pins configuration table 2. pins description pin name so-8 (d) so-20 (md) function wen 1 1 watchdog enable input if high watchdog functionality is active gnd 2 4 ground reference gnd 5, 6, 15, 16 ground connected these pins to a heat spreader ground res 3 7 reset output. it is pulled down when output voltage goes below vo_th or frequency at wi is too low. leave floating if not used. vcr 4 10 reset timing adjust. a capacitor between vcr pin and gnd, sets the reset delay time (trd) vcw 5 11 watchdog timer adjust a capacitor between vcw pin and gnd, sets the time response of the watchdog monitor. wi 6 14 watchdog input. if the frequency at this input pin is too low, the reset output is activated. connect to ground if not used vo s 717 voltage regulator output block to ground with a capacitor >100nf (needed for regulator stability) vs 8 20 supply voltage block to ground directly at ic pin with a capacitor n.c. 2, 3, 8, 9, 12, 13, 18, 19 not connected . # . # ' . $ ' . $ 2 % 3 ' . $ . # # . # . . # 7 i ' . $ ' . $ 6 / 3 . # . # 6 3 6 c r 3 / ' ! 0 ' 2 ) 7 % . 6 c w ' . $ 2 % 3 c w 6 c r 6 7 i 6 / 3 6 3 3 / ' ! 0 ' 2 ) 8 & / l4993 electrical specifications doc id 13517 rev 8 7/32 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in ta b l e 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operat ing sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. 2.2 thermal data for details, please refer to section 4.1: so-8 thermal data and section 4.2: so-20 thermal data . table 3. absolute maximum ratings symbol parameter value unit v vsdc dc supply voltage -0.3 to 40 v i vsdc input current internally limited v vo dc output voltage -0.3 to 6 (1) 1. using the typical application sche matic with cout= 10 f and iout=0 a, when the regulator is switched-on, an overshoot exceeding 6 v could occur.this behavior does not impact the reliabi lity of the regulator. v i vo dc output current internally limited v wi watchdog input voltage -0.3 to v vo + 0.3 v v od open drain output voltage -0.3 to v vo + 0.3 v i od open drain output current internally limited v cr reset delay voltage -0.3 to v vo + 0.3 v v cw watchdog delay voltage -0.3 to v vo + 0.3 v v wen watchdog enable input voltage -0.3 to v vo +0.3 v t j junction temperature -40 to 150 c v esd esd voltage level (hbm-mil std 883c) 2 kv v esd esd voltage level (cdm aec-q100-011) 750 v table 4. thermal data (1) 1. the values quoted are for pcb fr4 area= 58mm x 58 mm, pcb thickness = 2mm, cu thickness = 35m , copper areas: so-8= 2 cm 2 , so-20= 6 cm 2 . symbol parameter value unit r th-jamb thermal resistance junction to ambient: so-8 so-20 130 51 c/w c/w electrical specifications l4993 8/32 doc id 13517 rev 8 2.3 electrical characteristics values specified in th is section are for v s =5.6v to 31v, t j = -40c to +150c unless otherwise stated. table 5. general pin symbol parameter test condition min. typ. max. unit vo v o_ref output voltage vs = 6 to 31v io = 1 to 150ma 4.9 5.0 5.1 v vo i short short circuit current vs = 13.5v (1) 1. see figure 25 . 150 280 400 ma vo i lim (2) 2. measured output current when the output voltage has dropped 100mv from its nominal value obtained at vs=13.5v and io= 75ma . output current limitation vs = 13.5v (1) 150 320 500 ma vs, vo v line line regulation voltage vs = 6 to 31v io = 1 to 150ma 25 mv vo v load load regulation voltage io = 1 to 150ma 25 mv vs, vo v dp (3) 3. vs-vo measured when the output voltage has dr opped 100mv from its nominal value obtained at vs=13.5v and io= 75ma . drop voltage io = 150ma 200 400 mv vs, vo svr ripple rejection fr = 100 hz (4) 4. guaranteed by design. 55 db vs, vo i qn_150 quiescent current vs=13.5v, io=150ma, wen = high 1.25 2 ma vs, vo i qn_50 quiescent current vs=13.5v, io= 50ma, wen = high 470 1000 a vs, vo i qn_1 quiescent current vs=13.5v, io< 1ma, wen = high 100 180 a vs, vo i qs quiescent current with watchdog regulator disabled vs=13.5v, io< 1ma, wen = low 79 125 a tw thermal protection temperature 150 190 c tw _ hy thermal protection temperature hysteresis 10 c l4993 electrical specifications doc id 13517 rev 8 9/32 table 6. reset pin symbol parameter test condition min. typ. max. unit res vres_l reset output low voltage r ext = 5k ? to vo, vo > 1v 0.4 v res i res_h reset output high leakage current v res = 5v 1 a res r_p_u pull up internal resistance with respect to vo 12 25 50 k ? res vo_th vo out of regulation threshold vs = 6 to 31v, io = 1 to 150ma 6% 8% 10% below v o_ref vcr vrlth reset delay circuit low threshold vs = 13.5v 10% 13% 16% v o_ref vcr vrhth reset delay circuit high threshold vs =13.5v 44% 47% 50% v o_ref vcr icr charge current vs = 13.5v 8 17.6 30 a vcr idr discharge current vs = 13.5v 8 17.6 30 a res trr_2 reset reaction time (1) 1. when vo becomes lower than 4v, t he reset reaction time decreases dow n to 2s assuring a faster reset condition in this particular case. vo = v o_ th -100mv 100 275 1000 s res trd reset delay time vs = 13.5v, ctr = 1nf 65 150 ms table 7. watchdog pin symbol parameter test condition min. typ. max. unit wi vih input high voltage vs = 13.5v 3.5 v wi vil input low voltage vs = 13.5v 1.5 v wi vih_hyst input hysteresis vs = 13.5v 500 mv wi ii pull down current vs = 13.5v 10 20 a vcw vwhth high threshold vs = 13.5v 44% 47% 50% v o_ref vcw vwlth low threshold vs = 13.5v 10% 13% 16% v o_ref vcw icwc charge current vs = 13.5v, vcw = 0.1v 4 8 14 a electrical specifications l4993 10/32 doc id 13517 rev 8 pin symbol parameter test condition min. typ. max. unit vcw icwd discharge current vs = 13.5v, vcw = 2.5v 1.0 2.13 4.5 a vcw twop watchdog period vs = 13.5v, ctw = 47nf 25 50 90 ms res twol watchdog output low time vs = 13.5v, ctw = 47nf 6 10.5 22 ms table 8. watchdog enable pin symbol parameter test condition min. typ. max. unit wen w en_low enable input low voltage 1 v wen w en_high enable input high voltage 3 v wen w en_hyst enable input hysteresis 500 800 1100 mv wen i leak pull down current wen = 5v 2 8 20 a table 7. watchdog (continued) l4993 electrical specifications doc id 13517 rev 8 11/32 2.4 electrical characteristics curves figure 3. output voltage vs. tj figure 4. output voltage vs. vs figure 5. drop voltage vs. output current figure 6. current consumption vs. output current figure 7. current consumption vs. input voltage figure 8. current limitation vs. tj -50 -25 0 25 50 75 100 125 150 tj(c ) 4,5 4,6 4,7 4,8 4,9 5 5,1 5,2 5,3 5,4 5,5 vo_ref (v) vs= 13.5v i0 = 75ma 0 5 10 15 20 25 30 35 vs (v ) 0 1 2 3 4 5 6 7 8 9 10 vo_ref (v) i 0 = 75 ma tj = 25 c -50 0 50 100 150 200 io (ma) 0 0,05 0,1 0,15 0,2 0,25 0,3 vdp (v) tj= 25 c tj= 125 c -50 0 50 100 150 200 io (ma) 0 300 600 900 1200 1500 iqn (a) vs= 13.5 v tj= 25 c en= high 0 5 10 15 20 25 30 35 vs (v ) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 iqn(a ) tj = 25 c en = high io = 1ma io =50ma io= 100ma -50 -25 0 25 50 75 100 125 150 tj(c ) 0 100 200 300 400 500 600 ilim (ma) vs= 13.5v electrical specifications l4993 12/32 doc id 13517 rev 8 figure 9. current limitation vs. input volt age figure 10. short circuit current vs. tj figure 11. short circuit current vs. input voltage figure 12. v wen_high vs. tj figure 13. v wen_low vs. tj figure 14. vrhth vs. tj 0 5 10 15 20 25 30 35 vs (v ) 200 225 250 275 300 325 350 ilim (ma) tj = 25 c tj = 125 c -50 -25 0 25 50 75 100 125 150 tj(c ) 0 100 200 300 400 500 600 ishort (ma) vs= 13.5v 0 5 10 15 20 25 30 35 vs (v ) 150 200 250 300 350 ishort (ma ) tj = 25 c tj = 150 c -50 -25 0 25 50 75 100 125 150 tj(c ) 1 1,5 2 2,5 3 3,5 4 vwen_high (v) vs= 5.6v to 31v -50 -25 0 25 50 75 100 125 150 tj(c ) 1,4 1,5 1,6 1,7 1,8 1,9 2 vwen_low (v) vs= 5.6v to 31v -50 -25 0 25 50 75 100 125 150 tj(c ) 30 35 40 45 50 55 60 vrhth (% vo_ref ) vs= 5.6v to 31v l4993 electrical specifications doc id 13517 rev 8 13/32 figure 15. vrlth vs. tj figure 16. vwhth vs. tj figure 17. vwlth vs. tj figure 18. icr & icwc vs. tj figure 19. idr & icwd vs. tj figure 20. twop vs. tj -50 -25 0 25 50 75 100 125 150 tj(c ) 0 10 20 30 40 50 vrlth (% vo_ref) vs= 5.6v to 31v -50 -25 0 25 50 75 100 125 150 tj(c ) 30 35 40 45 50 55 60 vwhth (% vo_ref ) vs= 5.6v to 31v -50 -25 0 25 50 75 100 125 150 tj(c ) 0 10 20 30 40 50 vwlth (% vo_ref) vs= 5.6v to 31v -50 -25 0 25 50 75 100 125 150 tj(c ) 0 5 10 15 20 25 30 icr & icwc (a) vs= 5.6v to 31v icr icwc -50 -25 0 25 50 75 100 125 150 tj(c ) 0 5 10 15 20 25 30 idr & icwd (a) vs= 5.6v to 31v idr icwd -50 -25 0 25 50 75 100 125 150 tj(c ) 20 30 40 50 60 70 80 twop (ms) vs= 5.6v to 31v ctw= 47nf electrical specifications l4993 14/32 doc id 13517 rev 8 2.5 test circuit and waveforms plot 2.5.1 load regulation figure 22. load regulation test circuit figure 21. psrr 0 10 20 30 40 50 60 70 80 0,1 1 10 100 1000 10000 frequency [khz] psrr [db] c 0 = 4.7f ' ! 0 ' 2 ) l4993 electrical specifications doc id 13517 rev 8 15/32 figure 23. maximum load variation response 0 , 0 0 e + 0 0 5 , 0 0 e - 0 5 1 , 00 0 0 e - 0 4 1 , 5 0 e - 0 4 2 , 0 0 e - 0 4 2 , 5 0 e - 0 4 3 , 0 0 e - 0 4 3 , 5 0 e - 0 4 4 , 0 0 e - 0 4 t i m e [ s ] v 0 [1 [ 1 v / d / d i v ] i 0 [ 50 5 0 m a / di d i v ] gapgri0007 3 g a p g r i 0 0 0 7 3 application information l4993 16/32 doc id 13517 rev 8 3 application information figure 24. l4993 application schematic note: the input capacitor cs > 200nf is necessary for the smoothing of line disturbances. the output capacitor c01 > 10 0nf is necessary for the stability of the regulation lo op. in order to damp output voltage oscillations during high load current surges, it is recommended put an additional electrolytic capacito r c02 > 10f at the output pin. 3.1 voltage regulator voltage regulator uses a p-channel transistor as a regulating element. with this structure, very low dropout voltage at current up to 500ma is obtained. the output voltage is regulated up to transient input supply voltage of 40v. no functional interruption due to over-voltage pulses is generated. a short circuit protection to gnd is provided. the voltage regulator watchdog functionality can be disabled by putting wen low. 7 k h u p d o s u r w h f w l r q : d w f k g r j 5 h v h w 9 r o w d j h u h i h u h q f h 7 k h u p d o s u r w h f w l r q 7 k h u p d o s u r w h f w l r q : d w f k g r j 5 h v h w 9 r o w d j h u h i h u h q f h 9 r o w d j h u h i h u h q f h 9 r o w d j h u h i h u h q f h 6 i 6 s 6 c w # s # t w 7 i 7 % n 6 c r # t r ' n d 2 e s # # 6 o ' ! 0 ' 2 ) l4993 application information doc id 13517 rev 8 17/32 figure 25. behavior of output current versus regulated voltage vo 3.2 reset the reset circuit supervises the output voltage vo. the vo_th reset threshold is defined with the in-ternal reference voltage and a resistor output divider. if the output voltage becomes lower than vo_th then res goes low with a reaction time trr. the reset low signal is guaranteed for an output voltage vo greater than 1v. when the output voltage becomes higher than vo_th then res goes high with a delay trd. this delay is obtained by an internal oscillator. the oscillator period is given by: tosc = [(vrhth-vrlth) x ctr] / icr + [(vrhth-vrlth) x ctr] / idr where: icr: is an internally generated charge current idr: is an internally generated discharge current vrhth, vrlth: are two voltages defined with the output voltage and a resistor output divider ctr: is an external capacitance. trd is given by: trd = 512 x tosc reset is active when en is high. 6 o 6 o ? r e f ) o u t ) s h o r t ) l i m 6 o 6 o ? r e f ) o u t ) s h o r t ) l i m ( " 1 ( $ ' 5 application information l4993 18/32 doc id 13517 rev 8 figure 26. reset timing diagram 3.3 watchdog a connected microcontroller is monitored by th e watchdog input wi. if pulses are missing, the reset output pin is set to low. the pulse sequence time can be set within a wide range with the external capacitor, ctw. the watchdog circuit discharges the capacitor ctw, with the constant current icwd. if the lower threshold vwlth is reached, a watchdog reset is generated. to prevent this the microcontroller must generate a positive edge during the discharge of the capacitor before the voltage has reached the threshold vwlth. in order to calculate the minimum time t, during which the micro-controller must output the positive edge, the following equation can be used: (vwhth-vwlth) x ctw = icwd x t every wi positive edge switches the current sour ce from discharging to charging. the same happens when the lower threshold is reached. when the voltage reaches the upper threshold, vwhth, the current switches from charging to discharging. the result is a saw-tooth voltage at the watchdog timer capacitor ctw. figure 27. watchdog timing diagram t r r t r r t r d 4 o s c 4 o s c 6 r h t h 6 r l t h 2 e s 6 c r 6 o 7 i 6 o u t ? t h ' ! 0 ' # & 4 2 e s 6 c w 7 i 6 w l t h 6 w h t h t w o l 4 w o p ' ! 0 ' 2 ) 6 w l t h l4993 package and pcb thermal data doc id 13517 rev 8 19/32 4 package and pcb thermal data 4.1 so-8 thermal data figure 28. so-8 pc board note: layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness = 2mm, cu thickness = 35m , copper areas: from minimum pad lay-out to 2cm 2 ). figure 29. r thj-amb vs. pcb copper area in open box free air condition * $ 3 * & ) 7 2 4 ( j ? a m b ? # 7 0 # " # u h e a t s i n k a r e a c m > 2 4 ( j ? a m b v s # u h e a t s i n k a r e a 2 4 ( j a m b ' ! 0 ' # & 4 package and pcb thermal data l4993 20/32 doc id 13517 rev 8 figure 30. so-8 thermal impedance junction ambient single pulse equation 1: pulse calculation formula where ? = t p /t figure 31. thermal fitting model of vreg in so-8 a t a d l a m r e h t " # 0 d n a e g a k c a 0 , 7 l p h v = 7 + ? & : & o o t p r i n t c m ' ! 0 ' 2 ) z th ? r th ? z thtp 1 ? ? ?? + ? = * $ 3 * & ) 7 l4993 package and pcb thermal data doc id 13517 rev 8 21/32 table 9. so-8 thermal parameter area/island (cm 2 )footprint2 r1 (c/w) 4.21 r2 (c/w) 2.11 r3 (c/w) 2 r4 (c/w) 41 r5 (c/w) 40 r6 (c/w) 58 40 c1 (w.s/c) 0.00029 c2 (w.s/c) 0.0024 c3 (w.s/c) 0.03 c4 (w.s/c) 0.04 c5 (w.s/c) 0.1 c6 (w.s/c) 1.05 2 package and pcb thermal data l4993 22/32 doc id 13517 rev 8 4.2 so-20 thermal data figure 32. so-20 pc board note: layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm,pcb thickness = 2mm, cu thickness=35 ? m , copper areas: from minimum pad lay-out to 6cm 2 ). figure 33. r thj-amb vs. pcb copper area in open box free air condition . * $ 3 * & ) 7 5 7 + m b d p e ? & : 3 & % & x k h d w v l q n d u h d f p a 5 7 + m b d p e y v & x k h d w v l q n d u h d 5 7 + m d p e ( " 1 ( $ ' 5 l4993 package and pcb thermal data doc id 13517 rev 8 23/32 figure 34. so-20 thermal impedance junction ambient single pulse equation 2: pulse calculation formula where ? = t p /t figure 35. thermal fitting model of vreg in so-20 = 7 + ? & : 7 l p h v & x f p & x i r r w s u l q w ( " 1 ( $ ' 5 z th ? r th ? z thtp 1 ? ? ?? + ? = * $ 3 * & ) 7 package and pcb thermal data l4993 24/32 doc id 13517 rev 8 table 10. so-20 thermal parameter area/island (cm 2 )footprint2 r1 (c/w) 4.21 r2 (c/w) 2.11 r3 (c/w) 2.2 r4 (c/w) 10 r5 (c/w) 15 r6 (c/w) 35 18 c1 (w.s/c) 0.00029 c2 (w.s/c) 0.0024 c3 (w.s/c) 0.015 c4 (w.s/c) 0.15 c5 (w.s/c) 1.5 c6 (w.s/c) 4 7 l4993 package and packing information doc id 13517 rev 8 25/32 5 package and packing information 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. so-8 package information figure 36. so-8 package dimensions table 11. so-8 mechanical data symbol millimeters min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b 0.28 0.48 c 0.17 0.23 ' ! 0 ' # & 4 package and packing information l4993 26/32 doc id 13517 rev 8 d (1) 4.80 4.90 5.00 e 5.80 6.00 6.20 e1 (2) 3.80 3.90 4.00 e1.27 h 0.25 0.50 l 0.40 1.27 l1 1.04 k0 8 ccc 0.10 1. dimensions d does not include mold flash, protrusions or gate burrs. mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. dimension ?e1? does not include interlead flash or pr otrusions. interlead flash or protrusions shall not exceed 0.25mm per side. table 11. so-8 mechanical data symbol millimeters min. typ. max. l4993 package and packing information doc id 13517 rev 8 27/32 5.2 so-20 package information figure 37. so-20 package dimensions table 12. so-20 mechanical data symbol millimeters min. typ. max. a 2.35 2.65 a1 0.10 0.30 b 0.33 0.51 c 0.23 0.32 d (1) 12.60 13.00 e 7.40 7.60 e1.27 h 10.0 10.65 h 0.25 0.75 l 0.40 1.27 ( " 1 ( $ ' 5 package and packing information l4993 28/32 doc id 13517 rev 8 5.3 so-8 packing information figure 38. so-8 tube shipment (no suffix) k0 8 ddd 0.10 1. ?d? dimension does not include mold flash, protusions or gat e burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. table 12. so-20 mechanical data (continued) symbol millimeters min. typ. max. # " ! ' ! 0 ' 2 ) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 l4993 package and packing information doc id 13517 rev 8 29/32 figure 39. so-8 tape and reel shipment (suffix ?tr?) 5.4 so-20 packing information figure 40. so-20 tube shipment (no suffix) ! # " ' ! 0 ' 2 ) base q.ty 40 bulk q.ty 800 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 package and packing information l4993 30/32 doc id 13517 rev 8 figure 41. so-20 tape and reel shipment (suffix ?tr?) base q.ty 1000 bulk q.ty 1000 a (max) 33 0 b (min) 1.5 c ( 0.2) 1 3 d 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 3 0.4 tape dimensions according to electronic ind us trie s a ss oci a tion (eia) s t a nd a rd 4 8 1 rev. a, fe b . 19 8 6 all dimen s ion s a re in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d (+ 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover t a pe end s t a rt no component s no component s component s 500mm min 500mm min empty component s pocket s sa led with cover t a pe. u s er direction of feed reel dimensions gapgri000 8 0 l4993 revision history doc id 13517 rev 8 31/32 6 revision history table 13. document revision history date revision changes june-2004 1 initial release. 18-jan-2007 2 updated table 5. , 6 , 7 and 8 . 01-jun-2007 3 document put in corporate technical literature template. updated table 4. 22-aug-2007 4 table 5: general : updated i short , i lim , i q, t rr2, v ih_hist parameters. 29-aug-2007 5 added list of tables and figures. added section 4: package and pcb thermal data . 08-apr-2008 6 document restructured. changed figure 1: block diagram . updated table 5: general : ? changed i short max value from 4000 ma to 400 ma ? changed i qn_150 typ. value from 1.45 ma to 1.25 ma ? changed i qn_50 typ. value from 538 a to 470 a ? changed i qn_1 typ. value from 120 a to 100 a. updated table 6: reset : ? corrected trd formula. updated table 7: watchdog : ? changed vwlth values in v o_ref percentages ? changed vwhth values in v o_ref percentages. added figure 24: l4993 application schematic . added section 2.4: electrical characteristics curves . added section 2.5: test circuit and waveforms plot . 09-mar-2012 7 updated table 3: absolute maximum ratings . 20-sep-2013 8 updated disclaimer. l4993 32/32 doc id 13517 rev 8 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
Price & Availability of L4993MDTR
 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |
