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sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 1 version 0.9 sn8p275x series user?s manual version 0.9 sn8p2754 sn8p2755 SN8P2758 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without furt her notice to any products herein to improve reliab ility, function or design. sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its paten t rights nor the rights of others. sonix products are not designed, intended, or authorized for us as co mponents in systems intended, for surgical implant into the body, or other applications intend ed to support or sustain life, or for any other app lication in which the failure of the sonix product could create a situation where personal injury or d eath may occur. should buyer purchase or use sonix p roducts for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subsidiari es, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reason able attorney fees arising out of, directly or indi rectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 2 version 0.9 amendent history version date description ver 0.1 nov. 2008 1. preliminary version first issu e ver 0.2 nov. 2008 1. modify package information. ver 0.3 nov. 2008 1. modify ice msp emulation. ver 0.4 feb. 2008 1. modify msp,package information . ver 0.5 apr. 2009 1. modify sop32 package size. ver 0.6 jun. 2009 1. update code option table. ver 0.7 nov. 2009 1. modify lqfp48 marking name 2. add avdd pin descriptment 3. modify dao as 7bit dac output in 1.4 pin description 4. fix typing error ver 0.8 may.2011 1. remove p33. ver 0.9 dec.2011 1. add qfn32 package.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 3 version 0.9 table of content amendent history............................................ ................................................... ............................ 2 1 1 1 product overview ................................................... ................................................... .............. 9 1.1 features......................................... ................................................... ....................................... 9 1.2 system block diagram ............................................ ................................................... ..... 10 1.3 pin assignment......................................... ................................................... ......................... 11 1.4 pin descriptions ....................................... ................................................... ........................ 14 1.5 pin circuit diagrams........................................... ................................................... ........... 15 2 2 2 central processor unit (cpu)....................... ................................................... ................. 16 2.1 memory map................................................ ................................................... ....................... 16 2.1.1 program memory (rom)............................... ................................................... ............ 16 2.1.2 reset vector (0000h) .................................... ................................................... ............. 17 2.1.3 interrupt vector (0008h)............................... ................................................... ......... 18 2.1.3.1 look-up table description..................... ................................................... ......... 19 2.1.4 jump table description .............................. ................................................... ............ 22 2.1.4.1 checksum calculation .......................... ................................................... .......... 24 2.1.5 code option table .................................. ................................................... .................. 25 2.1.6 data memory (ram).................................. ................................................... .................. 26 2.1.7 system register ....................................... ................................................... .................. 27 2.1.7.1 system register table ......................... ................................................... ............. 27 2.1.7.2 system register description ................... ................................................... ...... 27 2.1.7.3 bit definition of system register .............. ................................................... ... 28 2.1.7.4 accumulator ................................... ................................................... ..................... 32 2.1.8 program flag....................................... ................................................... ...................... 33 2.1.8.1 program counter............................... ................................................... ................. 34 2.1.9 h, l registers ...................................... ................................................... ........................ 36 2.1.10 y, z registers ...................................... ................................................... ......................... 38 2.1.10.1 x registers................................... ................................................... ....................... 38 2.1.11 r registers......................................... ................................................... .......................... 39 2.2 addressing mode............................................... ................................................... .............. 40 2.2.1 immediate addressing mode........................... ................................................... ...... 40 2.2.2 directly addressing mode............................. ................................................... ....... 40 2.2.3 indirectly addressing mode.......................... ................................................... ...... 40 2.3 stack operation .......................................... ................................................... .................... 41 2.3.1 overview........................................... ................................................... ............................ 41 2.3.2 stack registers...................................... ................................................... .................... 42
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 4 version 0.9 2.3.3 stack operation example ............................. ................................................... ......... 43 3 3 3 reset .............................................. ................................................... .............................................. 44 3.1 overview......................................... ................................................... .................................... 44 3.2 power on reset .............................................. ................................................... ................... 45 3.3 watchdog reset .............................................. ................................................... ................ 45 3.4 brown out reset.............................................. ................................................... ................ 46 3.4.1 brown out description ............................... ................................................... ........... 46 3.4.2 the system operating voltage decsription.............. ........................................ 47 3.4.3 brown out reset improvement......................... ................................................... ... 47 3.5 external reset .............................................. ................................................... .................. 49 3.6 external reset circuit ............................................ ................................................... .... 49 3.6.1 simply rc reset circuit ............................... ................................................... ..................... 49 3.6.2 diode & rc reset circuit .............................. ................................................... ................... 50 3.6.3 zener diode reset circuit ............................. ................................................... .................... 50 3.6.4 voltage bias reset circuit.............................. ................................................... ................... 51 3.6.5 external reset ic ................................... ................................................... ........................... 52 4 4 4 system clock ....................................... ................................................... ................................... 53 4.1 overview......................................... ................................................... .................................... 53 4.2 clock block diagram ............................................ ................................................... ....... 53 4.3 oscm register ........................................... ................................................... ........................ 54 4.4 system high clock.............................................. ................................................... ............ 55 4.4.1 internal high rc ................................... ................................................... .................... 55 4.4.2 external high clock................................ ................................................... ............... 55 4.4.2.1 crystal/ceramic............................... ................................................... ................... 56 4.4.2.2 rc............................................ ................................................... ..................................... 56 4.4.2.3 external clock signal ......................... ................................................... ........... 57 4.5 system low clock.............................................. ................................................... ............. 58 4.5.1 system clock measurement............................. ................................................... ..... 59 5 5 5 system operation mode .............................. ................................................... ...................... 60 5.1 overview......................................... ................................................... .................................... 60 5.2 system mode switching.......................................... ................................................... ...... 61 5.3 wakeup........................................... ................................................... ...................................... 63 5.3.1 overview........................................... ................................................... ............................ 63 5.3.2 wakeup time ........................................ ................................................... ........................ 63 5.3.3 p1w wakeup control register.......................... ................................................... ... 64 6 6 6 interrupt .......................................... ................................................... ........................................ 65 6.1 overview......................................... ................................................... .................................... 65
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 5 version 0.9 6.2 inten interrupt enable register........................................... ..................................... 66 6.3 intrq interrupt request register ........................................... .................................. 67 6.4 gie global interrupt operation .......................................... ....................................... 68 6.5 push, pop routine ............................................ ................................................... ................. 68 6.6 external interrupt operation (int0~int2) ......................................... .................... 70 6.7 t0 interrupt operation.......................................... ................................................... ....... 71 6.8 tc0 interrupt operation .......................................... ................................................... .... 72 6.9 tc1 interrupt operation .......................................... ................................................... .... 73 6.10 sio interrupt operation.......................................... ................................................... ..... 74 6.11 adc interrupt operation.......................................... ................................................... ... 75 6.12 multi-interrupt operation .......................................... ................................................. 76 7 7 7 i/o port........................................... ................................................... ............................................. 78 7.1 i/o port mode ............................................... ................................................... ...................... 78 7.2 i/o pull up register ........................................... ................................................... .............. 80 7.3 i/o port data register ........................................... ................................................... ........ 81 7.4 i/o open-drain register........................................... ................................................... ...... 82 7.5 port 4 adc share pin................................................ ................................................... ........ 83 8 8 8 timers............................................. ................................................... ............................................. 85 8.1 watchdog timer .............................................. ................................................... ................ 85 8.2 timer 0 (t0) ................................................ ................................................... ........................... 87 8.2.1 overview........................................... ................................................... ............................ 87 8.2.2 t0m mode register.................................... ................................................... ................ 88 8.2.3 t0c counting register ................................ ................................................... ............ 89 8.2.4 t0 timer operation sequence.......................... ................................................... ..... 90 8.3 timer/counter 0 (tc0) ............................................... ................................................... ...... 91 8.3.1 overview........................................... ................................................... ............................ 91 8.3.2 tc0m mode register ................................... ................................................... .............. 92 8.3.3 tc0c counting register ............................... ................................................... .......... 93 8.3.4 tc0r auto-load register.............................. ................................................... .......... 94 8.3.5 tc0 clock frequency output (buzzer)................. ............................................... 95 8.3.6 tc0 timer operation sequence ......................... ................................................... ... 96 8.3.7 tc0 timer notice .................................... ................................................... .................... 97 8.4 timer/counter 1 (tc1) ............................................... ................................................... ...... 98 8.4.1 overview........................................... ................................................... ............................ 98 8.4.2 tc1m mode register ................................... ................................................... .............. 99 8.4.3 tc1c counting register ............................... ................................................... ........ 100 8.4.4 tc1r auto-load register.............................. ................................................... ........ 101 8.4.5 tc1 clock frequency output (buzzer)................. ............................................. 102
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 6 version 0.9 8.4.6 tc1 timer operation sequence ......................... ................................................... . 103 8.4.7 tc1 timer notice .................................... ................................................... .................. 104 8.5 pwm0 mode ............................................... ................................................... ......................... 105 8.5.1 overview........................................... ................................................... .......................... 105 8.5.2 tc0irq and pwm duty ................................. ................................................... ............ 106 8.5.3 pwm program example................................ ................................................... .......... 107 8.5.4 pwm0 duty changing notice........................... ................................................... .... 108 8.6 pwm1 mode ............................................... ................................................... ......................... 110 8.6.1 overview........................................... ................................................... .......................... 110 8.6.2 tc1irq and pwm duty ................................. ................................................... ............ 111 8.6.3 pwm program example................................ ................................................... .......... 112 8.6.4 pwm1 duty changing notice........................... ................................................... .... 113 9 9 9 serial input/output transceiver (sio) .............. ................................................... ..... 115 9.1 overview......................................... ................................................... .................................. 115 9.2 sio operation .......................................... ................................................... ........................ 115 9.3 siom mode register ........................................... ................................................... ........... 117 9.4 siob data buffer............................................. ................................................... ............... 118 9.5 sior register description........................................ ................................................... .. 119 1 1 1 0 0 0 main serial port (msp)............................. ................................................... ..................... 120 10.1 overview......................................... ................................................... .................................. 120 10.2 msp status register ........................................... ................................................... .......... 120 10.3 msp mode register 1.................................................. ................................................... .... 121 10.4 msp mode register 2.................................................. ................................................... .... 122 10.5 msp mspbuf register ........................................... ................................................... ......... 123 10.6 msp mspadr register........................................... ................................................... ......... 123 10.7 s lave m ode o peration ................................................... ................................................... ..... 124 10.7.1 addressing ............................................ ................................................... .......................... 124 10.7.2 slave receiving ....................................... ................................................... ........................ 125 10.7.3 slave transmission...................................... ................................................... .................... 126 10.7.4 general call address .................................... ................................................... .................. 127 10.7.5 slave wake up.......................................... ................................................... ....................... 128 10.8 m aster mode ................................................... ................................................... ..................... 129 10.8.1 mater mode support ......................................... ................................................... .............. 129 10.8.2 msp rate generator ..................................... ................................................... .................. 129 10.8.3 msp mater start condition................................ ................................................... .......... 130 wcol status flag ................................... ................................................... ....................... 130 10.8.4 msp master mode repeat start condition ...................... ................................................ 131 wcol status flag ................................... ................................................... ....................... 131
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 7 version 0.9 10.8.5 acknowledge sequence timing.............................. ................................................... .......... 132 wcol status flag ................................... ................................................... ....................... 132 10.8.6 stop condition timing .................................... ................................................... .............. 133 wcol status flag ................................... ................................................... ....................... 133 10.8.7 clock arbitration ...................................... ................................................... ...................... 133 10.8.8 master mode transmission ................................. ................................................... ............ 134 bf status flag..................................... ................................................... ............................ 134 wcol flag ......................................... ................................................... ........................... 134 ackstat status flag................................ ................................................... .................... 134 10.8.9 master mode receiving.................................. ................................................... ................. 135 bf status flag..................................... ................................................... ............................ 135 mspov flag........................................ ................................................... ........................... 135 wcol flag ......................................... ................................................... ........................... 135 1 1 1 1 1 1 8 channel analog to digital converter ............... ............................................. 136 11.1 overview......................................... ................................................... .................................. 136 11.2 adm register ........................................... ................................................... ........................ 137 11.3 adr registers.......................................... ................................................... ........................ 138 11.4 adb registers.......................................... ................................................... ........................ 139 11.5 p4con registers.......................................... ................................................... .................... 140 11.6 adc converting time ............................................... ................................................... .... 140 11.7 adc routine example............................................ ................................................... ....... 141 11.8 adc circuit ............................................ ................................................... ........................... 142 1 1 1 2 2 2 digital to analog converter........................ ................................................... ......... 143 12.1 overview......................................... ................................................... .................................. 143 12.2 ................................................. ................................................... ................................................... 143 12.3 dam register ........................................... ................................................... ........................ 144 12.4 d/a converter operation .......................................... ................................................... 144 1 1 1 3 3 3 instruction table .................................. ................................................... ........................ 145 1 1 1 4 4 4 electrical characteristic .......................... ................................................... ........... 146 14.1 absolute maximum rating ............................................. ............................................. 146 14.2 standard electrical characteristic ..................................... .............................. 146 1 1 1 5 5 5 application notice ................................. ................................................... ....................... 147 15.1 d evelopment t ool v ersion ................................................... ................................................ 147 15.1.1 ice (in circuit emulation) .............................. ................................................... ................. 147 15.1.2 otp writer ......................................... ................................................... ............................ 148 15.1.3 ide (integrated development environment)..................... .................................................. 148
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 8 version 0.9 15.1.4 ................................................ ................................................... ............................................. 148 15.2 otp p rogramming p in ................................................... ................................................... ...... 149 15.2.1 the pin assignment of easy writer transition board socket: ....... ........................................ 149 15.2.2 the pin assignment of writer v3.0 and v2.5 transition board socket:. ................................ 149 15.2.3 sn8p275x series programming pin mapping: .......................... ........................................ 150 1 1 1 6 6 6 package information ................................ ................................................... .................. 151 16.1 sk-dip28 pin ................................................ ................................................... ........................ 151 16.2 sop28 pin ................................................ ................................................... ............................. 152 16.3 p-dip 32 pin ................................................ ................................................... .......................... 153 16.4 sop 32 pin................................................ ................................................... ............................. 153 16.5 qfn 32 pin ................................................ ................................................... ............................ 154 16.6 ssop 48 pin ................................................ ................................................... .......................... 155 16.7 lqfp 48 pin ................................................ ................................................... .......................... 156 1 1 1 7 7 7 marking definition ................................. ................................................... ...................... 157 17.1 introduction ..................................... ................................................... ............................. 157 17.2 marking indetification system ............................................. ................................... 157 17.3 marking example ............................................ ................................................... .............. 158 17.4 datecode system............................................. ................................................... .............. 158
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 9 version 0.9 1 1 1 product overview 1.1 features ? memory configuration ? eight interrupt sources otp rom size: 4k * 16 bits. six internal interrupts: t0, tc0, tc1, sio, adc,ms p. ram size: 256 * 8 bits (bank 0 and bank 1). three external interrupts: int0, int1, int2. ? 8 levels stack buffer. ? three 8-bit timer/counter ? i/o pin configuration (total 36 pins) t0: basic timer bi-directional: p0, p1, p2, p3, p4, p5 tc0: auto- reload timer/counter/pwm0/buzzer output programmable open-drain: p1.0, p1.1, p5.2 tc1: au to-reload timer/counter/pwm1/buzzer output wakeup: p0, p1 level change trigger external interrupt: p0 ? on chip watchdog timer and clock source is internal pull-up resisters: p0, p1, p2, p3, p4, p5 low clock rc type (16khz @3v, 32khz @5v). p4 pins shared with adc inputs. programmable open-drain: p1.0, p1.1,p5.2 ? dual system clocks ? 8-channel 12-bit sar adc. external high clock: rc type up to 10 mhz external high clock: crystal type 32khz up to 16 m hz ? one channel 7-bit r2r dac. internal low clock: rc type 16khz(3v), 32khz(5v) internal high clock: rc type 16mhz. ? sio function. ? operating modes normal mode: both high and low clock active ? powerful instructions slow mode: low clock only one clocks per instruction cycle (1t) sleep mode: both high and low clock stop most of instructions are one cycle only green mode: periodical wakeup by t0 timer all rom area lookup table function (movc) hardware multiplier (mul) ? package (chip form support) SN8P2758: ssop 48 pins, lqfp 48 pins ? memory configuration sn8p2755: pdip 32 pins, sop 32 pins otp rom size: 4k * 16 bits. sn8p2754: sk-dip 28 pins, sop 28pins ram size: 256 * 8 bits (bank 0 and bank 1). eight levels stack buffer ? i/o pin configuration (total 36 pins) ? three 8-bit timer/counter bi-directional: p0, p1, p2, p3, p4, p5 t0: basic timer programmable open-drain: p1.0, p1.1, p5.2 tc0: au to-reload timer/counter/pwm0/buzzer output wakeup: p0, p1 level change trigger tc1: auto-rel oad timer/counter/pwm1/buzzer output external interrupt: p0 pull-up resisters: p0, p1, p2, p3, p4, p5 ? on chip watchdog timer and clock source is internal p4 pins shared with adc inputs. low clock rc type (16khz @3v, 32khz @5v). ? build in msp interface with interrupt function ? dual system clocks msp sleep mode wake up function.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 10 version 0.9 features selection table timer pwm chip rom ram stack t0 tc0 tc1 i/o adc dac buzzer sio wakeup pin no. package SN8P2758 4k*16 256 8 v v v 36 8ch 1ch 2 1 11 ssop48/lqfp48 sn8p2755 4k*16 256 8 v v v 23 8ch 1ch 2 1 9 dip32/sop32/qfn32 sn8p2754 4k*16 256 8 v v v 18 5ch 1ch 2 1 8 skdip28/sop28 1.2 system block diagram pc ir otp rom h-osc timing generator ram system register alu acc interrupt control timer & counter port 0 port 2 port 1 port 4 port 5 flags dac adc dao ain0~ain7 sio tx/rx system block internal clk pwm1 pwm0 pwm0/buzzer0 pwm1/buzzer1 low volt detector watch-dog timer port 3 pc ir otp rom h-osc timing generator ram system register alu acc interrupt control timer & counter port 0 port 2 port 1 port 4 port 5 flags dac adc dao ain0~ain7 sio tx/rx system block internal clk pwm1 pwm0 pwm0/buzzer0 pwm1/buzzer1 low volt detector watch-dog timer port 3
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 11 version 0.9 1.3 pin assignment sn8p2754k (sk-dip28) sn8p2754a (sop28) p1.4 1 u 28 rst/vpp p1.3 2 27 p0.2/int2 vdd 3 26 p0.1/int1 p1.2 4 25 p0.0/int0 sda/p1.1 5 24 vdd scl/p1.0 6 23 xin/p3.2 vss 7 22 xout/p3.1 p4.4/ain4 8 21 vss p4.3/ain3 9 20 p5.0/sck p4.2/ain2 10 19 p5.1/si p4.1/ain1 11 18 p5.2/so p4.0/ain0 12 17 p5.3/tc1/pwm1 avrefh 13 16 p5.4/tc0/pwm0 vdd 14 15 dao sn8p2754k sn8p2754s sn8p2755p (p-dip32) sn8p2755s (sop32) vss 1 u 32 p5.0/sck xout/p3.1 2 31 p5.1/si xin/p3.2 3 30 p5.2/so vdd 4 29 p5.3/bz1/pwm1 p0.0/int0 5 28 p5.4/bz0/pwm0 p0.1/int1 6 27 dao p0.2/int2 7 26 vdd rst/vpp 8 25 avrefh p1.5 9 24 p4.0/ain0 p1.4 10 23 p4.1/ain1 p1.3 11 22 p4.2/ain2 p1.2 12 21 p4.3/ain3 sda/p1.1 13 20 p4.4/ain4 scl/p1.0 14 19 p4.5/ain5 p2.0 15 18 p4.6/ain6 vss 16 17 p4.7/ain7 sn8p2755p sn8p2755s
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 12 version 0.9 sn8p2755j (qfn32) p5.0/sck p5.1/si p5.2/so p5.3/bz1/pwm1 p5.4/bz0/pwm0 dao vdd avrefh 32 31 30 29 28 27 26 25 vss 1 o 24 p4.0/ain0 xout/p3.1 2 23 p4.1/ain1 xin/p3.2 3 22 p4.2/ain2 vdd 4 21 p4.3/ain3 p0.0/int0 5 20 p4.4/ain4 p0.1/int1 6 19 p4.5/ain5 p0.2/int2 7 18 p4.6/ain6 rst/vpp 8 17 p4.7/ain7 9 10 11 12 13 14 15 16 p1.5 p1.4 p1.3 p1.2 sda/p1.1 scl/p1.0 p2.0 vss SN8P2758x (ssop48) p2.5 1 u 48 p2.4 p2.6 2 47 p5.0/sck p2.7 3 46 p5.1/si p1.7 4 45 p5.2/so vss 5 44 p5.3/bz1/pwm1 xout/p3.1 6 43 p3.0 xin/p3.2 7 42 p5.4/bz0/pwm0 vdd 8 41 p5.5 p0.0/int0 9 40 p5.6 p0.1/int1 10 39 p5.7 p0.2/int2 11 38 dao rst/vpp 12 37 vdd p1.5 13 36 avdd p1.4 14 35 avrefh p1.3 15 34 p4.0/ain0 vdd 16 33 p4.1/ain1 p1.6 17 32 p4.2/ain2 p1.2 18 31 p4.3/ain3 sda/p1.1 19 30 p4.4/ain4 scl/p1.0 20 29 p4.5/ain5 p2.0 21 28 p4.6/ain6 p2.1 22 27 p4.7/ain7 p2.2 23 26 avrefl p2.3 24 25 vss SN8P2758x
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 13 version 0.9 SN8P2758f (lqfp48) p2.4 p5.0/sck p5.1/si p5.2/so p5.3/bz1/pwm1 p3.0 p5.4/bz0/pwm0 p5.5 p5.6 p5.7 dao vdd 48 47 46 45 44 43 42 41 40 39 38 37 p2.5 1 o 36 avdd p2.6 2 35 avrefh p2.7 3 34 p4.0/ain0 p1.7 4 33 p4.1/ain1 vss 5 32 p4.2/ain2 xout/p3.1 6 SN8P2758f 31 p4.3/ain3 xin/p3.2 7 30 p4.4/ain4 vdd 8 29 p4.5/ain5 p0.0/int0 9 28 p4.6/ain6 p0.1/int1 10 27 p4.7/ain7 p0.2/int2 11 26 avrefl rst/vpp 12 25 vss 13 14 15 16 17 18 19 20 21 22 23 24 p1.5 p1.4 p1.3 vdd p1.6 p1.2 sda/p1.1 scl/p1.0 p2.0 p2.1 p2.2 p2.3
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 14 version 0.9 1.4 pin descriptions pin name description vdd, vss p power supply input pins for digital circ uit. rst/vpp i, p rst: system reset input pin. schmitt trigger struct ure, low active, normal stay to ?high?. vpp: otp programming pin. schmitt trigger structure as input mode. no built-in pull-up resisters. xin/p3.2 i/o oscillator input pin while external oscillator enabl e (crystal and rc). port 3.2 bi-direction pin. schmitt trigger structure as input mode. built-in pull-up resisters. xout/p3.1 i/o xout: oscillator output pin while external crystal en able. port 3.1 bi-direction pin. schmitt trigger structure as input mode. built-in pull-up resisters. p0.0/int0 i/o port 0.0 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. built-in wakeup function. int0 trigger pin (schmitt trigger). tc0 event counter clock input pin. p0.1/int1 i/o port 0.1 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. built-in wakeup function. int1 trigger pin (schmitt trigger). tc1 event counter clock input pin. p0.2/int2 i/o port 0.2 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. built-in wakeup function. int2 trigger pin (schmitt trigger). p1.0/scl i/o port 1.0 bi-direction pin and open-drain pin. schmi tt trigger structure as input mode. built-in pull-up resisters. msp serial clock input/output pin. programmable open-drain. p1.1/sda i/o port p1.1 bi-direction pin and open-drain pin. schm itt trigger structure as input mode. built-in pull-up resisters. msp data i/o pin. programmable open-drain. p1 [7:2] i/o port 1.2~p1.7 bi-direction pin. schmitt trigger str ucture as input mode. built-in pull-up resisters. p2 [7:0] i/o port 2 bi-direction pin. schmitt trigger structure as input mode. built-in pull-up resisters. p3.0 i/o port 3.0 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. p4.[7:0]/ain[7:0] i/o port 4 bi-direction pins. no schmitt trigger struct ure. built-in pull-up resisters. ain[7:0]: adc channel-0~7 input. p5.0/sck i/o port 5.0 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. sck: sio clock pin. p5.1/so i/o port 5.1 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. so: sio data output pin. p5.2/si i/o port 5.2 bi-direction pin and open-drain pin. schmi tt trigger structure as input mode. built-in pull-up resisters. si: sio data input pin. p5.3/bz1/pwm1 i/o port 5.3 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. tc1 2 signal output pin for buzzer or pwm1 output pin. p5.4/bz0/pwm0 i/o port 5.4 bi-direction pin. schmitt trigger structur e as input mode. built-in pull-up resisters. tc0 2 signal output pin for buzzer or pwm0 output pin. avdd p power supply input pins for a/d circuit avrefh i adc highest reference voltage input avrefl i adc lowest reference voltage input dao o 7bit dac output
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 15 version 0.9 1.5 pin circuit diagrams port 1.0, p1.1, p5.2 structure: pull-up pin output latch pnm, pnur input bus pnm output bus p1oc open-drain port 0, 1, 2, 3, 5 structure: pull-up pin output latch pnm, pnur input bus pnm output bus port 4 structure: gchs int. adc p4con pull-up output latch pnm, pnur input bus pnm output bus pin
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 16 version 0.9 2 2 2 central processor unit (cpu) 2.1 memory map 2.1.1 program memory (rom) 4k words rom rom 0000h reset vector user reset vector jump to user start address 0001h . . 0007h general purpose area 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . . . . ffbh general purpose area end of user program ffch ffdh ffeh fffh reserved
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 17 version 0.9 2.1.2 reset vector (0000h) a one-word vector address area is used to execute s ystem reset. power on reset (nt0=1, npd=0). watchdog reset (nt0=0, npd=0). external reset (nt0=1, npd=1). after power on reset, external reset or watchdog ti mer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. it is easy to know reset status from nt0, npd flags of pflag register. the following example show s the way to define the reset vector in the program memory. example: defining reset vector org 0 ; 0000h jmp start ; jump to user program address. ? org 10h start: ; 0010h, the head of user program. ? ; user program ? endp ; end of program
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 18 version 0.9 2.1.3 interrupt vector (0008h) a 1-word vector address area is used to execute int errupt request. if any interrupt service executes, the program counter (pc) value is stored in stack buffer and ju mp to 0008h of program memory to execute the vector ed interrupt. users have to define the interrupt vector. the foll owing example shows the way to define the interrupt vector in the program memory. note: ?push?, ?pop? instructions save and load acc/ pflag without (nt0, npd). push/pop buffer is a unique buffer and only one level. example: defining interrupt vector. the interrupt s ervice routine is following org 8. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. push ; save acc and pflag register to buffers. ? ? pop ; load acc and pflag register from buffers. reti ; end of interrupt service routine ? start: ; the head of user program. ? ; user program ? jmp start ; end of user program ? endp ; end of program
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 19 version 0.9 example: defining interrupt vector. the interrupt s ervice routine is following user program. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. jmp my_irq ; 0008h, jump to interrupt service rout ine address. org 10h start: ; 0010h, the head of user program. ? ; user program. ? ? jmp start ; end of user program. ? my_irq: ;the head of interrupt service routine. push ; save acc and pflag register to buffers. ? ? pop ; load acc and pflag register from buffers. reti ; end of interrupt service routine. ? endp ; end of program. note: it is easy to understand the rules of sonix p rogram from demo programs given above. these points are as following: 1. the address 0000h is a ?jmp? instruction to make the program starts from the beginning. 2. the address 0008h is interrupt vector. 3. user?s program is a loop routine for main purpos e application. 2.1.3.1 look-up table description in the rom?s data lookup function, x register is po inted to high byte address (bit 16~bit 23), y regis ter is pointed to middle byte address (bit 8~bit 15) and z register i s pointed to low byte address (bit 0~bit 7) of rom. after movc instruction executed, the low-byte data will be sto red in acc and high-byte data stored in r register. example: to look up the rom data located ?table1?. b0mov x, #table1$h ; to set lookup table1?s high a ddress b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low a ddress. movc ; to lookup data, r = 00h, acc = 35h ; increment the index address for next address. incms z ; z+1 jmp @f ; z is not overflow. incms y ; z is overflow, y=y+1. jmp @f ; y is not overflow. incms x ; y is overflow, x=x+1. nop ; @@: movc ; to lookup data, r = 51h, acc = 05h.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 20 version 0.9 ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? note: the x, y registers will not increase automatically when y, z registers crosses boundary from 0xff to 0x00. therefore, user must take care such situat ion to avoid loop-up table errors. if z register is overflow, y register must be added one. if y regist er is overflow, x register must be added one. the following inc_xyz macro shows a simple method to pr ocess x, y and z registers automatically. example: inc_xyz macro. inc_xyz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 jmp @f ; not overflow incms x ; x+1 nop ; not overflow @@: endm
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 21 version 0.9 example: modify above example by ?inc_xyz? macro. b0mov x, #table1$h ; to set lookup table1?s high a ddress b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low a ddress. movc ; to lookup data, r = 00h, acc = 35h inc_xyz ; increment the index address for next address. ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? the other example of loop-up table is to add x, y o r z index register by accumulator. please be carefu l if ?carry? happen. example: increase y and z register by b0add/add ins truction. b0mov x, #table1$h ; to set lookup table1?s high address b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table?s low ad dress. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. jmp getdata ; y is not overflow. incms x ; y is overflow, x=x+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x00 35 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 ? table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ?
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 22 version 0.9 2.1.4 jump table description the jump table operation is one of multi-address ju mping function. add low-byte program counter (pcl) and acc value to get one new pcl. if pcl is overflow after pcl+acc, pch adds one automatically. the new progra m counter (pc) points to a series jump instructions as a list ing table. it is easy to make a multi-jump program depends on the value of the accumulator (a). note: pch only support pc up counting result and doesn?t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl?acc, pch keeps value and not change. example: jump table. org 0x0100 ; the jump table is from the head of t he rom boundary b0add pcl, a ; pcl = pcl + acc, pch + 1 when pcl overflow occurs . jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point sonix provides a macro for safe jump table function . this macro will check the rom boundary and move t he jump table to the right position automatically. the side effect of this macro maybe wastes some rom size. example: if ?jump table? crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm note: ?val? is the number of the jump table listing number.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 23 version 0.9 example: ?@jmp_a? application in sonix macro file c alled ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is across a rom boundary (0x00ff~0x0100), the ?@jmp_a? macro will adjust th e jump table routine begin from next ram boundary (0x0100). example: ?@jmp_a? operation. ; before compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x00fd jmp a0point ; acc = 0, jump to a0point 0x00fe jmp a1point ; acc = 1, jump to a1point 0x00ff jmp a2point ; acc = 2, jump to a2point 0x0100 jmp a3point ; acc = 3, jump to a3point 0x0101 jmp a4point ; acc = 4, jump to a4point ; after compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x0100 jmp a0point ; acc = 0, jump to a0point 0x0101 jmp a1point ; acc = 1, jump to a1point 0x0102 jmp a2point ; acc = 2, jump to a2point 0x0103 jmp a3point ; acc = 3, jump to a3point 0x0104 jmp a4point ; acc = 4, jump to a4point
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 24 version 0.9 2.1.4.1 checksum calculation the last rom address are reserved area. user should avoid these addresses (last address) when calculat e the checksum value. example: the demo program shows how to calculated c hecksum from 00h to the end of user?s code. mov a,#end_user_code$l b0mov end_addr1, a ; save low end address to end_a ddr1 mov a,#end_user_code$m b0mov end_addr2, a ; save middle end address to en d_addr2 clr y ; set y to 00h clr z ; set z to 00h @@: movc b0bset fc ; clear c flag add data1, a ; add a to data1 mov a, r adc data2, a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; if z = 00h increase y end_check: mov a, end_addr1 cmprs a, z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a, end_addr2 cmprs a, y ; if yes, check if y = middle end addre ss jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is d one. y_add_1: incms y ; increase y nop jmp @b ; jump to checksum calculate checksum_end: ? ? end_user_code: ; label of program end
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 25 version 0.9 2.1.5 code option table code option content function description rc low cost rc for external high clock oscillator and xout becomes to fcpu frequency output pin. 12m x?tal high speed crystal /resonator (e.g. 12mhz) for exte rnal high clock oscillator. 4m x?tal standard crystal /resonator (e.g. 4m) for external high clock oscillator. ihrc_16m high speed internal 16mhz rc. xin/xout become to p3 .2/p3.1 bi-direction i/o pins. ihrc_rtc high speed internal 16mhz rc with 0.5sec rtc. xin/x out become to p3.2/p3.1 bit-direction i/o pins. high_clk 32k x?tal low frequency, power saving crystal (e.g. 32.768khz ) for external high clock oscillator. always_on watchdog timer is always on enable even in power do wn and green mode. enable enable watchdog timer. watchdog timer stops in powe r down mode. watchdog is running in green mode. watch_dog disable disable watchdog function. fhosc/1 instruction cycle is oscillator clock. notice: in fosc/1, noise filter must be disabled. fhosc/2 instruction cycle is 2 oscillator clocks. notice: in fosc/1, noise filter must be disabled. fhosc/4 instruction cycle is 4 oscillator clocks. fhosc/8 instruction cycle is 8 oscillator clocks. fhosc/16 instruction cycle is 16 oscillator clocks. fhosc/32 instruction cycle is 32 oscillator clocks. fhosc/64 instruction cycle is 64 oscillator clocks. fcpu fhosc/128 instruction cycle is 128 oscillator clock s. enable enable rom code security function. security disable disable rom code security function. enable enable noise filter. noise_filter disable disable noise filter. no disable external reset de-bounce time. external reset length 128 * ilrc enable external reset de-bounce time. note: 1. in high noisy environment, enable ?noise filter? an d set watch_dog as ?always_on? is strongly recommended. 2. fcpu code option is only available for high clock. fcpu of slow mode is flosc/4. 3. in external rc mode, the noise_filter is enabled by assembler. 4. if watchdog enable, watchdog timer is still countin g in green mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 26 version 0.9 2.1.6 data memory (ram) 256 x 8-bit ram address ram location 000h ? ? 000h~07fh o f bank 0 = to store general purpose data (128 bytes). ? ? ? 07fh general purpose area 080h ? 080h~0ffh of bank 0 store system registers (128 bytes). ? ? ? ? system register bank 0 0ffh end of bank 0 area 100h ? 1 00h~17fh of bank 1 = to store general purpose data (128 bytes). ? ? ? ? general purpose area bank 1 17fh end of bank 1 area
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 27 version 0.9 2.1.7 system register 2.1.7.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 l h r z y x pflag rbank - - - - - - - - 9 mspstat mspm1 mspm2 mspbuf mspadr - - - - - - - - - - - a - - - - - - - - - - - - - - p4con - b dam adm adb adr siom sior siob - p0m - - - - - - pedge c p1w p1m p2m p3m p4m p5m intrq_1 inten_1 intrq inten oscm - wdtr tc0r pcl pch d p0 p1 p2 p3 p4 p5 - - t0m t0c tc0m tc0c tc1m tc1c tc1r stkp e p0ur p1ur p2ur p3ur p4ur p5ur @hl @yz - p1oc - - - - - - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.1.7.2 system register description l, h = working & @hl addressing register. r = working register and rom lookup data buffer. x = working and rom address register. y, z = working, @yz and rom addressing register. pflag = rom page and special flag register. rbank = ram bank select register. dam = dac?s mode register. adm = adc?s mode register. adb = adc?s data buffer. adr = adc?s resolution selects register. siom = sio mode control register. sior = sio?s clock reload buffer. siob = sio?s data buffer. p1w = port 1 wakeup register. pnm = port n input/output mode register. pn = port n data buffer. intrq = interrupts? request register. inten = interrupts? enable register. oscm = oscillator mode register. pch, pcl = program counter. t0m = timer 0 mode register. tc0m = timer/counter 0 mode register. t0c = timer 0 counting register. tc0c = timer/counter 0 counting register. tc1m = timer/counter 1 mode register. tc0r = timer/counter 0 auto-reload data buffer. tc1c = timer/counter 1 counting register. tc1r = timer/counter 1 auto-reload data buffer. stkp = stack pointer buffer. stk0~stk7 = stack 0 ~ stack 7 buffer. @hl = ram hl indirect addressing index pointer. @yz = ram yz indirect addressing index pointer. p4con= port 4 configuration setting
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 28 version 0.9 2.1.7.3 bit definition of system register address 080h ~ 09fh addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w register name 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 085h xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w x 086h nt0 npd c dc z r/w pflag 087h rbnks0 r/w rbank 088h 089h 08ah 08bh 08ch 08dh 08eh 08fh 090h cke d_a p s red_wrt bf r mspstat 091h wcol mspov mspenb ckp slrxckp mspwk - mspc r/w mspm1 092h gcen ackstat ackdt acken rcen pen rsen sen r/w mspm2 093h mspbuf7 mspbuf6 mspbuf5 mspbuf4 mspbuf3 mspbuf2 mspbuf1 mspbuf0 r/w mspbuf 094h mspadr7 mspadr6 mspadr5 mspadr4 mspadr3 mspadr2 mspadr1 mspadr0 r/w mspadr 095h 096h 097h 098h 099h 09ah 09bh 09ch 09dh 09eh 09fh address 0a0h ~ 0bfh addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w register name 0a0h 0a1h 0a2h 0a3h 0a4h
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 29 version 0.9 0a5h 0a6h 0a7h 0a8h 0a9h 0aah 0abh 0ach 0adh 0aeh p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 w p4con 0afh 0b0h daenb dab6 dab5 dab4 dab3 dab2 dab1 dab0 r/w dam 0b1h adenb ads eoc gchs - chs2 chs1 chs0 r/w adm 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb 0b3h adcks2 adcks1 adlen adcks0 adb3 adb2 adb1 adb0 r/w adr 0b4h senb start srate1 srate0 mlsb sckmd cpol cpha r/w siom 0b5h sior7 sior6 sior5 sior4 sior3 sior2 sior1 sior0 w sior 0b6h siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w siob 0b7h 0b8h p02m p01m p00m r/w p0m 0b9h 0bah 0bbh 0bch 0bdh 0beh 0bfh p02g1 p02g0 p01g1 p01g0 p00g1 p00g0 r/w pedge address 0c0h ~ 0dfh addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w register name 0c0h p17w p16w p15w p14w p13w p12w p11w p10w w p1w 0c1h p17m p16m p15m p14m p13m p12m p11m p10m r/w p1m 0c2h p27m p26m p25m p24m p23m p22m p21m p20m r/w p2m 0c3h - - - - - p32m p31m p30m r/w p3m 0c4h p47m p46m p45m p44m p43m p42m p41m p40m r/w p4m 0c5h p57m p56m p55m p54m p53m p52m p51m p50m r/w p5m 0c6h mspirq r/w intrq_1 0c7h mspien r/w inten_1 0c8h adcirq tc1irq tc0irq t0irq sioirq p02irq p01irq p00 irq r/w intrq 0c9h adcien tc1ien tc0ien t0ien sioien p02ien p01ien p00 ien r/w inten 0cah cpum1 cpum0 clkmd stphx r/w oscm 0cbh 0cch wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 w wdtr
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 30 version 0.9 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh pc11 pc10 pc9 pc8 r/w pch 0d0h p02 p01 p00 r/w p0 0d1h p17 p16 p15 p14 p13 p12 p11 p10 r/w p1 0d2h p27 p26 p25 p24 p23 p22 p21 p20 r/w p2 0d3h p32 p31 p30 r/w p3 0d4h p47 p46 p45 p44 p43 p42 p41 p40 r/w p4 0d5h p57 p56 p55 p54 p53 p52 p51 p50 r/w p5 0d6h 0d7h 0d8h t0enb t0rate2 t0rate1 t0rate0 tc1x8 tx0x8 t0tb r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload1 tc1out pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w tc1r 0dfh gie stkpb2 stkpb1 stkpb0 r/w stkp address 0e0h ~ 0ffh addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w register name 0e0h - p02r p01r p00r w p0ur 0e1h p17r p16r p15r p14r p13r p12r p11r p10r w p1ur 0e2h p27r p26r p25r p24r p23r p22r p21r p20r w p2ur 0e3h p32r p31r p30r w p3ur 0e4h p47r p46r p45r p44r p43r p42r p41r p40r w p4ur 0e5h p57r p56r p55r p54r p53r p52r p51r p50r w p5ur 0e6h @hl7 @hl6 @hl5 @hl4 @hl3 @hl2 @hl1 @hl0 r/w @hl 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz 0e8h 0e9h p52oc p11oc p10oc w p1oc 0eah 0ebh 0ech 0edh 0eeh 0efh 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 31 version 0.9 0f5h s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh s1pc12 s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h note: 1. to avoid system error, make sure to put all the ?0? and ?1? as it indicates in the above table . 2. all of register names had been declared in sn8as m assembler. 3. one-bit name had been declared in sn8asm assembl er with ?f? prefix code. 4. ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instructions are only available to the ?r/w? registers.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 32 version 0.9 2.1.7.4 accumulator the acc is an 8-bit data register responsible for t ransferring or manipulating data between alu and da ta memory. if the result of operating is zero (z) or there is car ry (c or dc) occurrence, then these flags will be s et to pflag register. acc is not in data memory (ram), so acc can?t be ac cess by ?b0mov? instruction during the instant addr essing mode. example: read and write acc value. ; read acc data and store in buf data memory mov buf, a ; write a immediate data into acc mov a, #0fh ; write acc data from buf data memory mov a, buf the system doesn?t store acc and pflag value when i nterrupt executed. acc and pflag data must be saved to other data memories. ?push?, ?pop? save and load 0x 80~0x87 system registers data into buffers. users h ave to save acc data by program. example: protect acc and working registers. .data accbuf ds 1 ; define accbuf for store acc da ta. .code int_service: b0xch a, accbuf ; save acc to buffer. push ; save pflag and working registers to buffer . ? . ? pop ; load pflag and working registers form buffe rs. b0xch a, accbuf ; load acc form buffer. reti ; exit interrupt service vector note: to save and re- load acc data, users must use ?b0xch? instruction, or else the pflag register might be modified by acc operation.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 33 version 0.9 2.1.8 program flag the pflag register contains the arithmetic status o f alu operation, system reset status and lvd detect ing status. nt0, npd bits indicate system reset status includin g power on reset, lvd reset, reset by external pin active and watchdog reset. c, dc, z bits indicate the result s tatus of alu operation. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd reset status 0 0 watch-dog time out 0 1 reserved 1 0 reset by lvd 1 1 reset by external reset pin bit 2 c: carry flag 1 = addition with carry, subtraction without borrow ing, rotation with shifting out logic ?1?, comparis on result 0. 0 = addition without carry, subtraction with borrow ing signal, rotation with shifting out logic ?0?, c omparison result < 0. bit 1 dc: decimal carry flag 1 = addition with carry from low nibble, subtractio n without borrow from high nibble. 0 = addition without carry from low nibble, subtrac tion with borrow from high nibble. bit 0 z: zero flag 1 = the result of an arithmetic/logic/branch operat ion is zero. 0 = the result of an arithmetic/logic/branch operat ion is not zero. note: refer to instruction set table for detailed i nformation of c, dc and z flags.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 34 version 0.9 2.1.8.1 program counter the program counter (pc) is a 12-bit binary counter separated into the high-byte 4 and the low-byte 8 bits. this counter is responsible for pointing a location in o rder to fetch an instruction for kernel circuit. no rmally, the program counter is automatically incremented with each inst ruction during program execution. besides, it can be replaced with specific address b y executing call or jmp instruction. when jmp or ca ll instruction is executed, the destination address will be insert ed to bit 0 ~ bit 11. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - - - 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl one address skipping there are nine instructions (cmprs, incs, incms, de cs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these i nstructions is true, the pc will add 2 steps to ski p next instruction. if the condition of bit test instruction is true, t he pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. ? ? c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. ? ? c1step: nop if the acc is equal to the immediate data or memory , the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step. ? ? c0step: nop
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 35 version 0.9 if the destination increased by 1, which results ov erflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop if the destination decreased by 1, which results un derflow of 0x01 to 0x00, the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 36 version 0.9 multi-address jumping users can jump around the multi-address by either j mp instruction or add m, a instruction (m = pcl) to activate multi-address jumping function. program counter sup ports ?add m,a? , ?adc m,a? and ?b0add m,a? instructions for carry to pch when pcl overflow automatically. f or jump table or others applications, users can cal culate pc value by the three instructions and don?t care pcl overfl ow problem. note: pch only support pc up counting result and doesn?t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl?acc, pch keeps value and not change. example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ? ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to address 0300h ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point ? ? 2.1.9 h, l registers the h and l registers are the 8-bit buffers. there are two major functions of these registers. can be used as general working registers can be used as ram data pointers with @hl register 081h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset x x x x x x x x 080h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset x x x x x x x x example: if want to read a data from ram address 20 h of bank_0, it can use indirectly addressing mode
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 37 version 0.9 to access data as following. b0mov h, #00h ; to set ram bank 0 for h register b0mov l, #20h ; to set location 20h for l register b0mov a, @hl ; to read a data into acc example: clear general-purpose data memory area of bank 0 using @hl register. clr h ; h = 0, bank 0 b0mov l, #07fh ; l = 7fh, the last address of the data memory area clr_hl_buf: clr @hl ; clear @hl to be zero decms l ; l ? 1, if l = 0, finish the routine jmp clr_hl_buf ; not zero clr @hl end_clr: ; end of clear general purpose data memo ry area of bank 0 ? ?
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 38 version 0.9 2.1.10 y, z registers the y and z registers are the 8-bit buffers. there are three major functions of these registers. can be used as general working registers can be used as ram data pointers with @yz register can be used as rom data pointer with the movc inst ruction for look-up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z ? 1, if z= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memo ry area of bank 0 ? 2.1.10.1 x registers x register is an 8-bit buffer. there are two major functions of the register. can be used as general working registers can be used as rom data pointer with the movc inst ruction for look-up table 085h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note: please refer to the ?look-up table descriptio n? about x register look-up table application.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 39 version 0.9 2.1.11 r registers r register is an 8-bit buffer. there are two major functions of the register. can be used as working register for store high-byte data of look-up table (movc instruction executed, the high-byte data of s pecified rom address will be stored in r register a nd the low-byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - note: please refer to the ?look-up table descriptio n? about r register look-up table application.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 40 version 0.9 2.2 addressing mode 2.2.1 immediate addressing mode the immediate addressing mode uses an immediate dat a to set up the location in acc or specific ram. example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into ac c. example: move the immediate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. note: in immediate addressing mode application, the specific ram must be 0x80~0x87 working register. 2.2.2 directly addressing mode the directly addressing mode moves the content of r am location in or out of acc. example: move 0x12 ram location data into acc. b0mov a, 12h ; to get a content of ram location 0x12 of bank 0 a nd save in acc. example: move acc data into 0x12 ram location. b0mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. 2.2.3 indirectly addressing mode the indirectly addressing mode is to access the mem ory by the data pointer registers (h/l, y/z). example: indirectly addressing mode with @hl regist er b0mov h, #0 ; to clear h register to access ram ba nk 0. b0mov l, #12h ; to set an immediate data 12h into l register. b0mov a, @hl ; use data pointer @hl reads a data f rom ram location ; 012h into acc. example: indirectly addressing mode with @yz regist er b0mov y, #0 ; to clear y register to access ram ba nk 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data f rom ram location ; 012h into acc.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 41 version 0.9 2.3 stack operation 2.3.1 overview the stack buffer has 8-level. these buffers are des igned to push and pop up program counter?s (pc) dat a when interrupt service routine and ?call? instruction ar e executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack bu ffer. the stknh and stknl are the stack buffers to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 42 version 0.9 2.3.2 stack registers the stack pointer (stkp) is a 3-bit register to sto re the address used to access the stack buffer, 12- bit data memory (stknh and stknl) set aside for temporary storage o f stack addresses. the two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always p oint to the top address of stack buffer and write the last program counter value (pc) into the stack buffer. the program counter (pc) value is stored in the sta ck buffer before a call instruction executed or dur ing interrupt service routine. stack operation is a lifo type (la st in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in the system registe r area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit[2:0] stkpbn: stack pointer (n = 0 ~ 2) bit 7 gie: global interrupt control bit. 0 = disable. 1 = enable. please refer to the interrupt chapter. example: stack pointer (stkp) reset, we strongly re commended to clear the stack pointer in the beginning of the program. mov a, #00000111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - - snpc11 snpc10 snpc9 snpc8 read/write - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 43 version 0.9 2.3.3 stack operation example the two kinds of stack-save operations refer to the stack pointer (stkp) and write the content of prog ram counter (pc) to the stack buffer are call instruction and interr upt service. under each condition, the stkp decreas es and points to the next available stack location. the stack buffer stores the program counter about the op-code addre ss. the stack-save operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - 5 0 1 0 stk4h stk4l - 6 0 0 1 stk5h stk5l - 7 0 0 0 stk6h stk6l - 8 1 1 1 stk7h stk7l - > 8 1 1 0 - - stack over, error there are stack-restore operations correspond to ea ch push operation to restore the program counter (p c). the reti instruction uses for interrupt service routine. the ret instruction is for call instruction. when a po p operation occurs, the stkp is incremented and points to the next free stack location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack-re store operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 8 1 1 1 stk7h stk7l - 7 0 0 0 stk6h stk6l - 6 0 0 1 stk5h stk5l - 5 0 1 0 stk4h stk4l - 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free -
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 44 v0.9 3 3 3 reset 3.1 overview the system would be reset in three conditions as fo llowing. power on reset watchdog reset brown out reset external reset when any reset condition occurs, all system registe rs keep initial status, program stops and program c ounter is cleared. after reset status released, the system boots up an d program starts to execute from org 0. the nt0, np d flags indicate system reset status. the system can depend on nt0, npd status and go to different paths by pr ogram. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd condition description 0 0 watchdog reset watchdog timer overflow. 0 1 reserved - 1 0 power on reset and lvd reset. power voltage is lower than lvd detecting level. 1 1 external reset external reset pin detect low le vel status. finishing any reset sequence needs some time. the s ystem provides complete procedures to make the powe r on reset successful. for different oscillator types, the res et time is different. that causes the vdd rise rate and start-up time of different oscillator is not fixed. rc type oscillat or?s start-up time is very short, but the crystal t ype is longer. under client terminal application, users have to take care the p ower on reset time for the master terminal requirem ent. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 45 v0.9 3.2 power on reset the power on reset depend no lvd operation for most power-up situations. the power supplying to system is a rising curve and needs some time to achieve the normal vol tage. power on reset sequence is as following. power-up: system detects the power voltage up and waits for power stable. external reset: system checks external reset pin status. if extern al reset pin is not high level, the system keeps reset status and waits external reset pin released. system initialization: all system registers is set as initial conditions and system is ready. oscillator warm up: oscillator operation is successfully and supply to system clock. program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal co ndition, system works well and clears watchdog time r by program. under error condition, system is in unknown situati on and watchdog can?t be clear by program before wa tchdog timer overflow. watchdog timer overflow occurs and the sy stem is reset. after watchdog reset, the system res tarts and returns normal mode. watchdog reset sequence is as following. watchdog timer status: system checks watchdog timer overflow status. if w atchdog timer overflow occurs, the system is reset. system initialization: all system registers is set as initial conditions and system is ready. oscillator warm up: oscillator operation is successfully and supply to system clock. program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. before clearing watchdog timer, check i/o status a nd check ram contents can improve system error. don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main r outine fail. clearing watchdog timer program is only at one par t of the program. this way is the best structure to enhance the watchdog timer function. note: please refer to the ?watchdog timer? about wa tchdog timer detail information.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 46 v0.9 3.4 brown out reset 3.4.1 brown out description the brown out reset is a power dropping condition. the power drops from normal voltage to low voltage by external factors (e.g. eft interference or external loading changed). the brown out reset would make the system not work well or executing program error. vdd vss v1 v2 v3 system work well area system work error area brown out reset diagram the power dropping might through the voltage range that?s the system dead-band. the dead-band means th e power range can?t offer the system minimum operation powe r requirement. the above diagram is a typical brown out reset diagram. there is a serious noise under the vdd, an d vdd voltage drops very deep. there is a dotted li ne to separate the system working area. the above area is the syst em work well area. the below area is the system wor k error area called dead-band. v1 doesn?t touch the below area a nd not effect the system operation. but the v2 and v3 is under the below area and may induce the system error occurren ce. let system under dead-band includes some condit ions. dc application: the power source of dc application is usually using battery. when low battery condition and mcu drive any loading, the power drops and keeps in dead-band. under the s ituation, the power won?t drop deeper and not touch the system reset voltage. that makes the system under dead-ban d. ac application: in ac power application, the dc power is regulated from ac power source. this kind of power usually co uples with ac noise that makes the dc power dirty. or the externa l loading is very heavy, e.g. driving motor. the lo ading operating induces noise and overlaps with the dc power. vdd d rops by the noise, and the system works under unsta ble power situation. the power on duration and power down duration are l onger in ac application. the system power on sequen ce protects the power on successful, but the power down situati on is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead-band for a while.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 47 v0.9 3.4.2 the system operating voltage decsription to improve the brown out reset needs to know the sy stem minimum operating voltage which is depend on t he system executing rate and power level. different system ex ecuting rates have different system minimum operati ng voltage. the electrical characteristic section shows the sys tem voltage to executing rate relationship. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area normally the system operation voltage area is highe r than the system reset voltage to vdd, and the res et voltage is decided by lvd detect level. the system minimum ope rating voltage rises when the system executing rate upper even higher than system reset voltage. the dead-band def inition is the system minimum operating voltage abo ve the system reset voltage. 3.4.3 brown out reset improvement how to improve the brown reset condition? there are some methods to improve brown out reset a s following. lvd reset watchdog reset reduce the system executing rate external reset circuit. (zener diode reset circuit, voltage bias reset circuit, external reset ic) note: 1. the ? zener diode reset circuit?, ?voltage bias reset circuit? and ?external reset ic? c an completely improve the brown out reset, dc low batt ery and ac slow power down conditions. 2. for ac power application and enhance eft perform ance, the system clock is 4mhz/4 (1 mips) and use external reset (? zener diode reset circuit ?, ?voltage bias reset circuit?, ? external reset ic?). the structure can improve noise effective and get good eft characteristic.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 48 v0.9 lvd reset: vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset. the lvd (low voltage detector) is built-in sonix 8- bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be trigg ered, and the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of volta ge and not easy to cover all dead-band range. using lvd to improve brown out reset is depend on application re quirement and environment. if the power variation i s very deep, violent and trigger the lvd, the lvd can be the pro tection. if the power variation can touch the lvd d etect level and make system work error, the lvd can?t be the protec tion and need to other reset methods. more detail l vd information is in the electrical characteristic section. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog t imer in several addresses. the system executes norm ally and the watchdog won?t reset system. when the system is und er dead-band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously c ounting until overflow occurrence. the overflow sig nal of watchdog timer triggers the system to reset, and th e system return to normal mode after reset sequence . this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is st ill in dead-band, the system reset sequence won?t b e successful and the system stays in reset status until the powe r return to normal range. reduce the system executing rate: if the system rate is fast and the dead-band exists , to reduce the system executing rate can improve t he dead-band. the lower system rate is with lower minimum operati ng voltage. select the power voltage that?s no dead -band issue and find out the mapping system rate. adjust the sy stem rate to the value and the system exits the dea d-band issue. this way needs to modify whole program timing to fi t the application requirement. external reset circuit: the external reset methods also can improve brown o ut reset and is the complete solution. there are th ree external reset circuits to improve brown out reset including ?zener diode reset circuit?, ?voltage bias reset c ircuit? and ?external reset ic?. these three reset structures use externa l reset signal and control to make sure the mcu be reset under power dropping and under dead-band. the external re set information is described in the next section.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 49 v0.9 3.5 external reset external reset pin is schmitt trigger structure and low level active. the system is running when reset pin is high level voltage input. the reset pin receives the low volta ge and the system is reset. the external reset oper ation actives in power on and normal running mode. during system pow er-up, the external reset pin must be high level in put, or the system keeps in reset status. external reset sequen ce is as following. external reset: system checks external reset pin status. if extern al reset pin is not high level, the system keeps reset status and waits external reset pin released. system initialization: all system registers is set as initial conditions and system is ready. oscillator warm up: oscillator operation is successfully and supply to system clock. program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during powe r on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in ac power application? 3.6 external reset circuit 3.6.1 simply rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow ri sing signal into reset pin as power up. the reset signal is slower t han vdd power up timing, and system occurs a power on signal from the timing difference. note: the reset circuit is no any protection agains t unusual power or brown out reset.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 50 v0.9 3.6.2 diode & rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm this is the better reset circuit. the r1 and c1 cir cuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against u nusual power. the diode offers a power positive pat h to conduct higher power to vdd. it is can make reset pin volta ge level to synchronize with vdd voltage. the struc ture can improve slight brown out reset condition. note: the r2 100 ohm resistor of ?simply reset circ uit? and ?diode & rc reset circuit? is necessary to limit any current flowing into reset pin from exter nal capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or e lectrical over-stress (eos). 3.6.3 zener diode reset circuit mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b the zener diode reset circuit is a simple low volta ge detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vd d voltage level is above ?vz + 0.7v?, the c termina l of the pnp transistor outputs high voltage and mcu ope rates normally. when vdd is below ?vz + 0.7v?, the c terminal of the pnp transistor outputs low voltage and mcu is i n reset mode. decide the reset detect voltage by ze ner specification. select the right zener voltage to co nform the application.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 51 v0.9 3.6.4 voltage bias reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b the voltage bias reset circuit is a low cost voltag e detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diod e reset circuit. use r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to ?0.7v x (r1 + r2) / r1?, the c terminal of the pnp transistor o utputs high voltage and mcu operates normally. when vdd is belo w ?0.7v x (r1 + r2) / r1?, the c terminal of the pn p transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistanc es. select the right r1, r2 value to conform the ap plication. in the circuit diagram condition, the mcu?s reset pin leve l varies with vdd voltage variation, and the differ ential voltage is 0.7v. if the vdd drops and the voltage lower than r eset pin detect level, the system would be reset. i f want to make the reset active earlier, set the r2 > r1 and the cap b etween vdd and c terminal voltage is larger than 0. 7v. the external reset circuit is with a stable current through r1 a nd r2. for power consumption issue application, e.g . dc power system, the current must be considered to whole sys tem power consumption. note: under unstable power condition as brown out r eset, ?zener diode rest circuit? and ? voltage bias reset circuit? can protect s system no any error occurrence as power dropping. when power drops below the reset detect voltage, the system reset wo uld be triggered, and then system executes reset sequence. that makes sure the system work wel l under unstable power situation.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 52 v0.9 3.6.5 external reset ic mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf the external reset circuit also use external reset ic to enhance mcu reset performance. this is a high cost and good effect solution. by different application and syste m requirement to select suitable reset ic. the rese t circuit can improve all power variation.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 53 v0.9 4 4 4 system clock 4.1 overview the micro-controller is a dual clock system. there are high-speed clock and low-speed clock. the high- speed clock is generated from the external oscillator circuit or o n-chip 16mhz high-speed rc oscillator circuit (ihrc 16mhz). the low-speed clock is generated from on-chip low-speed rc oscillator circuit (ilrc 16khz @3v, 32khz @5v). both the high-speed clock and the low-speed clock c an be system clock (fosc). the system clock in slow mode is divided by 4 to be the instruction cycle (fcpu). normal mode (high clock): fcpu = fhosc / n , n = 1 ~ 128 select n by fcpu code option. slow mode (low clock): fcpu = flosc/4. sonix provides a ?noise filter? controlled by code option. in high noisy situation , the noise filter can isolate noise outside and protect system works well. the minimum fcpu of high clock is limited at fhosc/4 when noise filter enable. 4.2 clock block diagram fhosc. fcpu = fhosc/1 ~ fhosc/128, noise filter disable. fcpu = fhosc/4 ~ fhosc/128, noise filter enable. flosc. fcpu = flosc/4 cpum[1:0] xin xout stphx hosc fcpu code option fosc fosc clkmd fcpu hosc: high_clk code option. fhosc: external high-speed clock / internal high-s peed rc clock. flosc: internal low-speed rc clock (about 16khz@3v , 32khz@5v). fosc: system clock source. fcpu: instruction cycle.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 54 v0.9 4.3 oscm register the oscm register is an oscillator control register . it controls oscillator status, system mode. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm - - - cpum1 cpum0 clkmd stphx - read/write - - - r/w r/w r/w r/w - after reset - - - 0 0 0 0 - bit 1 stphx: external high-speed oscillator control bit. 0 = external high-speed oscillator free run. 1 = external high-speed oscillator free run stop. i nternal low-speed rc oscillator is still running. bit 2 clkmd: system high/low clock mode control bit. 0 = normal (dual) mode. system clock is high clock. 1 = slow mode. system clock is internal low clock. bit[4:3] cpum[1:0]: cpu operating mode control bits. 00 = normal. 01 = sleep (power down) mode. 10 = green mode. 11 = reserved. example: stop high-speed oscillator b0bset fstphx ; to stop external high-speed oscill ator only. example: when entering the power down mode (sleep m ode), both high-speed oscillator and internal low-speed oscillator will be stopped. b0bset fcpum0 ; to stop external high-speed oscill ator and internal low-speed ; oscillator called power down mode (sleep mode) .
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 55 v0.9 4.4 system high clock the system high clock is from internal 16mhz oscill ator rc type or external oscillator. the high clock type is controlled by ?high_clk? code option. high_clk code option description ihrc_16m the high clock is internal 16mhz oscillator rc type . xin and xout pins are general purpose i/o pins. ihrc_rtc the high clock is internal 16mhz oscillator rc type . xin and xout pins connect with 32768hz crystal for rtc clock source. rc the high clock is external rc type oscillator. x out pin is general purpose i/o pin. 32k the high clock is external 32768hz low speed os cillator. 12m the high clock is external high speed oscillato r. the typical frequency is 12mhz. 4m the high clock is external oscillator. the typic al frequency is 4mhz. 4.4.1 internal high rc the chip is built-in rc type internal high clock (1 6mhz) controlled by ?ihrc_16m? or ?ihrc_rtc? code o ptions. in ?ihrc_16m? mode, the system clock is from internal 16mhz rc type oscillator and xin / xout pins are general-purpose i/o pins. in ?ihrc_rtc? mode, the s ystem clock is from internal 16mhz rc type oscillat or and xin / xout pins are connected with external 32768 crystal for real time clock (rtc). ihrc: high clock is internal 16mhz oscillator rc type. x in/xout pins are general purpose i/o pins. ihrc_rtc: high clock is internal 16mhz oscillator rc type. x in/xout pins are connected with external 32768hz crystal/ceramic oscillator for rtc clock so urce. the rtc period is controlled by option register and rtc timer is t0. please consult ?t0 timer? chapter to apply rtc function. 4.4.2 external high clock external high clock includes three modules (crystal /ceramic, rc and external clock signal). the high c lock oscillator module is controlled by high_clk code option. the s tart up time of crystal/ceramic and rc type oscilla tor is different. rc type oscillator?s start-up time is very short, b ut the crystal?s is longer. the oscillator start-up time decides reset time length. rc 4mhz ceramic 4mhz crystal 32768hz crystal
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 56 v0.9 4.4.2.1 crystal/ceramic crystal/ceramic devices are driven by xin, xout pin s. for high/normal/low frequency, the driving curre nts are different. high_clk code option supports different frequencies. 12m option is for high speed (ex. 12mh z). 4m option is for normal speed (ex. 4mhz). 32k option is for low speed (ex. 32768hz). mcu vcc gnd c 20pf xin x o u t vdd vss c 20pf crystal note: connect the crystal/ceramic and c as near as possible to the xin/xout/vss pins of micro-controller. 4.4.2.2 rc selecting rc oscillator is by rc option of high_clk code option. rc type oscillator?s frequency is up to 10mhz. using ?r? value is to change frequency. 50p~100p is good value for ?c?. xout pin is general purpose i/o pin. r mcu vcc gnd xin x o u t v d d vss c note: connect the r and c as near as possible to th e vdd pin of micro-controller.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 57 v0.9 4.4.2.3 external clock signal selecting external clock signal input to be system clock is by rc option of high_clk code option. the external clock signal is input from xin pin. xout pin is general p urpose i/o pin. mcu vcc gnd vss vdd xin xout external clock input note: the gnd of external oscillator circuit must b e as near as possible to vss pin of micro-controlle r.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 58 v0.9 4.5 system low clock the system low clock source is the internal low-spe ed oscillator built in the micro-controller. the lo w-speed oscillator uses rc type oscillator circuit. the frequency is a ffected by the voltage and temperature of the syste m. in common condition, the frequency of the rc oscillator is ab out 16khz at 3v and 32khz at 5v. the relation betwe en the rc frequency and voltage is as the following figure. intern al low rc frequen cy intern al low rc frequen cy intern al low rc frequen cy intern al low rc frequen cy 10.0khz 20.0khz 30.0khz 40.0khz 50.0khz 60.0khz 2.4 2.6 2.8 3.0 3.2 3.3 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 vdd(v) vdd(v) vdd(v) vdd(v) frequency frequency frequency frequency the internal low rc supports watchdog clock source and system slow mode controlled by clkmd. flosc = internal low rc oscillator (about 32 khz @3 .3v). slow mode fcpu = flosc / 4 the only one condition to stop internal low rc is t he system into power down mode with watchdog disabl e or enable. system into power down mode with watchdog set alway s_on in code option, the ilrc is still running and watchdog is active well. b0bset fcpum0 ; to stop ihrc and ilrc oscillator c alled power down mode ; (sleep mode). note: the internal low-speed clock can?t be turned off individually. it is controlled by cpum0, cpum1 (32k, watchdog disable) bits of oscm register.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 59 v0.9 4.5.1 system clock measurement under design period, the users can measure system c lock speed by software instruction cycle (fcpu). th is way is useful in rc mode. example: fcpu instruction cycle of external oscilla tor. b0bset p0m.0 ; set p0.0 to be output mode for outp utting fcpu toggle signal. @@: b0bset p0.0 ; output fcpu toggle signal in low-spe ed clock mode. b0bclr p0.0 ; measure the fcpu frequency by oscill oscope. jmp @b note: do not measure the rc frequency directly from xin; the probe impendence will affect the rc frequency.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 60 v0.9 5 5 5 system operation mode 5.1 overview the chip is featured with low power consumption by switching around four different modes as following. normal mode (high-speed mode) slow mode (low-speed mode) power-down mode (sleep mode) green mode power down mode (sleep mode) slow mode green mode normal mode clkmd = 1 clkmd = 0 p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01. cpum1, cpum0 = 10. p0, p1 wake-up function active. t0 timer time out. external reset circuit active. p0, p1 wake-up function active. t0 timer time out. external reset circuit active. system mode switching diagram operating mode description mode normal slow green power down (sleep) remark ehosc running by stphx by stphx stop ilrc running running running stop cpu instruction executing executing stop stop t0 timer *active *active *active inactive * active if t0enb=1 tc0 timer *active *active *active inactive * active if tc0enb=1 tc1 timer *active *active *active inactive * active if tc1enb=1 watchdog timer by watch_dog code option by watch_dog code option by watch_dog code option by watch_dog code option refer to code option description internal interrupt all active all active t0, tc0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, t0 reset p0, p1, reset ehosc : external high clock ilrc : internal low clock (16k rc oscillator at 3v, 32k at 5v)
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 61 v0.9 5.2 system mode switching example: switch normal/slow mode to power down (sle ep) mode. b0bset fcpum0 ; set cpum0 = 1. note: during the sleep, only the wakeup pin and res et can wakeup the system back to the normal mode. example: switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high-speed oscilla tor for power saving. example: switch slow mode to normal mode (the exter nal high-speed oscillator is still running) b0bclr fclkmd ;to set clkmd = 0 example: switch slow mode to normal mode (the exter nal high-speed oscillator stops) if external high clock stop and program want to swi tch back normal mode. it is necessary to delay at l east 20ms for external clock stable. b0bclr fstphx ; turn on the external high-speed os cillator. b0mov z, #54 ; if vdd = 5v, internal rc=32khz (typ ical) will delay @@: decms z ; 0.125ms x 162 = 20.25ms for external clock stable jmp @b b0bclr fclkmd ; change the system back to the norm al mode example: switch normal/slow mode to green mode. b0bset fcpum1 ; set cpum1 = 1. note: if t0 timer wakeup function is disabled in th e green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation m ode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 62 v0.9 example: switch normal/slow mode to green mode and enable t0 wakeup function. ; set t0 timer wakeup function. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial value = 74h (to s et t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer ; go into green mode b0bclr fcpum0 ;to set cpumx = 10 b0bset fcpum1 note: during the green mode with t0 wake-up functio n, the wakeup pins, reset pin and t0 can wakeup the system back to the last mode. t0 wake-up period is controlled by program and t0enb must be set.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 63 version 0.9 5.3 wakeup 5.3.1 overview under power down mode (sleep mode) or green mode, p rogram doesn?t execute. the wakeup trigger can wake the system up to normal mode or slow mode. the wakeup t rigger sources are external trigger (p0, p1 level c hange) and internal trigger (t0 timer overflow). power down mode is waked up to normal mode. the wa keup trigger is only external trigger (p0, p1 level change) green mode is waked up to last mode (normal mode o r slow mode). the wakeup triggers are external trig ger (p0, p1 level change) and internal trigger (t0 timer ove rflow). 5.3.2 wakeup time when the system is in power down mode (sleep mode), the high clock oscillator stops. when waked up fro m power down mode, mcu waits for 4096 external high-speed o scillator clocks as the wakeup time to stable the o scillator circuit. after the wakeup time, the system goes into the nor mal mode. note: wakeup from green mode is no wakeup time beca use the clock doesn?t stop in green mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 4096 (sec) + high cloc k start-up time note: the high clock start-up time is depended on t he vdd and oscillator type of high clock. example: in power down mode (sleep mode), the syste m is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the fo llowing. the wakeup time = 1/fosc * 4096 = 1.024 ms (fosc = 4mhz) the total wakeup time = 1.024ms + oscillator start- up time
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 64 version 0.9 5.3.3 p1w wakeup control register under power down mode (sleep mode) and green mode, the i/o ports with wakeup function are able to wake the system up to normal mode. the port 0 and port 1 hav e wakeup function. port 0 wakeup function always en ables, but the port 1 is controlled by the p1w register. 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w p17w p16w p15w p14w p13w p12w p11w p10w read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit[7:0] p10w~p17w: port 1 wakeup function control bits. 0 = disable p1n wakeup function. 1 = enable p1n wakeup function.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 65 version 0.9 6 6 6 interrupt 6.1 overview this mcu provides nine interrupt sources, including six internal interrupt (t0/tc0/tc1/sio/adc/msp) an d three external interrupt (int0/int1/int2). the external i nterrupt can wakeup the chip while the system is sw itched from power down mode to high-speed normal mode, and inte rrupt request is latched until return to normal mod e. once interrupt service is executed, the gie bit in stkp register will clear to ?0? for stopping other inter rupt request. on the contrast, when interrupt service exits, the gie bit will set to ?1? to accept the next interrupts? req uest. all of the interrupt request signals are stored in intrq register. note: the gie bit must enable during all interrupt operation.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 66 version 0.9 6.2 inten interrupt enable register inten is the interrupt request control register inc luding three internal interrupts, two external inte rrupts enable control bits. one of the register to be set ?1? is to enabl e the interrupt request function. once of the inter rupt occur, the stack is incremented and program jump to org 8 to execute in terrupt service routines. the program exits the int errupt service routine when the returning interrupt service routin e instruction (reti) is executed. 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten adcien tc1ien tc0ien t0ien sioien p02ien p01ien p00 ien read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = disable int0 interrupt function. 1 = enable int0 interrupt function. bit 1 p01ien: external p0.1 interrupt (int1) control bit. 0 = disable int1 interrupt function. 1 = enable int1 interrupt function. bit 2 p02ien: external p0.2 interrupt (int2) control bit. 0 = disable int1 interrupt function. 1 = enable int1 interrupt function. bit 3 sioien: sio interrupt control bit. 0 = disable sio interrupt function. 1 = enable sio interrupt function. bit 4 t0ien: t0 timer interrupt control bit. 0 = disable t0 interrupt function. 1 = enable t0 interrupt function. bit 5 tc0ien: tc0 timer interrupt control bit. 0 = disable tc0 interrupt function. 1 = enable tc0 interrupt function. bit 6 tc1ien: tc1 timer interrupt control bit. 0 = disable tc1 interrupt function. 1 = enable tc1 interrupt function. bit 7 adcien: adc interrupt control bit. 0 = disable adc interrupt function. 1 = enable adc interrupt function. 0c7h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten_1 - - - - - - - mspien read/write - - - - - - - r/w after reset - - - - - - - 0 bit 0 mspien: msp interrupt control bit.. 0 = disable 1 = enable
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 67 version 0.9 6.3 intrq interrupt request register intrq is the interrupt request flag register. the r egister includes all interrupt request indication f lags. each one of the interrupt requests occurs, the bit of the intrq reg ister would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interr upt vector of program, users know the any interrupt requests occurring by the register and do the routine corres ponding of the interrupt request. 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq adcirq tc1irq tc0irq t0irq sioirq p02irq p01irq p00 irq read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 p00irq: external p0.0 interrupt (int0) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. bit 1 p01irq: external p0.1 interrupt (int1) request flag. 0 = none int1 interrupt request. 1 = int1 interrupt request. bit 2 p02irq: external p0.2 interrupt (int2) request flag. 0 = none int1 interrupt request. 1 = int1 interrupt request. bit 3 sioirq: sio interrupt request flag. 0 = none sio interrupt request. 1 = sio interrupt request. bit 4 t0irq: t0 timer interrupt request flag. 0 = none t0 interrupt request. 1 = t0 interrupt request. bit 5 tc0irq: tc0 timer interrupt request flag. 0 = none tc0 interrupt request. 1 = tc0 interrupt request. bit 6 tc1irq: tc1 timer interrupt request flag. 0 = none tc1 interrupt request. 1 = tc1 interrupt request. bit 7 adcirq: adc interrupt request flag. 0 = none adc interrupt request. 1 = adc interrupt request. 0c6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq_1 - - - - - - - mspirq read/write - - - - - - - r/w after reset - - - - - - - 0 bit 0 mspirq: msp interrupt request bit. 0 = no request. 1 = request.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 68 version 0.9 6.4 gie global interrupt operation gie is the global interrupt control bit. all interr upts start work after the gie = 1 it is necessary f or interrupt service request. one of the interrupt requests occurs, and the program counter (pc) points to the interrupt ve ctor (org 8) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable global interrupt. 1 = enable global interrupt. ? example: set global interrupt control bit (gie). b0bset fgie ; enable gie note: the gie bit must enable during all interrupt operation. 6.5 push, pop routine when any interrupt occurs, system will jump to org 8 and execute interrupt service routine. it is nece ssary to save acc, pflag data. the chip includes ?push?, ?pop? fo r in/out interrupt service routine. the two instruc tions save and load acc , pflag data into buffers and avoid main routine error aft er interrupt service routine finishing. note: ?push?, ?pop? instructions save and load acc/ pflag without (nt0, npd). push/pop buffer is an unique buffer and only one level. example: store acc and paflg data by push, pop inst ructions when interrupt service routine executed. org 0 jmp start org 8 jmp int_service org 10h start: ? int_service: push ; save acc and pflag to buffers. ? ? pop ; load acc and pflag from buffers. reti ; exit interrupt service vector ? endp
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 69 version 0.9
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 70 version 0.9 6.6 external interrupt operation (int0~int2) sonix provides 3 sets external interrupt sources in the micro-controller. int0, int1 and int2 are exte rnal interrupt trigger sources and build in edge trigger configura tion function. when the external edge trigger occur s, the external interrupt request flag will be set to ?1? when the external interrupt control bit enabled. if the exte rnal interrupt control bit is disabled, the external interrupt request flag wo n?t active when external edge trigger occurrence. w hen external interrupt control bit is enabled and external inter rupt edge trigger is occurring, the program counter will jump to the interrupt vector (org 8) and execute interrupt serv ice routine. the external interrupt builds in wake-up latch func tion. that means when the system is triggered wake- up from power down mode, the wake-up source is external interrupt source (p0.0, p0.1 or p0.2), and the trigger edge direction matches interrupt edge configuration, the trigger e dge will be latched, and the system executes interr upt service routine fist after wake-up. 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge - - p02g1 p02g0 p01g1 p01g0 p00g1 p00g0 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 bit[5:4] p02g[1:0]: int2 edge trigger select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. bit[3:2] p01g[1:0]: int1 edge trigger select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. bit[1:0] p00g[1:0]: int0 edge trigger select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. example: setup int0 interrupt request and bi-direct ion edge trigger. mov a, #98h b0mov pedge, a ; set int0 interrupt trigger as bi- direction edge. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq ? ; int0 interrupt service routine exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 71 version 0.9 6.7 t0 interrupt operation when the t0c counter occurs overflow, the t0irq wil l be set to ?1? however the t0ien is enable or disa ble. if the t0ien = 1, the trigger event will make the t0irq to be ?1? and the system enter interrupt vector. if t he t0ien = 0, the trigger event will make the t0irq to be ?1? but the system will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m, a ; set t0 clock = fcpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. ? ; t0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 72 version 0.9 6.8 tc0 interrupt operation when the tc0c counter overflows, the tc0irq will be set to ?1? no matter the tc0ien is enable or disab le. if the tc0ien and the trigger event tc0irq is set to be ?1 ?. as the result, the system will execute the inte rrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set t o be ?1?. moreover, the system won?t execute inter rupt vector even when the tc0irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt s ituation. example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. ? ; tc0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 73 version 0.9 6.9 tc1 interrupt operation when the tc1c counter overflows, the tc1irq will be set to ?1? no matter the tc1ien is enable or disab le. if the tc1ien and the trigger event tc1irq is set to be ?1 ?. as the result, the system will execute the inte rrupt vector. if the tc1ien = 0, the trigger event tc1irq is still set t o be ?1?. moreover, the system won?t execute inter rupt vector even when the tc1irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt s ituation. example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ftc1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = fcpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. ? ; tc1 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 74 version 0.9 6.10 sio interrupt operation when the sio converting successfully, the sioirq wi ll be set to ?1? no matter the sioien is enable or disable. if the sioien and the trigger event sioirq is set to be ?1 ?. as the result, the system will execute the inte rrupt vector. if the sioien = 0, the trigger event sioirq is still set t o be ?1?. moreover, the system won?t execute inter rupt vector even when the sioien is set to be ?1?. users need to be cautious with the operation under multi-interrupt s ituation. example: sio interrupt request setup. b0bset fsioien ; enable sio interrupt service b0bclr fsioirq ; clear sio interrupt request flag b0bset fgie ; enable gie example: sio interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 fsioirq ; check sioirq jmp exit_int ; sioirq = 0, exit interrupt vector b0bclr fsioirq ; reset sioirq ? ; sio interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 75 version 0.9 6.11 adc interrupt operation when the adc converting successfully, the adcirq wi ll be set to ?1? no matter the adcien is enable or disable. if the adcien and the trigger event adcirq is set to be ?1 ?. as the result, the system will execute the inte rrupt vector. if the adcien = 0, the trigger event adcirq is still s et to be ?1?. moreover, the system won?t execute i nterrupt vector even when the adcien is set to be ?1?. users need t o be cautious with the operation under multi-interr upt situation. example: adc interrupt request setup. b0bclr fadcien ; disable adc interrupt service mov a, #10110000b ; b0mov adm, a ; enable p4.0 adc input and adc funct ion. mov a, #00000000b ; set adc converting rate = fcpu /16 b0mov adr, a b0bset fadcien ; enable adc interrupt service b0bclr fadcirq ; clear adc interrupt request flag b0bset fgie ; enable gie b0bset fads ; start adc transformation example: adc interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . b0bts1 fadcirq ; check adcirq jmp exit_int ; adcirq = 0, exit interrupt vector b0bclr fadcirq ; reset adcirq ? ; adc interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 76 version 0.9 6.12 multi-interrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi -interrupt request requires setting the priority of the interr upt requests. the irq flags of interrupts are contr olled by the interrupt event. nevertheless, the irq flag ?1? doesn?t mean the system will execute the interrupt vector. in ad dition, which means the irq flags can be set ?1? by the events wi thout enable the interrupt. once the event occurs, the irq will be logic ?1?. the irq and its trigger event relationsh ip is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge p01irq p0.1 trigger controlled by pedge p02irq p0.2 trigger controlled by pedge t0irq t0c overflow tc0irq tc0c overflow tc1irq tc1c overflow sioirq sio transmitting end. adcirq adc converting end. for multi-interrupt conditions, two things need to be taking care of. one is to set the priority for t hese interrupt requests. two is using ien and irq flags to decide which inte rrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 77 version 0.9 example: check the interrupt request under multi-in terrupt operation org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers . intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intp01chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 intp01chk: ; check int1 interrupt request b0bts1 fp00ien ; check p01ien jmp intp02chk ; jump check to next interrupt b0bts0 fp01irq ; check p01irq jmp intp01 intp02chk: ; check int2 interrupt request b0bts1 fp00ien ; check p02ien jmp intt0chk ; jump check to next interrupt b0bts0 fp02irq ; check p02irq jmp intp02 intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp inttc0chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp inttc1chk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; jump to tc0 interrupt service routine inttc1chk: ; check t1 interrupt request b0bts1 ftc1ien ; check tc1ien jmp intsiohk ; jump check to next interrupt b0bts0 ftc1irq ; check tc1irq jmp intt1 ; jump to tc1 interrupt service routine intsiochk: ; check sio interrupt request b0bts1 fsioien ; check sioien jmp intadchk ; jump check to next interrupt b0bts0 fsioirq ; check sioirq jmp intsio ; jump to sio interrupt service routine intadchk: ; check adc interrupt request b0bts1 fadcien ; check adcien jmp int_exit ; jump to exit of irq b0bts0 fadcirq ; check adcirq jmp intadc ; jump to adc interrupt service routine int_exit: ? ; pop routine to load acc and pflag from buffer s. reti ; exit interrupt vector
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 78 version 0.9 7 7 7 i/o port 7.1 i/o port mode the port direction is programmed by pnm register. a ll i/o ports can select input or output direction. 0b8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0m - - - - - p02m p01m p00m read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m p17m p16m p15m p14m p13m p12m p11m p10m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m p27m p26m p25m p24m p23m p22m p21m p20m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p3m - - - - - p32m p31m p30m read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0c4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4m p47m p46m p45m p44m p43m p42m p41m p40m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m p57m p56m p55m p54m p53m p52m p51m p50m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~5). 0 = pn is input mode. 1 = pn is output mode. note: users can program them by bit control instruc tions (b0bset, b0bclr). note: if not used adc function, avdd must be connec t with vdd, otherwise p4 i/o maybe error.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 79 version 0.9 example: i/o mode selecting clr p0m ; set all ports to be input mode. clr p4m clr p5m mov a, #0ffh ; set all ports to be output mode. b0mov p0m, a b0mov p4m,a b0mov p5m, a b0bclr p4m.0 ; set p4.0 to be input mode. b0bset p4m.0 ; set p4.0 to be output mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 80 version 0.9 7.2 i/o pull up register 0e0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0ur - - - - - p02r p01r p00r read/write - - - - - w w w after reset - - - - - 0 0 0 0e1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1ur p17r p16r p15r p14r p13r p12r p11r p10r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2ur p27r p26r p25r p24r p23r p22r p21r p20r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p3ur - - - - - p32r p31r p30r read/write - - - - - w w w after reset - - - - - 0 0 0 0e4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4ur p47r p46r p45r p44r p43r p42r p41r p40r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5ur p57r p56r p55r p54r p53r p52r p51r p50r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 example: i/o pull up register mov a, #0ffh ; enable port0, 4, 5 pull-up register , b0mov p0ur, a ; b0mov p4ur,a b0mov p5ur, a
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 81 version 0.9 7.3 i/o port data register 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - p02 p01 p00 read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p3 - - - - - p32 p31 p30 read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0d4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4 p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 p57 p56 p55 p54 p53 p52 p51 p50 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p4 ; read data from port 4 b0mov a, p5 ; read data from port 5 example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p0, a b0mov p4, a b0mov p5, a example: write one bit data to output port. b0bset p4.0 ; set p4.0 and p5.3 to be ?1?. b0bset p5.3 b0bclr p4.0 ; set p4.0 and p5.3 to be ?0?. b0bclr p5.3
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 82 version 0.9 7.4 i/o open-drain register p1.0/p1.1/p5.2 is built-in open-drain function. p1. 0/p1.1/p5.2 must be set as output mode when enable open-drain function. open-drain external circuit is as followi ng. u mcu2 u vcc open-drain pin open-drain pin mcu1 pull-up resistor the pull-up resistor is necessary. open-drain outpu t high is driven by pull-up resistor. output low is sunken by mcu?s pin. 0e9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1oc - - - - - p52oc p11oc p10oc read/write - - - - - w w w after reset - - - - - 0 0 0 bit 2 p52oc: p5.2 open-drain control bit 0 = disable open-drain mode 1 = enable open-drain mode bit 1 p11oc: p1.1 open-drain control bit 0 = disable open-drain mode 1 = enable open-drain mode bit 0 p10oc: p1.0 open-drain control bit 0 = disable open-drain mode 1 = enable open-drain mode example: enable p1.0 to open-drain mode and output high. b0bset p1.0 ; set p1.0 buffer high. b0bset p10m ; enable p1.0 output mode. mov a, #01h ; enable p1.0 open-drain function. b0mov p1oc, a note: p1oc is write only register. setting p10oc mu st be used ?mov? instructions. example: disable p1.0 to open-drain mode and output low. mov a, #0 ; disable p1.0 open-drain function. b0mov p1oc, a note: after disable open-drain function, i/o mode r eturns to last i/o mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 83 version 0.9 7.5 port 4 adc share pin the port 4 is shared with adc input function and no schmitt trigger structure. only one pin of port 4 can be configured as adc input in the same time by adm register. the other pins of port 4 are digital i/o pins. connect an analog signal to coms digital input pin, especially the analog si gnal level is about 1/2 vdd will cause extra curren t leakage. in the power down mode, the above leakage current will be a big problem. unfortunately, if users connect more than one analog input signal to port 4 will encounter above current leakage situation. p4con is port4 configura tion register. write ?1? into p4con.n will configure related port 4 pin as pure analog input pin to avoid current lea kage. 0aeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4con p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4 con0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[4:0] p4con[7:0]: p4.n configuration control bits. 0 = p4.n can be an analog input (adc input) or di gital i/o pins. 1 = p4.n is pure analog input, can?t be a digital i/o pin. note: when port 4.n is general i/o port not adc cha nnel, p4con.n must set to ?0? or the port 4.n digit al i/o signal would be isolated. port 4 adc analog input is controlled by gchs and c hsn bits of adm register. if gchs = 0, p4.n is gene ral purpose bi-direction i/o port. if gchs = 1, p4.n pointed by chsn is adc analog signal input pin. users should set p4 adc input pin as input mode without pull-up. 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs - chs2 chs1 chs0 read/write r/w r/w r/w r/w - r/w r/w r/w after reset 0 0 0 0 - 0 0 0 bit 4 gchs: global channel select bit. 0 = disable ain channel. 1 = enable ain channel. bit[2:0] chs[2:0]: adc input channels select bit. 000 = ain0, 001 = ain1, ? 110 = ain6, 111 = ain7. note: for p4.n general purpose i/o function, users should make sure of p4.n?s adc channel is disabled.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 84 version 0.9 example: set p4.1 to be general purpose input mode. p4con.1 must be set as ?0?. ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.1 (chs[2:0] = 001b), set g chs=0 ;if chs[2:0] don?t point to p4.1 (chs[2:0] 001b), don?t care gchs status. ; clear p4con. b0bclr p4con.1 ; enable p4.1 digital function. ; enable p4.1 input mode. b0bclr p4m.1 ; set p4.1 as input mode. example: set p4.1 to be general purpose output. p4c on.1 must be set as ?0?. ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.1 (chs[2:0] = 001b), set g chs=0. ;if chs[2:0] don?t point to p4.1 (chs[2:0] 001b), don?t care gchs status. ; clear p4con. b0bclr p4con.1 ; enable p4.1 digital function. ; set p4.1 output buffer to avoid glitch. b0bset p4.1 ; set p4.1 buffer as ?1?. ; or b0bclr p4.1 ; set p4.1 buffer as ?0?. ; enable p4.1 output mode. b0bset p4m.1 ; set p4.1 as input mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 85 version 0.9 8 8 8 timers 8.1 watchdog timer the watchdog timer (wdt) is a binary up counter des igned for monitoring program execution. if the prog ram goes into the unknown status by noise interference, wdt overf low signal raises and resets mcu. watchdog clock co ntrolled by code option and the clock source is internal low-sp eed oscillator (16khz @3v, 32khz @5v). watchdog overflow time = 8192 / internal low-speed oscillator (sec). vdd internal low rc freq. watchdog overflow time 3v 16khz 512ms 5v 32khz 256ms note: 1. if watchdog is ?always_on? mode, it keeps runnin g event under power down mode or green mode. 2. for s8kd ice simulation, clear watchdog timer us ing ?@rst_wdt? macro is necessary. or the s8kd watchdog would be error. watchdog clear is controlled by wdtr register. movi ng 0x5a data into wdtr is to reset watchdog timer. 0cch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdtr wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 example: an operation of watchdog timer is as follo wing. to clear the watchdog timer counter in the to p of the main routine of the program. main: mov a, #5ah ; clear the watchdog timer. b0mov wdtr, a ? ? call sub1 call sub2 ? ? jmp main
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 86 version 0.9 example: clear watchdog timer by @rst_wdt macro. main: @rst_wdt ; clear the watchdog timer. ? ? call sub1 call sub2 ? ? jmp main watchdog timer application note is as following. before clearing watchdog timer, check i/o status a nd check ram contents can improve system error. don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main r outine fail. clearing watchdog timer program is only at one par t of the program. this way is the best structure to enhance the watchdog timer function. example: an operation of watchdog timer is as follo wing. to clear the watchdog timer counter in the to p of the main routine of the program. main: ? ; check i/o. ? ; check ram err: jmp $ ; i/o or ram error. program jump here a nd don?t ; clear watchdog. wait watchdog timer overflow t o reset ic. correct: ; i/o and ram are correct. clear watchdo g timer and ; execute program. b0bset fwdrst ; only one clearing watchdog timer o f whole program. ? call sub1 call sub2 ? ? ? jmp main
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 87 version 0.9 8.2 timer 0 (t0) 8.2.1 overview the t0 is an 8-bit binary up timer and event counte r. if t0 timer occurs an overflow (from ffh to 00h) , it will continue counting and issue a time-out signal to trigger t0 interrupt to request interrupt service. the main purposes of the t0 timer is as following. 8-bit programmable up counting timer: generates interrupts at specific time intervals bas ed on the selected clock frequency. rtc timer: generates interrupts at real time intervals based o n the selected clock source. rtc function is only available in t0tb=1. green mode wakeup function: t0 can be green mode wake-up time as t0enb = 1. sy stem will be wake-up by t0 time out. fcpu t0 rate (fcpu/2~fcpu/256) t0enb cpum0,1 t0c 8-bit binary up counting counter t0 time out load internal data bus t0enb rtc t0tb note: in rtc mode, the t0 interval time is fixed at 0.5 sec and isn?t controlled by t0c.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 88 version 0.9 8.2.2 t0m mode register 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 - t0tb read/write r/w r/w r/w r/w r/w r/w - r/w after reset 0 0 0 0 0 0 - 0 bit 0 t0tb: rtc clock source control bit. 0 = disable rtc (t0 clock source from fcpu). 1 = enable rtc, t0 will be 0.5 sec rtc (low clock m ust be 32768 cyrstal). bit 2 tc0x8: tc0 internal clock source control bit. 0 = tc0 internal clock source is fcpu. tc0rate is f rom fcpu/2~fcpu/256. 1 = tc0 internal clock source is fosc. tc0rate is f rom fosc/1~fosc/128. bit 3 tc1x8: tc1 internal clock source control bit. 0 = tc1 internal clock source is fcpu. tc1rate is f rom fcpu/2~fcpu/256. 1 = tc1 internal clock source is fosc. tc1rate is f rom fosc/1~fosc/128. bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer. note: t0rate is not available in rtc mode. the t0 i nterval time is fixed at 0.5 sec.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 89 version 0.9 8.2.3 t0c counting register t0c is an 8-bit counter register for t0 interval ti me control. 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) example: to set 10ms interval time for t0 interrupt . high clock is external 4mhz. fcpu=fosc/4. select t0rate=010 (fcpu/64). t0c initial value = 256 - (t0 interrupt interval ti me * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of t0. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 1) t0rate t0clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 2000 ms 7812.5 us 001 fcpu/128 32.768 ms 128 us 1000 ms 3906.25 us 010 fcpu/64 16.384 ms 64 us 500 ms 1953.12 us 011 fcpu/32 8.192 ms 32 us 250 ms 976.56 us 100 fcpu/16 4.096 ms 16 us 125 ms 488.28 us 101 fcpu/8 2.048 ms 8 us 62.5 ms 244.14 us 110 fcpu/4 1.024 ms 4 us 31.25 ms 122.07 us 111 fcpu/2 0.512 ms 2 us 15.625 ms 61.035 us note: t0c is not available in rtc mode. the t0 inte rval time is fixed at 0.5 sec.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 90 version 0.9 8.2.4 t0 timer operation sequence t0 timer operation sequence of setup t0 timer is as following. stop t0 timer counting, disable t0 interrupt functi on and clear t0 interrupt request flag. b0bclr ft0enb ; t0 timer. b0bclr ft0ien ; t0 interrupt function is disabled. b0bclr ft0irq ; t0 interrupt request flag is clear ed. set t0 timer rate. mov a, #0xxx0000b ;the t0 rate control bits exist in bit4~bit6 of t0m. the ; value is from x000xxxxb~x111xxxxb. b0mov t0m,a ; t0 timer is disabled. set t0 clock source from fcpu or rtc. b0bclr ft0tb ; select t0 fcpu clock source. or b0bset ft0tb ; select t0 rtc clock source. set t0 interrupt interval time. mov a,#7fh b0mov t0c,a ; set t0c value. set t0 timer function mode. b0bset ft0ien ; enable t0 interrupt function. enable t0 timer. b0bset ft0enb ; enable t0 timer.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 91 version 0.9 8.3 timer/counter 0 (tc0) 8.3.1 overview the tc0 is an 8-bit binary up counting timer. tc0 h as two clock sources including internal clock and e xternal clock for counting a precision time. the internal clock sourc e is from fcpu. the external clock is int0 from p0. 0 pin (falling edge trigger). using tc0m register selects tc0c?s c lock source from internal or external. if tc0 timer occurs an overflow, it will continue counting and issue a tim e-out signal to trigger tc0 interrupt to request in terrupt service. tc0 overflow time is 0xff to 0x00 normally. under pwm m ode, tc0 overflow is still 256 counts. the main purposes of the tc0 timer is as following. 8-bit programmable up counting timer: generates interrupts at specific time intervals bas ed on the selected clock frequency. external event counter: counts system ?events? based on falling edge detect ion of external clock signals at the int0 input pin. buzzer output pwm output fcpu tc0 rate (fcpu/2~fcpu/256) int0 (schmitter trigger) tc0cks tc0enb cpum0,1 tc0c 8-bit binary up counting counter tc0r reload data buffer compare aload0 rs tc0 time out auto. reload tc0 / 2 buzzer internal p5.4 i/o circuit p5.4 pwm pwm0out tc0out load
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 92 version 0.9 8.3.2 tc0m mode register 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm0out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc0ou t, aload0 bits. bit 1 tc0out: tc0 time out toggle signal output control bit. only valid when pwm0out = 0. 0 = disable, p5.4 is i/o function. 1 = enable, p5.4 is output tc0out signal. bit 2 aload0: auto-reload control bit. only valid when pwm0out = 0. 0 = disable tc0 auto-reload function. 1 = enable tc0 auto-reload function. bit 3 tc0cks: tc0 clock source select bit. 0 = internal clock (fcpu). 1 = external clock from p0.0/int0 pin. bit [6:4] tc0rate[2:0]: tc0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 tc0enb: tc0 counter control bit. 0 = disable tc0 timer. 1 = enable tc0 timer. note: when tc0cks=1, tc0 became an external event c ounter and tc0rate is useless. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0).
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 93 version 0.9 8.3.3 tc0c counting register tc0c is an 8-bit counter register for tc0 interval time control. 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc0c initial value is as following. tc0c initial value = 256 - (tc0 interrupt interva l time * input clock) example: to set 10ms interval time for tc0 interrup t. tc0 clock source is fcpu (tc0ks=0). high clock i s external 4mhz. fcpu=fosc/4. select tc0rate=010 (fcp u/64). tc0c initial value = 256 - (tc0 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of tc0. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us note: tc0c can?t be set as 0xff when tc0 timer oper ating in interrupt, buzzer output modes. tc0c available range is 0x00~0xfe. the problem doesn?t e xist in pure pwm mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 94 version 0.9 8.3.4 tc0r auto-load register tc0 timer is with auto-load function controlled by aload0 bit of tc0m. when tc0c overflow occurring, t c0r value will load to tc0c by system. it is easy to generate an accurate time, and users don?t reset tc0c durin g interrupt service routine. 0cdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc0r initial value is as following. tc0r initial value = n - (tc0 interrupt interval time * input clock) n is tc0 overflow boundary number. tc0 timer overfl ow time has five types (tc0 timer, tc0 event counte r, tc0 fcpu clock source, pwm mode and no pwm mode). these para meters decide tc0 overflow time and valid value as follow table. tc0cks pwm0 aload0 tc0out n tc0r valid value tc0r value binary type 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - 256 0x00~0xff 00000000b~11111111b example: to set 10ms interval time for tc0 interrup t. tc0 clock source is fcpu (tc0ks=0) and no pwm output (pwm0=0). high clock is external 4mhz. fcpu= fosc/4. select tc0rate=010 (fcpu/64). tc0r initial value = n - (tc0 interrupt interval ti me * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h note: tc0r can?t be set as 0xff when tc0 timer oper ating in interrupt, buzzer output modes. tc0r available range is 0x00~0xfe. the problem doesn?t e xist in pure pwm mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 95 version 0.9 8.3.5 tc0 clock frequency output (buzzer) buzzer output (tc0out) is from tc0 timer/counter fr equency output function. by setting the tc0 clock f requency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-disable. the tc0out f requency is divided by 2 from tc0 interval time. tc0out frequen cy is 1/2 tc0 frequency. the tc0 clock has many com binations and easily to make difference frequency. the tc0out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc1 overflow clock tc1out (buzzer) output clock example: setup tc0out output from tc0 to tc0out (p5 .4). the external high-speed clock is 4mhz. the tc0out frequency is 0.5khz. because the tc0out sign al is divided by 2, set the tc0 clock to 1khz. the tc0 clock source is from external oscillator clock. tc0 rate is fcpu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 131. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc0c,a b0mov tc0r,a b0bset ftc0out ; enable tc0 output to p5.4 and dis able p5.4 i/o function b0bset faload0 ; enable tc0 auto-reload function b0bset ftc0enb ; enable tc0 timer note: buzzer output is enabled, and ?pwm0out? must be ?0?.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 96 version 0.9 8.3.6 tc0 timer operation sequence tc0 timer operation includes timer interrupt, event counter, tc0out and pwm. the sequence of setup tc0 timer is as following. stop tc0 timer counting, disable tc0 interrupt func tion and clear tc0 interrupt request flag. b0bclr ftc0enb ; tc0 timer, tc0out and pwm stop. b0bclr ftc0ien ; tc0 interrupt function is disable d. b0bclr ftc0irq ; tc0 interrupt request flag is cle ared. set tc0 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc0 rate control bits exist in bit4~bit6 of tc0m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc0m,a ; tc0 timer is disabled. set tc0 timer clock source. ; select tc0 internal / external clock source. b0bclr ftc0cks ; select tc0 internal clock source. or b0bset ftc0cks ; select tc0 external clock source. set tc0 timer auto-load mode. b0bclr faload0 ; enable tc0 auto reload function. or b0bset faload0 ; disable tc0 auto reload function. set tc0 interrupt interval time, tc0out (buzzer) fr equency or pwm duty cycle. ; set tc0 interrupt interval time, tc0out (buzzer) frequency or pwm duty. mov a,#7fh ; tc0c and tc0r value is decided by tc0 mode. b0mov tc0c,a ; set tc0c value. b0mov tc0r,a ; set tc0r value under auto reload mod e or pwm mode. ; in pwm mode, set pwm cycle. b0bclr faload0 ; aload0, tc0out = 00, pwm cycle bou ndary is 0~255. b0bclr ftc0out or b0bclr faload0 ; aload0, tc0out = 01, pwm cycle bou ndary is 0~63. b0bset ftc0out or b0bset faload0 ; aload0, tc0out = 10, pwm cycle bou ndary is 0~31. b0bclr ftc0out or b0bset faload0 ; aload0, tc0out = 11, pwm cycle bou ndary is 0~15. b0bset ftc0out
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 97 version 0.9 set tc0 timer function mode. b0bset ftc0ien ; enable tc0 interrupt function. or b0bset ftc0out ; enable tc0out (buzzer) function. or b0bset fpwm0out ; enable pwm function. enable tc0 timer. b0bset ftc0enb ; enable tc0 timer. 8.3.7 tc0 timer notice when tc0c value changes from ?0xff? to not ?0xff?, tc0irq is set ?1? whether tc0 is operating or not. if tc0irq = 0 and tc0c is changed by program, tc0irq might be s et as tc0c is from ?0xff? to not ?0xff?. the condit ion makes unexpected tc0 interrupt occurring. example: tc0c = 0xff and tc0irq = 0. tc0irq will se t as ?1? when tc0c is cleared by program (tc0c = 0). mov a, #0 ; clear tc0c. b0mov tc0c, a ; tc0irq changed from ?0? to ?1?. b0bset ftc0ien ; enable tc0 interrupt function and system jumps to interrupt ; vector (org 8) at next cycle. if tc0c changing in system operating duration is ne cessary, to disable tc0 interrupt function (tc0ien = 0) before changing tc0c value. the solution can avoid unexpec ted tc0 interrupt occurring and example is as follo wing. example: tc0c = 0xff and tc0irq = 0. clearing tc0c must be after tc0 interrupt disable. b0bclr ftc0ien ; disable tc0 interrupt function. mov a, #0 ; clear tc0c. b0mov tc0c, a ; tc0irq changed from ?0? to ?1?. b0bclr ftc0irq ; clear tc0irq flag. b0bset ftc0ien ; enable tc0 interrupt function. ? ? note: disable tc0 interrupt function first, and loa d new tc0c value into tc0c buffer. this way can avo id unexpected tc0 interrupt occurring. note: tc0c and tc0r can?t be set as 0xff when tc0 t imer operating in interrupt, buzzer output modes. tc0c and tc0r available range is 0x00~0xfe. the pro blem doesn?t exist in pure pwm mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 98 version 0.9 8.4 timer/counter 1 (tc1) 8.4.1 overview the tc1 is an 8-bit binary up counting timer. tc1 h as two clock sources including internal clock and e xternal clock for counting a precision time. the internal clock sourc e is from fcpu. the external clock is int1 from p0. 1 pin (falling edge trigger). using tc1m register selects tc1c?s c lock source from internal or external. if tc1 timer occurs an overflow, it will continue counting and issue a tim e-out signal to trigger tc1 interrupt to request in terrupt service. tc1 overflow time is 0xff to 0x00 normally. under pwm m ode, tc1 overflow is still 256 counts. the main purposes of the tc1 timer is as following. 8-bit programmable up counting timer: generates interrupts at specific time intervals bas ed on the selected clock frequency. external event counter: counts system ?events? based on falling edge detect ion of external clock signals at the int1 input pin. buzzer output pwm output fcpu tc1 rate (fcpu/2~fcpu/256) int1 (schmitter trigger) tc1cks tc1enb cpum0,1 tc1c 8-bit binary up counting counter tc1r reload data buffer compare aload1 rs tc1 time out auto. reload tc1 / 2 buzzer internal p5.3 i/o circuit p5.3 pwm pwm1out tc1out load
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 99 version 0.9 8.4.2 tc1m mode register 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload1 tc1out pwm1out read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm1out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc1ou t, aload1 bits. bit 1 tc1out: tc1 time out toggle signal output control bit. only valid when pwm1out = 0. 0 = disable, p5.3 is i/o function. 1 = enable, p5.3 is output tc1out signal. bit 2 aload1: auto-reload control bit. only valid when pwm1out = 0. 0 = disable tc1 auto-reload function. 1 = enable tc1 auto-reload function. bit 3 tc1cks: tc1 clock source select bit. 0 = internal clock (fcpu). 1 = external clock from p0.1/int1 pin. bit [6:4] tc1rate[2:0]: tc1 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 tc1enb: tc1 counter control bit. 0 = disable tc1 timer. 1 = enable tc1 timer. note: when tc1cks=1, tc1 became an external event c ounter and tc1rate is useless. no more p0.1 interrupt request will be raised. (p0.1irq will be always 0).
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 100 version 0.9 8.4.3 tc1c counting register tc1c is an 8-bit counter register for tc1 interval time control. 0ddh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc1c initial value is as following. tc1c initial value = 256 - (tc1 interrupt interva l time * input clock) example: to set 10ms interval time for tc1 interrup t. tc1 clock source is fcpu (tc1ks=0). high clock i s external 4mhz. fcpu=fosc/4. select tc1rate=010 (fcp u/64). tc1c initial value = 256 - (tc1 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of tc1. high speed mode (fcpu = 4mhz / 4) low speed mode (f cpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us note: tc1c and tc1r can?t be set as 0xff when tc1 t imer operating in interrupt, buzzer output modes. tc1c and tc1r available range is 0x00~0xfe. the pro blem doesn?t exist in pure pwm mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 101 version 0.9 8.4.4 tc1r auto-load register tc1 timer is with auto-load function controlled by aload1 bit of tc1m. when tc1c overflow occurring, t c1r value will load to tc1c by system. it is easy to generate an accurate time, and users don?t reset tc1c durin g interrupt service routine. 0deh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1r tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc1r initial value is as following. tc1r initial value = n - (tc1 interrupt interval time * input clock) n is tc1 overflow boundary number. tc1 timer overfl ow time has five types (tc1 timer, tc1 event counte r, tc1 fcpu clock source, pwm mode and no pwm mode). these para meters decide tc1 overflow time and valid value as follow table. tc1cks pwm1 aload1 tc1out n tc1r valid value tc1r value binary type 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - 256 0x00~0xff 00000000b~11111111b example: to set 10ms interval time for tc1 interrup t. tc1 clock source is fcpu (tc1ks=0) and no pwm output (pwm1=0). high clock is external 4mhz. fcpu= fosc/4. select tc1rate=010 (fcpu/64). tc1r initial value = n - (tc1 interrupt interval ti me * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h note: tc1r can?t be set as 0xff when tc1 timer oper ating in interrupt, buzzer output modes. tc1r available range is 0x00~0xfe. the problem doesn?t e xist in pure pwm mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 102 version 0.9 8.4.5 tc1 clock frequency output (buzzer) buzzer output (tc1out) is from tc1 timer/counter fr equency output function. by setting the tc1 clock f requency, the clock signal is output to p5.3 and the p5.3 general purpose i/o function is auto-disable. the tc1out f requency is divided by 2 from tc1 interval time. tc1out frequen cy is 1/2 tc1 frequency. the tc1 clock has many com binations and easily to make difference frequency. the tc1out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc1 overflow clock tc1out (buzzer) output clock example: setup tc1out output from tc1 to tc1out (p5 .3). the external high-speed clock is 4mhz. the tc1out frequency is 0.5khz. because the tc1out sign al is divided by 2, set the tc1 clock to 1khz. the tc1 clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 131. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc1c,a b0mov tc1r,a b0bset ftc1out ; enable tc1 output to p5.3 and dis able p5.3 i/o function b0bset faload1 ; enable tc1 auto-reload function b0bset ftc1enb ; enable tc1 timer note: buzzer output is enabled, and ?pwm1out? must be ?0?.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 103 version 0.9 8.4.6 tc1 timer operation sequence tc1 timer operation includes timer interrupt, event counter, tc1out and pwm. the sequence of setup tc1 timer is as following. stop tc1 timer counting, disable tc1 interrupt func tion and clear tc1 interrupt request flag. b0bclr ftc1enb ; tc1 timer, tc1out and pwm stop. b0bclr ftc1ien ; tc1 interrupt function is disable d. b0bclr ftc1irq ; tc1 interrupt request flag is cle ared. set tc1 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc1 rate control bits exist in bit4~bit6 of tc1m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc1m,a ; tc1 timer is disabled. set tc1 timer clock source. ; select tc1 internal / external clock source. b0bclr ftc1cks ; select tc1 internal clock source. or b0bset ftc1cks ; select tc1 external clock source. set tc1 timer auto-load mode. b0bclr faload1 ; enable tc1 auto reload function. or b0bset faload1 ; disable tc1 auto reload function. set tc1 interrupt interval time, tc1out (buzzer) fr equency or pwm duty cycle. ; set tc1 interrupt interval time, tc1out (buzzer) frequency or pwm duty. mov a,#7fh ; tc1c and tc1r value is decided by tc1 mode. b0mov tc1c,a ; set tc1c value. b0mov tc1r,a ; set tc1r value under auto reload mod e or pwm mode. ; in pwm mode, set pwm cycle. b0bclr faload1 ; aload1, tc1out = 00, pwm cycle bou ndary is 0~255. b0bclr ftc1out or b0bclr faload1 ; aload1, tc1out = 01, pwm cycle bou ndary is 0~63. b0bset ftc1out or b0bset faload1 ; aload1, tc1out = 10, pwm cycle bou ndary is 0~31. b0bclr ftc1out or b0bset faload1 ; aload1, tc1out = 11, pwm cycle bou ndary is 0~15. b0bset ftc1out
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 104 version 0.9 set tc1 timer function mode. b0bset ftc1ien ; enable tc1 interrupt function. or b0bset ftc1out ; enable tc1out (buzzer) function. or b0bset fpwm1out ; enable pwm function. enable tc1 timer. b0bset ftc1enb ; enable tc1 timer. 8.4.7 tc1 timer notice when tc1c value changes from ?0xff? to not ?0xff?, tc1irq is set ?1? whether tc1 is operating or not. if tc1irq = 0 and tc1c is changed by program, tc1irq might be s et as tc1c is from ?0xff? to not ?0xff?. the condit ion makes unexpected tc1 interrupt occurring. example: tc1c = 0xff and tc1irq = 0. tc1irq will se t as ?1? when tc1c is cleared by program (tc1c = 0). mov a, #0 ; clear tc1c. b0mov tc1c, a ; tc1irq changed from ?0? to ?1?. b0bset ftc1ien ; enable tc1 interrupt function and sy stem jumps to interrupt ; vector (org 8) at next cycle. if tc1c changing in system operating duration is ne cessary, to disable tc1 interrupt function (tc1ien = 0) before changing tc1c value. the solution can avoid unexpec ted tc1 interrupt occurring and example is as follo wing. example: tc1c = 0xff and tc1irq = 0. clearing tc1c must be after tc1 interrupt disable. b0bclr ftc1ien ; disable tc1 interrupt function. mov a, #0 ; clear tc1c. b0mov tc1c, a ; tc1irq changed from ?0? to ?1?. b0bclr ftc1irq ; clear tc1irq flag. b0bset ftc1ien ; enable tc1 interrupt function. ? ? note: disable tc1 interrupt function first, and loa d new tc1c value into tc1c buffer. this way can avo id unexpected tc1 interrupt occurring. note: tc1c and tc1r can?t be set as 0xff when tc1 t imer operating in interrupt, buzzer output modes. tc1c and tc1r available range is 0x00~0xfe. the pro blem doesn?t exist in pure pwm mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 105 version 0.9 8.5 pwm0 mode 8.5.1 overview pwm function is generated by tc0 timer counter and output the pwm signal to pwm0out pin (p5.4). the 8- bit counter counts modulus 256, 64, 32, 16 controlled b y aload0, tc0out bits. the value of the 8-bit count er (tc0c) is compared to the contents of the reference register (tc0r). when the reference register value (tc0r) is equal to the counter value (tc0c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. the low-to-high ratio (duty) of the pwm0 output is tc0r /256, 64, 32, 16. note: tc0c and tc0r can be 0xff in pure pwm output. if pwm function is operating with tc0 interrupt, tc0c and tc0r can?t be set as 0xff and the availabl e range is 0x00~0xfe. aload0 tc0out pwm duty range tc0c valid value tc0r valid bits value max. pwm frequency (fcpu = 4mhz) remark 0 0 0/256~255/256 0x00~0xff 0x00~0xff 7.8125k overflow per 256 count 0 1 0/64~63/64 0x00~0x3f 0x00~0x3f 31.25k overflow per 64 count 1 0 0/32~31/32 0x00~0x1f 0x00~0x1f 62.5k overflow p er 32 count 1 1 0/16~15/16 0x00~0x0f 0x00~0x0f 125k overflow pe r 16 count the output duty of pwm is with different tc0r. duty range is from 0/256~255/256. tc0 clock tc0r=00h tc0r=01h tc0r=80h tc0r=ffh 0 1 128 254 255 ?? ?? 0 1 128 254 255 ?? ?? low low low high high low high
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 106 version 0.9 8.5.2 tc0irq and pwm duty in pwm mode, the frequency of tc0irq is depended on pwm duty range. from following diagram, the tc0irq frequency is related with pwm duty. tc0c value pwm0 output (duty range 0~255) pwm0 output (duty range 0~63) pwm0 output (duty range 0~31) pwm0 output (duty range 0~15) tc0 overflow, tc0irq = 1 0xff 0x00
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 107 version 0.9 8.5.3 pwm program example example: setup pwm0 output from tc0 to pwm0out (p5. 4). the external high-speed oscillator clock is 4mhz. fcpu = fosc/4. the duty of pwm is 30/256. the pwm frequency is about 1khz. the pwm clock source is from external oscillator clock. tc0 rate is fcpu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 30. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc0c,a b0mov tc0r,a b0bclr ftc0out ; set duty range as 0/256~255/256. b0bclr faload0 b0bset fpwm0out ; enable pwm0 output to p5.4 and d isable p5.4 i/o function b0bset ftc0enb ; enable tc0 timer note: the tc0r is write-only register. don?t proces s them using incms, decms instructions. example: modify tc0r registers? value. mov a, #30h ; input a number using b0mov instructi on. b0mov tc0r, a incms buf0 ; get the new tc0r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc0r, a note: the pwm can work with interrupt request.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 108 version 0.9 8.5.4 pwm0 duty changing notice in pwm mode, the system will compare tc0c and tc0r all the time. when tc0c sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 109 version 0.9 if tc0r is changing in the program processing, the pwm waveform will became as following diagram. 1 1st pwm 2 update pwm duty 3 2nd pwm 4 update pwm duty tc0c value pwm0 output period 5 3th pwm tc0c overflow and tc0irq set old tc0r old tc0r new tc0r new tc0r update new tc0r! old tc0r < tc0c < new tc0r update new tc0r! new tc0r < tc0c < old tc0r tc0c > = tc0r pwm high > low tc0c < tc0r pwm low > high 0xff 0x00 in period 2 and period 4, new duty (tc0r) is set, b ut the pwm output waveform of period 2 and period 4 are wrong. in period 2, the new tc0r value is greater than old tc 0r value. if setting new tc0r is after pwm output ? low?, system is getting tc0c < tc0r result and making pwm output ?h igh?. there are two high level periods in the cycle , and the waveform is unexpected. until next cycle, pwm outpu ts correct duty. in period 4, the new tc0r value is smaller than the old tc0r value. if setting new tc0r is before p wm output ?low?, system is getting tc0c R tc0r result and making pwm output ?low?. in the cycle, the high dut y is shorter than last cycle and longer than correc t cycle. it is an unexpected pwm output. though the wrong waveforms only exist in one cycle, it is still a problem for precise pwm application and might make outside loading operations error. the solution is t o load new tc0r after tc0 timer overflow. using tc0 irq status to determine tc0 timer is overflow or not. when tc0irq becomes ?1?, to set the new tc0r value into tc0r b uffer, and the unexpected pwm output is resolved. example: using tc0 interrupt function to set new tc 0r value for changing pwm duty. main: ? b0mov tc0rbuf, a ; load new pwm duty setting valu e into tc0rbuf. ? ? int_ser: ? ; push routine to save acc and pflag to buffers . ? b0bts1 ftc0irq jmp int_ser90 b0mov a, tc0rbuf ; when tc0 interrupt occurs, upda te tc0r. b0mov tc0r, a ? ? int_ser90: ? ; pop routine to load acc and pflag from buffer s. reti
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 110 version 0.9 8.6 pwm1 mode 8.6.1 overview pwm function is generated by tc1 timer counter and output the pwm signal to pwm1out pin (p5.3). the 8- bit counter counts modulus 256, 64, 32, 16 controlled b y aload1, tc1out bits. the value of the 8-bit count er (tc1c) is compared to the contents of the reference register (tc1r). when the reference register value (tc1r) is equal to the counter value (tc1c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. the low-to-high ratio (duty) of the pwm1 output is tc1r /256, 64, 32, 16. note: tc1c and tc1r can be 0xff in pure pwm output. if pwm function is operating with tc1 interrupt, tc1c and tc1r can?t be set as 0xff and the availabl e range is 0x00~0xfe. aload1 tc1out pwm duty range tc1c valid value tc1r valid bits value max. pwm frequency (fcpu = 4mhz) remark 0 0 0/256~255/256 0x00~0xff 0x00~0xff 7.8125k overflow per 256 count 0 1 0/64~63/64 0x00~0x3f 0x00~0x3f 31.25k overflow per 64 count 1 0 0/32~31/32 0x00~0x1f 0x00~0x1f 62.5k overflow p er 32 count 1 1 0/16~15/16 0x00~0x0f 0x00~0x0f 125k overflow pe r 16 count the output duty of pwm is with different tc1r. duty range is from 0/256~255/256. tc1 clock tc1r=00h tc1r=01h tc1r=80h tc1r=ffh 0 1 128 254 255 ?? ?? 0 1 128 254 255 ?? ?? low low low high high low high
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 111 version 0.9 8.6.2 tc1irq and pwm duty in pwm mode, the frequency of tc1irq is depended on pwm duty range. from following diagram, the tc1irq frequency is related with pwm duty. tc1c value pwm1 output (duty range 0~255) pwm1 output (duty range 0~63) pwm1 output (duty range 0~31) pwm1 output (duty range 0~15) tc1 overflow, tc1irq = 1 0xff 0x00
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 112 version 0.9 8.6.3 pwm program example example: setup pwm1 output from tc1 to pwm1out (p5. 3). the external high-speed oscillator clock is 4mhz. fcpu = fosc/4. the duty of pwm is 30/256. the pwm frequency is about 1khz. the pwm clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 30. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc1c,a b0mov tc1r,a b0bclr ftc1out ; set duty range as 0/256~255/256. b0bclr faload1 b0bset fpwm1out ; enable pwm1 output to p5.3 and d isable p5.3 i/o function b0bset ftc1enb ; enable tc1 timer note: the tc1r is write-only register. don?t proces s them using incms, decms instructions. example: modify tc1r registers? value. mov a, #30h ; input a number using b0mov instructi on. b0mov tc1r, a incms buf0 ; get the new tc1r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc1r, a note: the pwm can work with interrupt request.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 113 version 0.9 8.6.4 pwm1 duty changing notice in pwm mode, the system will compare tc1c and tc1r all the time. when tc1c sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 114 version 0.9 if tc1r is changing in the program processing, the pwm waveform will became as following diagram. 1 1st pwm 2 update pwm duty 3 2nd pwm 4 update pwm duty tc1c value pwm1 output period 5 3th pwm tc1c overflow and tc1irq set old tc1r old tc1r new tc1r new tc1r update new tc1r! old tc1r < tc1c < new tc1r update new tc1r! new tc1r < tc1c < old tc1r tc1c > = tc1r pwm high > low tc1c < tc1r pwm low > high 0xff 0x00 in period 2 and period 4, new duty (tc1r) is set, b ut the pwm output waveform of period 2 and period 4 are wrong. in period 2, the new tc1r value is greater than old tc 1r value. if setting new tc1r is after pwm output ? low?, system is getting tc1c < tc1r result and making pwm output ?h igh?. there are two high level periods in the cycle , and the waveform is unexpected. until next cycle, pwm outpu ts correct duty. in period 4, the new tc1r value is smaller than the old tc1r value. if setting new tc1r is before p wm output ?low?, system is getting tc1c R tc1r result and making pwm output ?low?. in the cycle, the high dut y is shorter than last cycle and longer than correc t cycle. it is an unexpected pwm output. though the wrong waveforms only exist in one cycle, it is still a problem for precise pwm application and might make outside loading operations error. the solution is t o load new tc1r after tc1 timer overflow. using tc1 irq status to determine tc1 timer is overflow or not. when tc1irq becomes ?1?, to set the new tc1r value into tc1r b uffer, and the unexpected pwm output is resolved. example: using tc1 interrupt function to set new tc 1r value for changing pwm duty. main: ? b0mov tc1rbuf, a ; load new pwm duty setting valu e into tc1rbuf. ? ? int_ser: ? ; push routine to save acc and pflag to buffers . ? b0bts1 ftc1irq jmp int_ser90 b0mov a, tc1rbuf ; when tc1 interrupt occurs, upda te tc1r. b0mov tc1r, a ? ? int_ser90: ? ; pop routine to load acc and pflag from buffer s. reti
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 115 version 0.9 9 9 9 serial input/output transceiver (sio) 9.1 overview the sio (serial input/output) transceiver is a seri al communicate interface for data exchanging from o ne mcu to one mcu or other hardware peripherals. it is a simple 8 -bit interface without a major definition of protoc ol, packet or control bits. the sio transceiver includes three pins, cloc k (sck), data input (si) and data output (so) to se nd data between master and slaver terminals. the sio interface buil ds in 8-mode which are the clock idle status, the c lock phases and data fist bit direction. the 8-bit mode supports mo st of sio/spi communicate format. the sio features include the following: full-duplex, 3-wire synchronous data transfer. master (sck is clock output) or slave (sck is clock input) operation. msb/lsb first data transfer. the start phase of data sampling location selection is 1 st -phase or 2 nd -phase controlled register. sck, si, so are programmable open-drain output pin for multiple salve devices application. two programmable bit rates (only in master mode). end-of-transfer interrupt. 9.2 sio operation the siom register can control sio operating functio n, such as: transmit/receive, clock rate, data tran sfer direction, sio clock idle status and clock control phase and start ing this circuit. this sio circuit will transmit or receive 8-bit data automatically by setting senb and start bits in sio m register. the sio data buffer is double buffer de sign. when the sio operating, the siob register stores transfe r data and one internal buffer stores receive data. when sio operation is successfully, the internal buffer relo ads into siob register automatically. the sio 8-bit counter and sior register are designed to generate sio?s clock sourc e with auto-reload function. the 3-bit i/o counter can monitor the operation of sio and announce an interrupt request after transmitting/ receiving 8-bit data. after tra nsferring 8-bit data, this circuit will be disabled automatically and re- transfer data by programming siom register. cpol bi t is designed to control sio clock idle status. cpha bit is designed to control the clock edge direction of data receiv e. cpol and cpha bits decide the sio format. the sio data transfer d irection is controlled by mlsb bit to decide msb fi rst or lsb first. sio interface circuit diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 116 version 0.9 the sio supports 8-mode format controlled by mlsb, cpol and cpha bits. the edge direction is ?data tra nsfer edge?. when setting rising edge, that means to rece ive and transmit one bit data at sck rising edge, a nd data transition is at sck falling edge. when setting fal ling edge, that means to receive and transmit one b it data at sck falling edge, and data transition is at sck rising edge. ?cpha? is the clock phase bit controls the phase of the clock on which data is sampled. when cpha=1, t he sck first edge is for data transition, and receive and transm it data is at sck 2 nd edge. when cpha=0, the 1 st bit is fixed already, and the sck first edge is to receive and transmit d ata. the sio data transfer timing as following fig ure: m l s b c p o l c p h a diagrams description 0 0 1 sck idle status = low. the transfer first bit = msb. sck data transfer edge = falling edge. 0 1 1 sck idle status = high. the transfer first bit = msb. sck data transfer edge = rising edge. 0 0 0 sck idle status = low. the transfer first bit = msb. sck data transfer edge = rising edge. 0 1 0 sck idle status = high. the transfer first bit = msb. sck data transfer edge = falling edge. 1 0 1 sck idle status = low. the transfer first bit = lsb. sck data transfer edge = falling edge. 1 1 1 sck idle status = high. the transfer first bit = lsb. sck data transfer edge = rising edge. 1 0 0 sck idle status = low. the transfer first bit = lsb. sck data transfer edge = rising edge. 1 1 0 sck idle status = high. the transfer first bit = lsb. sck data transfer edge = falling edge. sio data transfer timing
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 117 version 0.9 the sio supports interrupt function. sioien is sio interrupt function control bit. sioien=0, disable s io interrupt function. sioien=1, enable sio interrupt function. when sio interrupt function enable, the program cou nter points to interrupt vector (org 8) to do sio interrupt servic e routine after sio operating. sioirq is sio interr upt request flag, and also to be the sio operating status indicator w hen sioien = 0, but cleared by program. when sio op eration finished, the sioirq would be set to ?1?, and the o peration is the inverse status of sio ?start? contr ol bit. the sioirq and sio start bit indicating the end sta tus of sio operation is after one 8-bit data transf erring. the duration from sio transfer end to sioirq/start acti ve is about ?1/2*sio clock? , means the sio end indicator doesn?t active immediately. note: the first step of sio operation is to setup t he sio pins? mode. enable senb, select cpol and cpha bits. these bits control sio pins? mode. 9.3 siom mode register siom initial value = 0000 0000 0b4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siom senb start srate1 srate0 mlsb sckmd cpol cpha read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 senb: sio function control bit. 0 = disable sio function. p5.0~p5.2 are gpio. 1 = enable sio function. p5.0~p5.2 are sio pins. sio pin structure can be push-pull structure and open-drain structure controlled by p1oc register. bit 6 start: sio progress control bit. 0 = end of transfer. 1 = sio transmitting. bit [5:4] srate1,0: sio?s transfer rate select bit. these 2-bits are workless when sckmd=1. 00 = fcpu. 01 = fcpu/32 10 = fcpu/16 11 = fcpu/8. bit 3 mlsb: msb/lsb transfer first. 0 = msb transmit first. 1 = lsb transmit first. bit 2 sckmd: sio?s clock mode select bit. 0 = internal. (master mode) 1 = external. (slave mode) bit 1 cpol: sck idle status control bit. 0 = sck idle status is low status. 1 = sck idle status is high status. bit 0 cpha: the clock phase bit controls the phase of the cloc k on which data is sampled. 0 = data receive at the first clock phase. 1 = data receive at the second clock phase.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 118 version 0.9 because sio function is shared with port5 for p5.0 as sck, p5.1 as si and p5.2 as so. the following ta ble shows the port5[2:0] i/o mode behavior and setting when sio f unction enable and disable. senb=1 (sio function enable) (sckmd=1) sio source = external clock p5.0 will change to input mode automatically, no ma tter what p5m setting. p5.0/sck (sckmd=0) sio source = internal clock p5.0 will change to output mode automatically, no m atter what p5m setting. p5.1/si p5.1 must be set as input mode in p5m ,or t he sio function will be abnormal p5.2/so sio = transmitter/receiver p5.2 will change to outp ut mode automatically, no matter what p5m setting. senb=0 (sio function disable) p5.0/p5.1/p5.2 port5[2:0] i/o mode are fully controlled by p5m wh en sio function disable note: 1. if sckmd=1 for external clock, the sio is in sla ve mode. if sckmd=0 for internal clock, the sio is in master mode. 2. don?t set senb and start bits in the same time. that makes the sio function error. 3. sio pin can be push-pull structure and open-drai n structure controlled by p1oc register. 9.4 siob data buffer siob initial value = 0000 0000 0b6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siob siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 siob is the sio data buffer register. it stores ser ial i/o transmit and receive data. the system is si ngle-buffered in the transmit direction and double-buffered in the recei ve direction. this means that bytes to be transmitt ed cannot be written to the siob data register before the entire shift cycle is completed. when receiving data, how ever, a received byte must be read from the siob data register befor e the next byte has been completely shifted in. oth erwise, the first byte is lost. following figure shows a typica l sio transfer between two micro-controllers. maste r mcu sends sck for initial the data transfer. both master and slav e mcu must work in the same clock edge direction, a nd then both controllers would send and receive data at the same time. shift register (siob) 2nd receive buffer (address = siob) internal bus read siob write siob sio master (sckmd = 0) so si sck shift register (siob) 2nd receive buffer (address = siob) internal bus read siob write siob sio slave (sckmd = 1) si so sck sio data transfer diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 119 version 0.9 9.5 sior register description sior initial value = 0000 0000 0b5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sior sior7 sior6 sior5 sior4 sior3 sior2 sior1 sior0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the sior is designed for the sio counter to reload the counted value when end of counting. it is like a post-scaler of sio clock source and let sio has more flexible to s etting sck range. users can set the sior value to s etup sio transfer time. to setup sior value equation to desi re transfer time is as following. sck frequency = sio rate / (256 - sior) sior = 256 - ( 1 / ( sck frequency ) * sio rate ) example: setup the sio clock to be 5khz. fosc = 3.5 8mhz. sio?s rate = fcpu = fosc/4. sior = 256 ? (1/(5khz) * 3.58mhz/4) = 256 ? (0.0002*895000) = 256 ? 179 = 77
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 120 version 0.9 1 1 1 0 0 0 main serial port (msp) 10.1 overview the msp (main serial port) is a serial communicatio n interface for data exchanging from one mcu to one mcu or other hardware peripherals. these peripheral device s may be serial eeprom, a/d converters, display dev ice, etc. the msp module can operate in one of two modes master tx,rx mode slave tx,rx mode (with general address call) support single mast, mutiplex slave. the msp features include the following: 2-wire synchronous data transfer / receiver. master (scl is clock output) or slave (sc is clock input) operation. scl, sda are programmable open-drain output pin for multiple salve devices application. support 400k clock rate @ fcpu=4mips. end-of-transfer/reciver interrupt. note. use ice emulation msp function, reference ch1 5.1.1 10.2 msp status register mspstat initial value = x000 00x0 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspstat - cke d_a p s red_wrt - bf read/write - r/w r r r r - r after reset - 0 0 0 0 0 - 0 bit 6 cke: slave clock edge control bit in slave mode: receive address or data byte 0= latch data on scl rising edge. (default) 1= latch data on scl falling edge. note 1. in slave transmit mode, address received de pended on cke sett ing. data transfer on scl falling edge. note 2. in slave receiver mode, address and data re ceived depended on cke setting. bit 5 d_a_: data/address_ bit 0=indicates the last byte received or transmitted w as address. 1= indicates the last byte received or transmitted was data. bit 4 p: stop bit 0 = stop bit was not detected. 1 = indicates that a stop bit has been detected las t. note1. it will be cleared when start bit was detect ed. bit 3 s: start bit. 0 = start bit was not detected. 1 = indicates that a start bit has been detected la st note1. it will be cleared when stop bit was detecte d. bit 2 red_wrt: read/write bit information.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 121 version 0.9 this bit holds the r/w bit information following th e last address match. this bit is only valid from t he address match to the next start bit, stop bit, or not ack b it. in slave mode : 0 = write. 1 = read. in master mode : 0 = transmit is not in progress. 1 = transmit is in progress. or this bit with sen, rsen, pen, rcen, or acken wil l indicate if the msp is in idle mode. bit 0 bf: buffer full status bit receive 1 = receive complete, mspbuf is full. 0 = receive not complete, mspbuf is empty. transmit 1 = data transmit in progress (does not include the ack and stop bits), mspbuf is full. 0 = data transmit complete (does not include the ac k and stop bits), mspbuf is empty. 10.3 msp mode register 1 mspm1 initial value = 0000 00x0 091h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspm1 wcol mspov mspenb ckp slrxckp mspwk - mspc read/write r/w r/w r/w r/w r/w r/w - r/w after reset 0 0 0 0 0 0 - 0 bit 7 wcol: write collision detect bit master mode : 0 = no collision 1 = a write to the sspbuf register was attempted wh ile the msp conditions were not valid for a transmission to be started slave mode : 0 = no collision 1 = the sspbuf register is written while it is stil l transmitting the previous word (must be cleared i n software) bit 6 pmspov: receive overflow indicator bit 0 = no overflow. 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode. sspov must be cleared in software in either mode. (must be cleared in software) bit 5 mspenb: msp communication enable. 0 = disables serial port and configures these pins as i/o port pins 1 = enables serial port and configures scl, sda as the source of the serial port pins note1. after msp disable or enable,must delay 2 ins truction cycle. ex: b0bset fmspenb nop nop .... ex:b0bclr fmspenb nop nop ?. no te2.msp status register will be clear after msp dis able. so,user should setting msp register again befort msp enable. ex:call msp_init_setting b0bset fmspenb nop
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 122 version 0.9 nop bit 4 ckp: scl clock priority control bit in msp slave mode 0 = hold scl keeping low. (ensure data setup time a nd slave device ready.) 1 = release scl clock (slave transistor mode ckp function always enables, slave receiver cpk function control by slrxckp) in msp master mode unused. bit 3 slrxckp: slave receiver mode scl clock priority control bit in msp slave receiver mode. 0 = disable ckp function. 1 = enable ckp function. in msp slave and slave transistor mode unused. bit 2 mspwk: msp wake-up indication bit 0 = mcu not wake-up by msp. 1 = mcu wake-up by msp note1. clear mspwk before entering power down mode for indication the wake- up source from msp or not bit 0 mspc: msp mode control register 0 = msp operated on slave mode, 7-bit address 1 = msp operated on master mode. note1.if msp want to operated on master mode,mspc m ust be setting 1 after mspenb. ex:b0bset mspenb nop nop b0bset fmspc note1.if msp want to operated on slave mode,mspc mu st be setting 1 before mspenb. ex:b0bclr fmspc b0bset mspenb nop nop ?. 10.4 msp mode register 2 mspm2 initial value = 0000 0000 092h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspm2 gcen ackstat ackdt acken rcen pen rsen sen read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 gcen : general call enable bit (in slave mode only) 0 = general call address disabled 1 = enable interrupt when a general call address (0 000h) is received. bit 6 ackstat : acknowledge status bit (in master mode only) in master transmit mode :
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 123 version 0.9 0 = acknowledge was received from slave 1 = acknowledge was not received from slave bit 5 ackdt : acknowledge data bit. (in master mode only) in master receive mode : value that will be transmitted when the user initia tes an acknowledge sequence at the end of a receive . 0 = acknowledge 1 = not acknowledge bit 4 acken : acknowledge sequence enable bit (in msp master m ode only) in master receive mode: 0 = acknowledge sequence idle 1 = initiate acknowledge sequence on sda and scl pi ns, and transmit akdt data bit. automatically cleared by hardware. bit 3 rcen: receive enable bit (in master mode only) 0 = receive idle 1 = enables receive mode for msp bit 2 pen: stop condition enable bit (in master mode only) 0 = stop condition idle 1 = initiate stop condition on sda and scl pins. au tomatically cleared by hardware. bit 1 rsen: repeated start condition enabled bit (in master mo de only) 0 = repeated start condition idle. 1 = initiate repeated start condition on sda and sc l pins. automatically cleared by hardware. bit 0 sen: start condition enabled bit (in master mode only) 0 = start condition idle 1 = initiate start condition on sda and scl pins. a utomatically cleared by hardware. 10.5 msp mspbuf register mspbuf initial value = 0000 0000 093h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspbuf mspbuf7 mspbuf6 mspbuf5 mspbuf4 mspbuf3 mspbuf2 mspbuf1 mspbuf0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 10.6 msp mspadr register mspadr initial value = 0000 0000 094h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mspadr mspadr7 mspadr6 mspadr5 mspadr4 mspadr3 mspadr2 mspadr1 mspadr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:1] 7-bit address. bit 0 tx/rx mode control bit. 0=tx mode. 1=rx mode.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 124 version 0.9 10.7 slave mode operation when an address is matched or data transfer after a nd address match is received, the hardware automati cally will generate the acknowledge (ack_) signal, and load ms pbuf (msp buffer register) with the received data f rom mspsr. there are some condition that will cause msp functi on will not reply ack_ signal: data buffer already full: bf=1 (mspstat bit 0), whe n another transfer was received. data overflow: mspov=1 (mspm1 bit 6), when another transfer was received when bf=1, means mspbuf data is still not read by m cu, so mspsr will not load data into mspbuf, but ms pirq and mspov bit will still set to 1. bf bit will be c lear automatically when reading mspbuf register. ms pov bit must be clear through by sofrware. 10.7.1 addressing when msp slave function has been enabled, it will w ait a start signal occur. following the start signa l, 8-bit address will shift into the mspsr register. the dat a of mspsr[7:1] is compare with mspaddr register on the falling edge of eight scl pulse, if the address are the sam e, the bf and sspov bit are both clear, the followi ng event occur: 1. mspsr register is loaded into mspbuf on the fall ing edge of eight scl pulse. 2. buffer full bit (bf) is set to 1, on the falling edge of eight scl pulse. 3. an ack_ signal is generated. 4. msp interrupt request mspirq is set on the falli ng edge of ninth scl pulse. status when data is received bf mspov mspsp mspbuf reply an ack_ signal set mspirq 0 0 yes yes yes *0 *1 yes no yes 1 0 no no yes 1 1 no no yes data received action table note1. bf=0, mspov=1 shows the software is not set properly to clear overflow register.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 125 version 0.9 10.7.2 slave receiving when the r/w bit of address byte =0 and address is matched, the r/w bit of mspstat is cleared. the add ress will be load into mspbuf. after reply an ack_ signal, msp w ill receive data every 8 clock. the ckp function en able or disable (default) is controlled by slrxckp bit and data latch edge -rising edge (default) or falling e dge is controlled by cpe bit. when overflow occur, no acknowledge signal replied which either bf=1 or mspov=1. msp interrupt is generated in every data transfer. the mspirq bit must be clear by software. following is the slave receiving diagram slrxckp=0 slrxckp=1
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 126 version 0.9 10.7.3 slave transmission after address match, the following r/w bit is set, mspstat bit 2 r/w will be set. the received address will be load to mspbuf and ack_ will be sent at ninth clock then sc l will be hold low. transmission data will be load into mspbuf which also load to mspsr register. the master shoul d monitor scl pin signal. the slave device may hold on the master by keep ckp low. when set. after load mspbuf , set ckp bit, mspbuf data will shift out on the fa lling edge on scl signal. this will ensure the sda signal is v alid on the scl high duty. an msp interrupt is generated on every byte transmi ssion. the mspirq will be set on the ninth clock of scl. clear mspirq by software. mspstat register can monitor th e status of data transmission. in slave transmission mode, an ack_ signal from mas ter-receiver is latched on rising edge of ninth clo ck of scl. if ack_ = high, transmission is complete. slave device will reset logic and waiting another start signal. if ack_= low, slave must load mspbuf which also mspsr, and set ck p=1 to start data transmission again. msp slave transmission timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 127 version 0.9 10.7.4 general call address in msp bus, the first 7-byte is the slave address. only the address match mspaddr the slave will respo nse an ack_. the exception is the general call address which can address all slave devices. when this address occur , all devices should response an acknowledge. the general call address is a special address which is reserved as all ?0? of 7-bytes address. the gen eral call address function is control by gcen bit. set this bit will enable general call address and clear it will disab le. when gecn=1, following a start signal, 8-bit will shift into msp sr and the address is compared with mspadd and also the general call address which fixed by hardware. if the genera call address matches, the mspsr data is transferred into mspbuf, the bf flag bit is set, and in the falling edge of the ninth clock (ack_) mspirq flag set for interrupt request. in the interrupt service routine, reading mspbuf can check if the address is the general call address or device specific. general call address timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 128 version 0.9 10.7.5 slave wake up when mcu enter power down mode, if msbenb bit is st ill set, mcu can wake-up by matched device address. the address of msp bus following start bit, 8-byte address will shift into mspsr, if address matched, an not acknowledge will response on the ninth clock of scl and mcu will be wake-up, mspwkset and start wake-u p procedure but mspirq will not set and mspsr data wi ll not load to mspubf. after mcu finish wake-up pro cedure, msp will be in idle status and waiting master?s sta rt signal. control register bf, mspirq, mspov and m spbuf will be the same status/data before power down. if address not matches, a not acknowledge is still sent on the ninth clock of scl, but mcu will be not wake-up and still keep in power down mode. s receiving address 1 a7 2 a6 3 a5 4 a4 5 a3 6 a2 7 a1 8 9 ack_ p sda scl mspirq bf r/w ? 0 ? ? 0 ? wake-up ? 0 ? mspwk ? 0 ? mcu mode clear mspwk, set fcpum0 (power down) normal mode power down mode msp wake-up timing diagram: address not matched msp wake-up timing diagram: address matched note: 1. msp function only can work on normal mode, when wake- up from power down mode, mcu must operate in normal mode before master sent start sig nal. note:2. in msp wake-up, if the address not match, m cu will keep in power down mode. note 3. clear mspwk before enter power down mode by software for wake-up indication.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 129 version 0.9 10.8 master mode master mode of msp operation from a start signal an d end by stop signal. the start (s) and stop (p) bit are clear when reset or msp function disabled. in master mode the scl and sda line are controlled by msp hardware. following events will set msp interrupt request (ms pirq), if mspien set, interrupt occurs. start condition stop condition data byte transmitted or received acknowledge transmit. repeat start. 10.8.1 mater mode support master mode enable when mspc and mspenb bit set. on ce the master mode enabled, the user had following six options. send a start signal on scl and sda line. send a repeat start signal on scl and sda line. write to mspbuf register for data or address byte transmission send a stop signal on scl and sda line. configuration msp port for receive data send an acknowledge at the end of a received byte of data. 10.8.2 msp rate generator in msp mode, the msp rate generator?s reload value is located in the lower 7 bit of mspaddr register. when mrg is loaded with the register, the mrg count down to 0 a nd stop until another reload has taken place. in ms p mater mode mrg reload from mspaddr automatically. if clock arb itration occur for instance (scl pin keep low by sl ave device), the mrg will reload when scl pin is detected high. scl clock rate = fcpu/(mspaddr)*2 for example, if we want to set 400khz in 4mhz fcpu, the mspaddr have to set 0x05h. mspaddr=4mhz/400khz*2=5 msp rate generator block diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 130 version 0.9 mrg timing diagram with and without clock arbitrati on (mspadrr=0x03) 10.8.3 msp mater start condition to generate a start signal, user sets sen bit (mspm 2.0). when sda and scl pin are both sampled high, m sp rate generator reload mspaddr[6:0], and starts down coun ter. when sda and scl are both sampled high and mrg overflow, sda pin is drive low. when scl sampled hi gh, and sda transmitted from high to low is the sta rt signal and will set s bit (mspstat.3). mrg reload again an d start down counter. sen bit will be clear automat ically when mrg overflow, the mrg is suspend leaving sda line h eld low, and start condition is complete. wcol status flag if user write to mspbuf when start condition proces sing, then wcol is set and the content of mspbuf da ta is un-changed. (the writer doesn?t occur) start condition timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 131 version 0.9 10.8.4 msp master mode repeat start condition when msp logic module is idle and rsen set to 1, re peat start progress occurs. rsen set and scl pin is sampled low, mspaddr[6:0] data reload to msp rate generator and start down counter. the sda pin is release to high in one msp rate generate counter (t mrg ). when the mrg is overflow, if sda is sampled high . scl will be brought high. when scl is sampled high, mspaddr reload to mrg and star t down counter. sda and scl must keep high in one t mrg period. in the next t mrg period, sda will be brought low when scl is sampled high, then rsen will clear automatically by hardware and mrg will not reload, leaving sda pi n held low. once detect sda and scl occur start con dition, the s bit will be set (mspstat.3). mspirq will not set until mrg overflow. note: 1. while any other event is progress, set rse n will take no effect. note:2. a bus collision during the repeat start con dition occur: sda is sampled low when scl goes from low to high wcol status flag if user write to mspbuf when repeat start condition processing, then wcol is set and the content of ms pbuf data is un-changed. (the writer doesn?t occur) repeat start condition timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 132 version 0.9 10.8.5 acknowledge sequence timing an acknowledge sequence is enabled when set acken ( mspm2.4). scl is pulled low when set acken and the content of the acknowledge data bit is present on s da pin. if user whished to reply a acknowledge, ack dt bit should be cleared. if not, set ackdt bit before starting a acknowledge sequence. scl pin will be release (bro ught high) when msp rate generator overflow. msp rate generator sta rt a t mrg period down counter, when scl is sampled high. afte r this period, scl is pulled low, and acken bit is cl ear automatically by hardware. when next mrg overfl ow again, msp goes into idle mode. wcol status flag if user write to mspbuf when acknowledge sequence p rocessing, then wcol bit is set and the content of mspbuf data is un-changed. (the writer doesn?t occur) acknowledge sequence timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 133 version 0.9 10.8.6 stop condition timing at the end of received/transmitted, a stop signal p resent on sda pin by setting the stop bit register, pen (mspm2.1). at the end of receive/transmit, scl goes low on the failing edge of ninth clock. master wil l set sda go low, when set pen bit. when sda is sampled low, msp rate generator is reloaded and start count down to 0. w hen mrg overflow, scl pin is pull high. after one t mrg period, sda goes high. when sda is sampled high whi le scl is high, bit p is set. pen bit is clear after next one t mrg period, and mspirq is set. wcol status flag if user write to mspbuf when a stop condition is pr ocessing, then wcol bit is set and the content of m spbuf data is un-changed. (the writer doesn?t occur) stop condition sequence timing diagram 10.8.7 clock arbitration clock arbitration occurs when the master, during an y receive, transmit or repeat start, stop condition that scl pin allowed to float high. when scl pin is allowed floa t high, the master rate generator (mrg) suspended f rom counting until the scl pin is actually sampled high. when sc l is sampled high, the mrg is reloaded with the con tent of mspaddr[6:0], and start down counter. this ensure t hat scl high time will always be at least one mrg o verflow time in the event that the clock is held low by an exter nal device. clock arbitration sequence timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 134 version 0.9 10.8.8 master mode transmission transmission a data byte, 7-bit address or the eigh t bit data is accomplished by simply write to mspbu f register. this operation will set the buffer full flag bf and allo w msp rate generator start counting. after write to mspbuf, each bit of address will be shifted out on the falling edge of scl until 7-bit address and r/w_ bit are complete. on the failing edge of eighth clo ck, the master will pull low sda fort slave device respond with an acknowledge. on the ninth clock falling edge, sda i s sampled to indicate the address already accept by slave device. the status of the ack bit is load into ackstat stat us bit. then mspirq bit is set, the bf bit is clear and the mrg is hold off until another write to the mspbuf occurs, holding scl low and allow sda floating. bf status flag in transmission mode, the bf bit is set when user w rites to mspbuf and is cleared automatically when a ll 8 bit data are shift out. wcol flag if user write to mspbuf during transmission sequenc e in progress, the wcol bit is set and the content of mspbuf data will unchanged. ackstat status flag in transmission mode, the ackstat bit is cleared wh en the slave has sent an acknowledge (ack_=0), and is set when slave does not acknowledge (ack_=1). a slave s end an acknowledge when it has recognized its addre ss (including general call), or when the slave has pro perly received the data. msp master transmission mode timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 135 version 0.9 10.8.9 master mode receiving master receiving mode is enable by set rcen bit. the mrg start counting and when scl change state fr om low to high, the data is shifted into mspsr. aft er the falling edge of eighth clock, the receive enable bit (rcen) is clear automatically, the contents of msp are lo ad into mspbuf, the bf flag is set, the mspirq flag is set and mrg counter is suspended fro, counting, holding scl low . the msp is now in idle mode and awaiting the next operation co mmand. when the mspbuf data is read by software, th e bf flag is cleat automatically. by setting acken bit, user can send an acknowledge bit at the end of rece iving. bf status flag in reception mode, the bf bit is set when an addres s or data byte is loaded into mspbuf from mspsr. it is cleared automatically when mspbuf is read. mspov flag in receive operation, the mspov bit is set when ano ther 8-bit are received into mspsr, and the bf bit is already set from previous reception wcol flag if user write to mspbuf when a receive is already p rogress, the wcol bit is set and the content of msp buf data will unchanged. msp master receiving mode timing diagram
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 136 version 0.9 1 1 1 1 1 1 8 channel analog to digital converter 11.1 overview this analog to digital converter has 8-input source s with up to 4096-step resolution to transfer analo g signal into 12-bits digital data. the sequence of adc operation is to s elect input source (ain0 ~ ain7) at first, then set gchs and ads bit to ?1? to start conversion. when the conversion is complete, the adc circuit will set eoc bit to ? 1? and final value output in adb register. this adc circuit can select between 8-bit and 12-bit resolution operation by p rogramming adlen bit in adr register. a/d converter (adc) data bus 8/12 ain0/p4.0 ain5/p4.5 ain2/p4.2 ain3/p4.3 ain4/p4.4 ain1/p4.1 ain6/p4.6 ain7/p4.7 a/d converter (adc) data bus 8/12 data bus 8/12 ain0/p4.0 ain0/p4.0 ain5/p4.5 ain5/p4.5 ain2/p4.2 ain2/p4.2 ain3/p4.3 ain3/p4.3 ain4/p4.4 ain4/p4.4 ain1/p4.1 ain1/p4.1 ain6/p4.6 ain6/p4.6 ain7/p4.7 ain7/p4.7 note: for 8-bit resolution the conversion time is 1 2 steps. for 12-bit resolution the conversion time is 16 ste ps note: the analog input level must be between the av refh and avrefl. note: the avrefl connects to vss internally in sn8p 2754, sn8p2755 and sn8p2756. note: the avrefh level must be between the avdd and avrefl + 2.0v. note: the avrefl level must be between the vss and avrefh - 2.0v. note: adc programming notice: 1. set adc input pin i/o direction as input mode 2. disable pull-up resistor of adc input pin 3. disable adc before enter power down (sleep) mode to save power consumption. 4. set related bit of p4con register to avoid extra power consumption in power down mode. 5. delay 100us after enable adc (set adenb = ?1?) t o wait adc circuit ready for conversion. 6. disable adc (set adenb = ?0?) before enter sleep mode to save power consumption.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 137 version 0.9 11.2 adm register 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs - chs2 chs1 chs0 read/write r/w r/w r/w r/w - r/w r/w r/w after reset 0 0 0 0 - 0 0 0 bit 7 adenb: adc control bit. 0 = disable. 1 = enable. bit 6 ads: adc start bit. 0 = stop. 1 = starting. bit 5 eoc: adc status bit. 0 = progressing. 1 = end of converting and reset ads bit. bit 4 gchs: global channel select bit. 0 = disable ain channel. 1 = enable ain channel. bit[2:0] chs[2:0]: adc input channels select bit. 000 = ain0, 001 = ain1, 010 = ain2, 011 = ain3 100 = ain4, 101 = ain5, 110 = ain6, 111 = ain7 note: if adenb = 1, users should set p4.n/ainn as i nput mode without pull-up. system doesn?t set automatically. if p4con.n is set, the p4.n/ainn?s d igital i/o function including pull-up is isolated.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 138 version 0.9 11.3 adr registers 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr adcks2 adcks1 adlen adcks0 adb3 adb2 adb1 adb0 read/write r/w r/w r/w r/w r r r r after reset 0 0 0 0 - - - - bit 7,6,4 adcks [2:0]: adc?s clock source select bit. adcks2 adcks1 adcks0 adc clock source 0 0 0 fcpu/16 0 0 1 fcpu/8 0 1 0 fcpu/1 0 1 1 fcpu/2 1 0 0 fcpu/64 1 0 1 fcpu/32 1 1 0 fcpu/4 1 1 1 reserved bit 5 adlen: adc?s resolution select bits. 0 = 8-bit 1 = 12-bit. bit [3:0] adb [3:0]: adc data buffer. adb11~adb4 bits for 8-bit adc adb11~adb0 bits for 12-bit adc note: adc buffer adr [3:0] initial value after rese t is unknown.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 139 version 0.9 11.4 adb registers 0b2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 read/write r r r r r r r r after reset - - - - - - - - bit[7:0] adb[7:0]: adc high-byte data buffer of 12-bit adc resolution. adb is adc data buffer to store ad converter result . the adb is only 8-bit register including bit 4~bi t11 adc data. to combine adb register and the low-nibble of adr will get full 12-bit adc data buffer. the adc buffer is a read-only register. in 8-bit adc mode, the adc data is stored in adb register. in 12-bit adc mode, the adc data is stored in adb and adr registers. the ain?s input voltage v.s. adb?s output data ain n adb1 1 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 0/4096*vrefh 0 0 0 0 0 0 0 0 0 0 0 0 1/4096*vrefh 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094/4096*vrefh 1 1 1 1 1 1 1 1 1 1 1 0 4095/4096*vrefh 1 1 1 1 1 1 1 1 1 1 1 1 for different applications, users maybe need more t han 8-bit resolution but less than 12-bit adc conve rter. to process the adb and adr data can make the job well. first, the ad resolution must be set 12-bit mode and then to execute adc converter routine. then delete the lsb of adc d ata and get the new resolution result. the table is as following. adb adr adc resolution adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 8-bit o o o o o o o o x x x x 9-bit o o o o o o o o o x x x 10-bit o o o o o o o o o o x x 11-bit o o o o o o o o o o o x 12-bit o o o o o o o o o o o o o = selected, x = delete note: adc buffer adb initial value after reset is u nknown.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 140 version 0.9 11.5 p4con registers the port 4 is shared with adc input function. only one pin of port 4 can be configured as adc input in the same time by adm register. the other pins of port 4 are digit al i/o pins. connect an analog signal to coms digit al input pin, especially the analog signal level is about 1/2 vdd will cause extra current leakage. in the power dow n mode, the above leakage current will be a big problem. unfort unately, if users connect more than one analog inpu t signal to port 4 will encounter above current leakage situation. p4c on is port4 configuration register. write ?1? into p4con [7:0] will configure related port 4 pin as pure analog input p in to avoid current leakage. 0aeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4con p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4 con0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[4:0] p4con[7:0]: p4.n configuration control bits. 0 = p4.n can be an analog input (adc input) or di gital i/o pins. 1 = p4.n is pure analog input, can?t be a digital i/o pin. note: when port 4.n is general i/o port not adc cha nnel, p4con.n must set to ?0? or the port 4.n digit al i/o signal would be isolated. 11.6 adc converting time 12-bit adc conversion time = 1/(adc clock /4)*16 sec 8-bit adc conversion time = 1/(adc clock /4)*12 s ec fcpu = 4mhz ( high clock, fosc is 16mhz and fcpu = fosc/4) adlen adcks2 adcks1 adcks0 adc clock adc conversion time 0 0 0 fcpu/16 1/(4mhz/16/4)*12 = 192 us 0 0 1 fcpu/8 1/(4mhz/8/4)*12 = 96 us 0 1 0 fcpu 1/(4mhz/4)*12 = 12 us 0 (8-bit) 0 1 1 fcpu/2 1/(4mhz/2/4)*12 = 24 us 1 0 0 fcpu/64 1/(4mhz/64/4)*12 = 768 us 1 0 1 fcpu/32 1/(4mhz/32/4)*12 = 384 us 1 1 0 fcpu/4 1/(4mhz/4/4)*12 = 48 us 0 (8-bit) 1 1 1 reserved reserved 0 0 0 fcpu/16 1/(4mhz/16/4)*16 = 256 us 0 0 1 fcpu/8 1/(4mhz/8/4)*16 = 128 us 0 1 0 fcpu 1/(4mhz/4)*16 = 16 us 1 (12-bit) 0 1 1 fcpu/2 1/(4mhz/2/4)*16 = 32 us 1 0 0 fcpu/64 1/(4mhz/64/4)*16 = 1024 us 1 0 1 fcpu/32 1/(4mhz/32/4)*16 = 512 us 1 1 0 fcpu/4 1/(4mhz/4/4)*16 = 64 us 1 (12-bit) 1 1 1 reserved reserved
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 141 version 0.9 11.7 adc routine example example : configure ain0 as 12-bit adc input and st art adc conversion then enter power down mode. adc0: b0bset fadenb ; enable adc circuit call delay100us ; delay 100us to wait adc circuit ready for conversion mov a, #0feh b0mov p4ur, a ; disable p4.0 pull-up resistor b0bclr fp40m ; set p4.0 as input pin mov a, #01h b0mov p4con, a ; set p4.0 as pure analog input mov a, #60h b0mov adr, a ; to set 12-bit adc and adc clock = f osc. mov a,#90h b0mov adm,a ; to enable adc and set ain0 input b0bset fads ; to start conversion wadc0: b0bts1 feoc ; to skip, if end of converting =1 jmp wadc0 ; else, jump to wadc0 b0mov a,adb ; to get ain0 input data bit11 ~ bit4 b0mov adc_buf_hi, a b0mov a,adr ; to get ain0 input data bit3 ~ bit0 and a, 0fh b0mov adc_buf_low, a power_down . . b0bclr fadenb ; disable adc circuit b0bclr fcpum1 b0bset fcpum0 ; enter sleep mode
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 142 version 0.9 11.8 adc circuit mcu vcc gnd v r e f h ainn/p4.n v d d vss 0.1uf analog signal input 47uf 0.1uf adc reference high voltage is from vdd pin. the ver fh should be from mcu?s vdd pin. don?t connect from main power. mcu vcc gnd vrefh ainn/p4.n vdd vss 0.1uf analog signal input 0.1uf 47uf reference high voltage input adc reference high voltage is from external voltage . the capacitor (47uf) between vrefh and vss is nec essary to stable verfh voltage.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 143 version 0.9 1 1 1 2 2 2 digital to analog converter 12.1 overview the d/a converter uses 7-bit structure to synthesiz e 128 steps' analog signal with current source outp ut. after daenb bit is set to ?1?, dac circuit will turn to be enab led and the dam register, from bit0 to bit6, will s end digital signal to ladder resistors in order to generate analog signal on dao pin. ladder resistors dam register dao output ladder resistors dam register dao output the da converter block diagram in order to get a proper linear output, a loading r esistor r l is usually added between dao and ground. the examp le shows the result of vdd = 5v, r l =150ohm and vdd = 3v, r l =150ohm. dao circuit with r l dac output voltage in vdd=5v and 3v note: 1: the d/a converter is not designed for a precise dc voltage output and is suitable for a simple audio application e.g. tone or melody generation. 2:for best linearity performance, the max. loading resistance r l is 150 ohm @5v, 100 ohm @3v 12.2 vdd=3v vdd=5v
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 144 version 0.9 12.3 dam register dam initial value = 0000 0000 0b0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dam daenb dab6 dab5 dab4 dab3 dab2 dab1 dab0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 daenb: digital to analog converter control bit. 0 = disable 1 = enable bit [6:0] dab [6:0]: digital input data. 12.4 d/a converter operation when the daenb = 0, the dao pin is output floating status. after setting daenb to ?1?, the dao output value is controlled by dab bits. example: output 1/2 vdd from dao pin. mov a, #00111111b b0mov dam, a ; set dab to a half of the full scal e. b0bset fdaenb ; enable d/a function. the dab?s data v.s. dao?s output voltage as followi ng: dab6 dab5 dab4 dab3 dab2 dab1 dab0 dao 0 0 0 0 0 0 0 vss 0 0 0 0 0 0 1 idac 0 0 0 0 0 1 0 2 * idac 0 0 0 0 0 1 1 3 * idac . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 0 126 * idac 1 1 1 1 1 1 1 127 * idac note: idac = i fso / (2 7 -1) (i fso : full-scale output current).
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 145 version 0.9 1 1 1 3 3 3 instruction table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bank 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, ?m? only supports 0x80~0x87 registers (e.g. pfl ag,r,y,z?) - - - 1 xch a,m a m - - - 1+n b0xch a,m a m (bank 0) - - - 1+n movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1+n r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1+n t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1+n h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borrow, then c=0, else c=1 1+n t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1+n c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 mul a,m r, a a * m, the lb of product stored in acc and hb stor ed in r register. zf affected by acc. - - 2 and a,m a a and m - - 1 l and m,a m a and m - - 1+n o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1+n c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1+n xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1+n r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1+n c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1+n s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1+n bset m.b m.b 1 - - - 1+n b0bclr m.b m(bank 0).b 0 - - - 1+n b0bset m.b m(bank 0).b 1 - - - 1+n cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1+ s a incms m m m + 1, if m = 0, then skip next instruction - - - 1+n+s n decs m a m - 1, if a = 0, then skip next instruction - - - 1+ s c decms m m m - 1, if m = 0, then skip next instruction - - - 1+n+s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s push to push acc and pflag (except nt0, npd bit ) into buffers. - - - 1 c pop to pop acc and pflag (except nt0, npd bit) fr om buffers. 1 nop no operation - - - 1 note: 1. ?m? is system register or ram. if ?m? is system registers then ?n? = 0, otherwise ?n? = 1. 2. if branch condition is true then ?s = 1?, otherwi se ?s = 0?.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 146 version 0.9 1 1 1 4 4 4 electrical characteristic 14.1 absolute maximum rating (all of the voltages referenced to vss) supply voltage (vdd)??????????????????????????????? ?????? - 0.3v ~ 6.0v input in voltage (vin)????????????????????????????? ??? ..vss - 0.2v ~ vdd + 0.2v operating ambient temperature (topr) sn8p2754k, sn8p2754s, sn8p2755p, sn8p2755s, sn8p27 56p, sn8p2757q SN8P2758p, SN8P2758x?????????????????????????????? 0 c ~ + 70 c storage ambient temperature (tstor) ??????????????? ?????????? .??? ?40 c ~ + 125 c 14.2 standard electrical characteristic (all of voltages referenced to vss, vdd = 5.0v, fos c = 4 mhz,fcpu=1mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit operating voltage vdd normal mode, vpp = vdd 2.4 5. 0 5.5 v ram data retention voltage vdr 1.5 - - v vdd rise rate vpor vdd rise rate to ensure internal power-on reset 0.05 - - v/ms vil1 all input ports vss - 0.3vdd v input low voltage vil2 reset pin vss - 0.2vdd v vih1 all input ports 0.7vdd - vdd v input high voltage vih2 reset pin 0.9vdd - vdd v reset pin leakage current ilekg vin = vdd - - 2 ua vin = vss , vdd = 3v 100 200 300 k i/o port pull-up resistor rup vin = vss , vdd = 5v 50 100 150 k i/o port input leakage current ilekg pull-up resist or disable, vin = vdd - - 2 ua i/o output source current ioh vop = vdd - 0.5v 8 12 - ma sink current iol vop = vss + 0.5v 8 15 - ma intn trigger pulse width tint0 int0 ~ int2 interrup t request pulse width 2/fcpu - - cycle avrefh input voltage varfh vdd = 5.0v varfl+2v - vdd v avrefl input voltage varfl vdd = 5.0v vss - varfh?2v v ain0 ~ ain7 input voltage vani vdd = 5.0v varfl - varfh v vdd= 5v 4mhz - 3 6 ma idd1 normal mode (no loading, fcpu = fosc/4) vdd= 3v 4mhz - 1.5 3 ma vdd= 5v ilrc 32khz - 80 160 ua idd2 slow mode (internal low rc, stop high clock) vdd= 3v ilrc 16khz - 15 30 ua vdd= 5v - 1 2 ua idd3 sleep mode vdd= 3v - 0.5 2 ua vdd= 5v 4mhz - 0.6 1.2 ma vdd= 3v 4mhz - 0.2 0.4 ma vdd= 5v ilrc 32khz - 20 40 ua supply current (adc disable) idd4 green mode (no loading, fcpu = fosc/4, watchdog disable) vdd= 3v ilrc 16khz - 5 10 ua lvd detect voltage vdet low voltage detect level 1. 5 1.8 2.2 v vdd=5.0v 8 14 21 ma dac full-scale output current i fso vdd=3.0v 5 11 18 ma vdd=5.0v - - 150 dac loading resistance r l vdd=3.0v - - 100 dac dnl dac dnl dac differential nonlinearity - 1* - lsb dac inl dac inl dac integral nonlinearity - 3* - lsb vdd=5.0v - 0.6* - ma adc current consumption i adc vdd=3.0v - 0.4* - ma adc enable time tast ready to start convert after s et adenb = ?1? 100 - - us f adclk vdd=5.0v - 8m hz adc clock frequency vdd=3.0v - 5m hz adc conversion cycle time f adcyl vdd=2.4v~5.5v 64 1/f adclk f adsmp vdd=5.0v 125 k/sec adc sampling rate (set fads=1 frequency) vdd=3.0v 80 k/sec
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 147 version 0.9 differential nonlinearity dnl vdd=5.0v , avrefh=3.2 v, f adsmp =7.8k 1 2 16 lsb integral nonlinearity inl vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 2 4 16 lsb no missing code nmc vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 8 10 12 bits *these parameters are for design reference, not tes ted. 1 1 1 5 5 5 application notice 15.1 development tool version 15.1.1 ice (in circuit emulation) sn8ice 2k plus: full function emulates sn8p275x series. use ice emulation msp function: 1. p10 must connect to lcd_cl k, p11 must connect to lcd_sda. 2. p10/p11 is built-in open-drain function. when en able open-drain function, p10/p11 must connect pull -up resistor.
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 148 version 0.9 15.1.2 otp writer mpiii writer: it's convenient to connect full speed usb 1.1 port with pc and then update the writer, connect programming chip or download programming code. 15.1.3 ide (integrated development environment) sonix 8-bit mcu integrated development environment include assembler, ice debugger and otp writer soft ware. for sn8ice 2k plus: m2ide v1.19 or later 15.1.4
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 149 version 0.9 15.2 otp programming pin 15.2.1 the pin assignment of easy writer transition board socket: easy writer jp1/jp2 easy writer jp3 (mapping to 48-pin text tool) vss 2 1 vdd dip1 1 48 dip48 ce 4 3 clk/pgclk dip2 2 47 dip47 oe/shiftdat 6 5 pgm/otpclk dip3 3 46 dip46 d0 8 7 d1 dip4 4 45 dip45 d2 10 9 d3 dip5 5 44 dip44 d4 12 11 d5 dip6 6 43 dip43 d6 14 13 d7 dip7 7 42 dip42 vpp 16 15 vdd dip8 8 41 dip41 rst 18 17 hls dip9 9 40 dip40 alsb/pdb 20 19 - dip10 10 39 dip39 dip11 11 38 dip38 jp1 for mp transition board dip12 12 37 dip38 jp2 for writer v3.0 transition board dip13 13 36 dip36 dip14 14 35 dip35 dip15 15 34 dip34 dip16 16 33 dip33 dip17 17 32 dip32 dip18 18 31 dip31 dip19 19 30 dip30 dip20 20 29 dip29 dip21 21 28 dip28 dip22 22 27 dip27 dip23 23 26 dip26 dip24 24 25 dip25 jp3 for mp transition board 15.2.2 the pin assignment of writer v3.0 and v2.5 t ransition board socket: gnd 2 1 vdd gnd 1 2 vdd ce 4 3 clk ce 3 4 clk oe 6 5 pgm oe 5 6 pgm d0 8 7 d1 d0 7 8 d1 d2 10 9 d3 d2 9 10 d3 d4 12 11 d5 d4 11 12 d5 d6 14 13 d7 d6 13 14 d7 vpp 16 15 vdd vpp 15 16 vdd rst 18 17 hls rst 17 18 hls 20 19 writer v2.5 jp1 pin assignment writer v3.0 jp1 pin assignment
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 150 version 0.9 15.2.3 sn8p275x series programming pin mapping: otp programming pin of sn8p275x series chip name sn8p2754 sn8p2755 SN8P2758 ez writer / writer v3.0 otp ic / jp3 pin assignment number pin number pin number pin number pin 1 vdd 3,14,24 vdd 4,26 vdd 8,16,36,37 vdd 2 gnd 7,21 vss 1,16 vss 5,25 vss 3 clk 20 p5.0 32 p5.0 47 p5.0 4 ce - - - - - - 5 pgm 6 p1.0 14 p1.0 20 p1.0 6 oe 19 p5.1 31 p5.1 46 p5.1 7 d1 - - - - - - 8 d0 - - - - - - 9 d3 - - - - - - 10 d2 - - - - - - 11 d5 - - - - - - 12 d4 - - - - - - 13 d7 - - - - - - 14 d6 - - - - - - 15 vdd 3,14,24 vdd 4,26 vdd 8,16,36,37 vdd 16 vpp 28 rst 8 rst 12 rst 17 hls - - - - - - 18 rst - - - - - - 19 - - - - - - - 20 alsb/pdb 5,22 p1.1/p3.1 13,2 p1.1/p3.1 19,6 p1.1/p3.1
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 151 version 0.9 1 1 1 6 6 6 package information 16.1 sk-dip28 pin symbols min. nor. max. a - - 0.210 a1 0.015 - - a2 0.114 0.130 0.135 d 1.390 1.390 1.400 e 0.310bsc. e1 0.283 0.288 0.293 l 0.115 0.130 0.150 b 0.330 0.350 0.370 0 7 15 unit : inch
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 152 version 0.9 16.2 sop28 pin symbols min. max. a 0.093 0.104 a1 0.004 0.012 d 0.697 0.713 e 0.291 0.299 h 0.394 0.419 l 0.016 0.050 0 8 unit : inch
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 153 version 0.9 16.3 p-dip 32 pin 16.4 sop 32 pin
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 154 version 0.9 16.5 qfn 32 pin min nor max min nor max symbols (inch) (mm) a 0.003 0.030 0.031 0.070 0.750 0.800 a1 0.000 0.001 0.002 0.000 0.020 0.050 a3 0.008 ref. 0.203 ref. b 0.007 0.010 0.012 0.180 0.250 0.300 d 0.20 bsc 5.00 bsc e 0.20 bsc 5.00 bsc e 0.02 bsc 0.50 bsc l 0.014 0.016 0.018 0.350 0.400 0.450 k 0.008 - - 0.20 - - d2 (mm) e2 (mm) pad size min nor max min nor max 114x114 mil 2.60 2.70 2.75 2.60 2.70 2.75 134x134 mil 3.10 3.20 3.25 3.10 3.20 3.25
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 155 version 0.9 16.6 ssop 48 pin min nor max min nor max symbols (inch) (mm) a 0.095 0.102 0.110 2.413 2.591 2.794 a1 0.008 0.012 0.016 0.203 0.305 0.406 a2 0.089 0.094 0.099 2.261 2.388 2.515 b 0.008 0.010 0.030 0.203 0.254 0.762 c - 0.008 - - 0.203 - d 0.620 0.625 0.630 15.748 15.875 16.002 e 0.291 0.295 0.299 7.391 7.493 7.595 [e] - 0.025 - - 0.635 - he 0.396 0.406 0.416 10.058 10.312 10.566 l 0.020 0.030 0.040 0.508 0.762 1.016 l1 - 0.056 - - 1.422 - y - - 0.003 - - 0.076 0 - 8 0 - 8
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 156 version 0.9 16.7 lqfp 48 pin min nor max symbols (mm) a - - 1.6 a1 0.05 - 0.15 a2 1.35 - 1.45 c1 0.09 - 0.16 d 9.00 bsc d1 7.00 bsc e 9.00 bsc e1 7.00 bsc e 0.5 bsc b 0.17 - 0.27 l 0.45 - 0.75 l1 1 ref
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 157 version 0.9 1 1 1 7 7 7 marking definition 17.1 introduction there are many different types in sonix 8-bit mcu p roduction line. this note listed the production def inition of all 8-bit mcu for order or obtain information. this definitio n is only for blank otp mcu. 17.2 marking indetification system sn8 x part no. x x x title sonix 8-bit mcu production rom type p=otp material b = pb-free package g = green package temperature range - = 0 ~ 70 shipping package w = wafer h = dice p = p-dip k = sk-dip s = sop x = ssop q = lqfp/qfp device 2758 2757 2756 2755 2754
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 158 version 0.9 17.3 marking example name rom type device package temperature material SN8P2758xb otp 2758 ssop 0 ~70 pb-free package 17.4 datecode system x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . .
sn8p275x series 8-bit micro-controller build-in 12-bit adc sonix technology co., ltd page 159 version 0.9 sonix reserves the right to make change without fur ther notice to any products herein to improve relia bility, function or design. sonix does not assume any liability arising out of the application or use of any product or ci rcuit described herein; neither does it convey any license under its patent rights nor the rights of others. sonix products ar e not designed, intended, or authorized for us as components in sys tems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any oth er application in which the failure of the sonix pr oduct could create a situation where personal injury or death may occur. should buyer purchase or use sonix products for an y such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employ ees, subsidiaries, affiliates and distributors harmless against all cl aims, cost, damages, and expenses, and reasonable a ttorney fees arising out of, directly or indirectly, any claim of person al injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 10f-1, no. 36, taiyuan stree., chupei city , hsinchu, taiwan r.o.c. tel: 886-3-5600 888 fax: 886-3-5600 889 taipei office: address: 15f-2, no. 171, song ted road, taipei, tai wan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 granville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw

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