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esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 1/43 flash 8 mbit serial flash memory with dual and quad ? features ? single supply voltage 2.7~3.6v ? standard, dual and quad spi ? speed - read max frequency: 33mhz - fast read max frequency: 50mhz / 86mhz / 100mhz - fast read dual/quad max frequency: 50mhz / 86mhz / 100mhz (100mhz / 172mhz / 200mhz equivalent dual spi; 200mhz / 344mhz / 400mhz equivalent quad spi) ? low power consumption - active current: 25 ma (max.) - standby current: 25 a (max.) - deep power down current: 10 a (max.) ? reliability - 100,000 typical program/erase cycles - 20 years data retention ? program - page programming time: 1.5 ms (typical) ? erase - chip erase time 7 sec (typical) - 64k bytes block erase time 0.75 sec (typical) - 32k bytes block erase time 500 ms (typical) - 4k bytes sector erase time 90 ms (typical) ? page programming - 256 byte per programmable page ? lockable 512 bytes otp security sector ? spi serial interface - spi compatible: mode 0 and mode 3 ? end of program or erase detection ? write protect ( wp ) ? hold pin ( hold ) ? all pb-free products are rohs-compliant ? ordering information product id speed package comments f25l08qa ?50pg2s 50mhz f25l08qa ?86pg2s 86mhz f25l08qa ?100pg2s 100mhz 8-lead soic 150 mil pb-free f25l08qa ?50pag2s 50mhz f25l08qa ?86pag2s 86mhz f25l08qa ?100pag2s 100mhz 8-lead soic 200 mil pb-free f25l08qa ?50hg2s 50mhz f25l08qa ?86hg2s 86mhz f25l08qa ?100hg2s 100mhz 8-contact wson 6x5 mm pb-free
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 2/43 ? general description the f25l08qa is a 8megabit, 3v only cmos serial flash memory device. the device supports the standard serial peripheral interface (spi), and a dual/quad spi. esmt?s memory devices reliably store memory data even after 100,000 programming and erase cycles. the memory array can be organized into 4,096 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the page program instruction. the device features sector erase architecture. the memory array is divided into 256 uniform sectors with 4k byte each; 32 uniform blocks with 32k byte each; 16 uni form blocks with 64k byte each. sectors can be erased individually without affecting the data in other sectors. blocks can be erased individually without affecting the data in other blocks. whole chip erase capabilities provide the flexibility to revise the data in the device. the device has sector, block or chip erase but no page erase. the sector protect/unprotect feat ure disables both program and erase operations in any combin ation of the sectors of the memory. ? functional block diagram memory array serial interface ce sck si (sio 0 ) wp (sio 2 ) so (sio 1 ) hold (sio 3 ) command and conrol logic page buffer y-decoder byte address latch / counter status register high voltage generator page address latch / counter
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 3/43 ? pin configurations 8-lead soic (soic 8l, 150mil body, 1.27mm pin pitch) (soic 8l, 208mil body, 1.27mm pin pitch) 1 2 3 4 8 7 6 5 ce so / sio 1 wp / sio 2 v ss v dd hold / sio 3 sck si/sio 0 8- contact wson (wson 8c, 6mmx5mm body, 1.27mm contact pitch) 1 2 3 4 8 7 6 5 ce so wp vss vdd ho ld sck si
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 4/43 ? pin description symbol pin name functions sck serial clock to provide the timing for serial input and output operations si / sio 0 serial data input / serial data input output 0 to transfer commands, addresses or data serially into the device. data is latched on the rising edge of sck (for standard read mode). / bidirectional io pin to transfer commands, addresses or data serially into the device on the rising edge of sck and read data or stat us from the device on the falling edge of sck(for dual/quad mode). so / sio 1 serial data output / serial data input output 1 to transfer data serially out of the devic e. data is shifted out on the falling edge of sck (for standard read mode). / bidirectional io pin to transfer commands, addresses or data serially into the device on the rising edge of sck and read data or status from the device on t he falling edge of sck (for dual/quad mode). ce chip enable to activate the device when ce is low. wp / sio 2 write protect / serial data input output 2 the write protect ( wp ) pin is used to enable/disable bpl bit in the status register. / bidirectional io pin to transfer commands, addresses or data serially into the device on the rising edge of sc k and read data or status from the device on the falling edge of sck (for quad mode). hold / sio 3 hold / serial data input output 3 to temporality stop serial communication with spi flash memory without resetting the device. / bidirectional io pin to transfer commands, addresses or data serially into the device on the rising edge of sck and read data or status from the device on the falling edge of sck (for quad mode). v dd power supply to provide power. v ss ground
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 5/43 ? sector structure table 1: sector address table block address 64kb block 32kb block sector sector size (kbytes) address range a19 a18 a17 a16 255 4kb 0ff000h ? 0fffffh : : : 31 248 4kb 0f8000h ? 0f8fffh 247 4kb 0f7000h ? 0f7fffh : : : 15 30 240 4kb 0f0000h ? 0f0fffh 1 1 1 1 239 4kb 0ef000h ? 0effffh : : : 29 232 4kb 0e8000h ? 0e8fffh 231 4kb 0e7000h ? 0e7fffh : : : 14 28 224 4kb 0e0000h ? 0e0fffh 1 1 1 0 223 4kb 0df000h ? 0dffffh : : : 27 216 4kb 0d8000h ? 0d8fffh 215 4kb 0d7000h ? 0d7fffh : : : 13 26 208 4kb 0d0000h ? 0d0fffh 1 1 0 1 207 4kb 0cf000h ? 0cffffh : : : 25 200 4kb 0c8000h ? 0c8fffh 199 4kb 0c7000h ? 0c7fffh : : : 12 24 192 4kb 0c0000h ? 0c0fffh 1 1 0 0 191 4kb 0bf000h ? 0bffffh : : : 23 184 4kb 0b8000h ? 0b8fffh 183 4kb 0b7000h ? 0b7fffh : : : 11 22 176 4kb 0b0000h ? 0b0fffh 1 0 1 1 175 4kb 0af000h ? 0affffh : : : 21 168 4kb 0a8000h ? 0a8fffh 167 4kb 0a7000h ? 0a7fffh : : : 10 20 160 4kb 0a0000h ? 0a0fffh 1 0 1 0
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 6/43 table 1: sector address table ? continued i block address 64kb block 32kb block sector sector size (kbytes) address range a19 a18 a17 a16 159 4kb 09f000h ? 09ffffh : : : 19 152 4kb 098000h ? 098fffh 151 4kb 097000h ? 097fffh : : : 9 18 144 4kb 090000h ? 090fffh 1 0 0 1 143 4kb 08f000h ? 08ffffh : : : 17 136 4kb 088000h ? 088fffh 135 4kb 087000h ? 087fffh : : : 8 16 128 4kb 080000h ? 080fffh 1 0 0 0 127 4kb 07f000h ? 07ffffh : : : 15 120 4kb 078000h ? 078fffh 119 4kb 077000h ? 077fffh : : : 7 14 112 4kb 070000h ? 070fffh 0 1 1 1 111 4kb 06f000h ? 06ffffh : : : 13 104 4kb 068000h ? 068fffh 103 4kb 067000h ? 067fffh : : : 6 12 96 4kb 060000h ? 060fffh 0 1 1 0 95 4kb 05f000h ? 05ffffh : : : 11 88 4kb 058000h ? 058fffh 87 4kb 057000h ? 057fffh : : : 5 10 80 4kb 050000h ? 050fffh 0 1 0 1 79 4kb 04f000h ? 04ffffh : : : 9 72 4kb 048000h ? 048fffh 71 4kb 047000h ? 047fffh : : : 4 8 64 4kb 040000h ? 040fffh 0 1 0 0
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 7/43 table 1: sector address table ? continued ii block address 64kb block 32kb block sector sector size (kbytes) address range a19 a18 a17 a16 63 4kb 03f000h ? 03ffffh : : : 7 56 4kb 038000h ? 038fffh 55 4kb 037000h ? 037fffh : : : 3 6 48 4kb 030000h ? 030fffh 0 0 1 1 47 4kb 02f000h ? 02ffffh : : : 5 40 4kb 028000h ? 028fffh 39 4kb 027000h ? 027fffh : : : 2 4 32 4kb 020000h ? 020fffh 0 0 1 0 31 4kb 01f000h ? 01ffffh : : : 3 24 4kb 018000h ? 018fffh 23 4kb 017000h ? 017fffh : : : 1 2 16 4kb 010000h ? 010fffh 0 0 0 1 15 4kb 00f000h ? 00ffffh : : : 1 8 4kb 008000h ? 008fffh 7 4kb 007000h ? 007fffh : : : 0 0 0 4kb 000000h ? 000fffh 0 0 0 0
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 8/43 ? status register the software status register prov ides status on whether the flash memory array is available for any read or write operation, whether the device is write enabl ed, and the state of the memory write protection. during an inter nal erase or program operation, the status register may be read only to determine the completion of an operation in progress. tabl e 2 describes the function of each bit in the software status register. table 2: software status register bit name function default at power-up read/write status register -1 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0 r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0 r 2 bp0 indicate current level of block write protection (see table 3) 0 r/w 3 bp1 indicate current level of block write protection (see table 3) 0 r/w 4 bp2 indicate current level of block write protection (see table 3) 0 r/w 5 bp3 indicate current level of block write protection (see table 3) 0 r/w 6 qe 1 = quad enabled 0 = quad disabled 0 r/w 7 bpl 1 = bp3, bp2,bp1,bp0 are read-only bits 0 = bp3, bp2,bp1,bp0 are read/writable 0 r/w bit name function default at power-up read/write status register -2 8 sus suspend status 0 r 9~15 reserved reserved for future use 0 n/a note: 1. busy and wel are read only. 2. bp0~3, qe and bpl bits are non-volatile. write enable latch (wel) the write-enable-latch bit indicate s the status of the internal memory write enable latch. if this bi t is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it indicates the device is not write enabled and does not accept any memory write (program/ erase) commands. th is bit is automatically reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? page program instruction completion ? sector erase instruction completion ? block erase instruction completion ? chip erase instruction completion ? write status register instructions busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indicates the device is busy with an operation in progress. a ?0? indicates the device is ready for t he next valid operation.
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 9/43 table 3: block protection table status register bit protected memory area protection level bp3 bp2 bp1 bp0 64kb block range address range 0 x 0 0 0 none none upper 1/16 0 0 0 1 block 15 0f0000h ? 0fffffh upper 1/8 0 0 1 0 block 14~15 0e0000h ? 0fffffh upper 1/4 0 0 1 1 block 12~15 0c0000h ? 0fffffh upper 1/2 0 1 0 0 block 8~15 080000h ? 0fffffh upper 7/8 0 1 0 1 block 2~15 020000h ? 0fffffh upper 15/16 0 1 1 0 block 1~15 010000h ? 0fffffh bottom 1/16 1 0 0 1 block 0 000000h ? 00ffffh bottom 1/8 1 0 1 0 block 0~1 000000h ? 01ffffh bottom 1/4 1 0 1 1 block 0~3 000000h ? 03ffffh bottom 1/2 1 1 0 0 block 0~7 000000h ? 07ffffh bottom 7/8 1 1 0 1 block 0~13 000000h ? 0dffffh bottom 15/16 1 1 1 0 block 0~14 000000h ? 0effffh all blocks x 1 1 1 block 0~15 000000h ? 0fffffh block protection (bp3, bp2, bp1, bp0) the block-protection (bp3, bp2, bp1, bp0) bits define the memory area, as defined in tabl e 3, to be software protected against any memory write (progr am or erase) operations. the write status register (wrsr) in struction is used to program the bp3, bp2, bp1 and bp0 bits as long as wp is high or the block- protection-look (bpl) bit is 0. chip erase can only be executed if bp3, bp2, bp1 and bp0 bits are all 0. the factory default setting for block protection bit (bp3 ~ bp0) is 0. block protection lock-down (bpl) wp pin driven low (v il ), enables the block-protection- lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp3, bp2, bp1 and bp0 bits. when the wp pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. quad enable (qe) when the quad enable bit is reset to ?0? (factory default), wp and hold pins are enabled. when qe pin is set to ?1?, quad sio 2 and sio 3 are enabled. (the qe should never be set to ?1? during standard and dual spi operation if the wp and hold pins are tied directly to the v dd or v ss .)
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 10/43 ? hold operation hold pin is used to pause a serial sequence underway with the spi flash memory without resetting the clocking sequence. to activate the hold mode, ce must be in active low state. the hold mode begins when the sck active low state coincides with the falling edge of the hold signal. the hold mode ends when the hold signal?s rising edge coincides with the sck active low state. if the falling edge of the hold signal does not coincide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reac hes the active low state. see figure 1 for hold condition waveform. once the device enters hold mode, so will be in high impedance state while si and sck can be v il or v ih . if ce is driven active high during a hold condition, it resets the internal logic of the device. as long as hold signal is low, the memory remains in the hold condition. to resume communication with the device, hold must be driven active high, and ce must be driven active low. see figure 31 for hold timing. the hold function is only available for standard spi and dual spi operation, not during quad spi because this pin is used for sio 3 when the qe bit of status register-1 is set for quad i/o. active hold active hold active hold sck figure 1: hold condition waveform ? write protection the device provides software write protection. the write-protect pin ( wp ) enables or disables the lock-down function of the status register. the block-protection bits (bp3, bp2, bp1, bp0 and bpl) in the stat us register provide write protection to the memory array and the status r egister. when the qe bit of status register-1 is set for quad i/o, the wp pin function is not available since this pin is used for sio 2 . write protect pin ( wp ) the write-protect ( wp ) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp is driven low, the execution of the wr ite status register (w rsr) instruction is determined by the value of the bpl bit (see table 4). when wp is high, the lock-down function of the bpl bit is disabled. table 4: conditions to execute write-status- register (wrsr) instruction wp bpl execute wrsr instruction l 1 not allowed l 0 allowed h x allowed
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 11/43 ? instructions instructions are used to read, write (erase and program), and configure the f25l08qa. the inst ruction bus cycles are 8 bits each for commands (op code), data, and addresses. prior to executing any page program, writ e status register, sector erase, block erase, or chip er ase instructions, the write enable (wren) instruction must be executed first. the complete list of the instructions is provided in table 5. all instructions are synchronized off a high to low transition of ce . inputs will be accepted on the rising edge of sck starting with the most significant bit. ce must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read id, read status register, read electronic signature instructions). any low to high transition on ce , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. instruction commands (op code), addresses, and data are all input from the most signi ficant bit (msb) first. table 5: device operation instruction bus cycle 1~3 1 2 3 4 5 6 n operation max. freq s in s out s in s out s in s out s in s out s in s out s in s out s in s out read 33 mhz 03h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x d out0 x d out1 x cont. fast read 0bh hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x x x d out0 x cont. fast read dual output 12,13 3bh a 23 -a 16 a 15 -a 8 a 7 -a 0 x d out0~1 cont. fast read dual i/o 12, 14 bbh a 23 -a 8 a 7 -a 0, m 7 -m 0 d out0~1 cont. - - fast read quad output 12, 15 6bh a 23 -a 16 a 15 -a 8 a 7 -a 0 x d out0~3 cont. fast read quad i/o 12, 16 ebh a 23 -a 0, m 7 -m 0 x, d out0~1 d out2~6 cont. - - sector erase 4 (4k byte) 20h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - - - - - block erase 5 (32k byte) 52h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - - - - - block erase 5 (64k byte) d8h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - - - - - chip erase 60h / c7h hi-z - - - - - - - - - - - - erase suspend 75h hi-z - - - - - - - - - - - - erase resume 7ah hi-z - - - - - - - - - - - - page program ( pp ) 02h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z d in0 hi-z d in1 hi-z up to 256 bytes hi-z quad page program 17 32h a 23 -a 16 a 15 -a 8 a 7 -a 0 d in0~3 d in4~7 up to 256 byte mode bit reset 6 ffh hi-z ffh hi-z - - - - - - - - - - deep power down ( dp ) b9h hi-z - - - - - - - - - - - - read status register-1 ( rdsr-1 ) 7 05h hi-z x d out (s 7 -s 0 ) - - - - - - - - - - read status register-2 ( rdsr-2 ) 7 35h hi-z x d out (s 15 -s 8 ) - - - - - - - - - - write status register ( wrsr ) 10 01h hi-z d in (s 7 -s 0 ) hi-z - - -. - - - - - - - write enable ( wren ) 10 06h hi-z - - - - - - - - - - - - write disable ( wrdi )/ exit secured otp mode 04h hi-z - - - - - - - - - - - - enter secured otp mode ( enso ) b1h hi-z - - - - -. - - - - - - - release from deep power down ( rdp ) abh hi-z - - - - - - - - - - - - read electronic signature ( res ) 8 abh hi-z x x x x x x x 13h - - - - res in secured otp mode & not lock down abh hi-z x x x x x x x 33h - - - - res in secured otp mode & lock down 50 mhz ~ 100 mhz abh hi-z x x x x x x x 73h - - - -
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 12/43 table 5: device operation instruction - continued bus cycle 1~3 1 2 3 4 5 6 n operation max. freq s in s out s in s out s in s out s in s out s in s out s in s out s in s out jedec read id ( jedec-id ) 9 9fh hi-z x 8ch x 40h x 14h - - - - - - 00h hi-z x 8ch x 13h - - read id ( rdid ) 11 50 mhz ~ 100 mhz 90h hi-z 00h hi-z 00h hi-z 01h hi-z x 13h x 8ch - - notes: 1. operation: s in = serial in, s out = serial out, bus cycle 1 = op code 2. x = dummy input cycles (v il or v ih ); - = non-applicable cycles (cycles are not necessary); cont. = continuous 3. one bus cycle is eight clock periods. 4. 4k byte sector earse addresses: use a ms -a 12 , remaining addresses can be v il or v ih . 5. 32k byte block earse addresses: use a ms -a 15 , remaining addresses can be v il or v ih 64k byte block earse addresses: use a ms -a 16 , remaining addresses can be v il or v ih 6. this instruction is recommended when us ing the dual or quad mode bit feature. 7. the read-status-register is continuo us with ongoing clock cycles until terminated by a low to high transition on ce . 8. the read-electronic-signature is contin uous with on going clock cycles until terminated by a low to high transition on ce . 9. the jedec-read-id is output first byte 8ch as manufacture id; second byte 40h as memory type; third byte 14h as memory capacity. 10. the write-enable (wren) instruction an d the write-status-register (wrsr) instru ction must work in conjunction of each other. the wrsr instruction must be execut ed immediately (very next bus cycle) afte r the wren instruct ion to make both instructions effective. a succe ssful wrsr can reset wren. 11. the manufacture id and device id output will repeat continuously until ce terminates the instruction. 12. dual and quad commands use bidirectional io pins. d out and cont. are serial data out; others are serial data in. 13. dual output data: io 0 =(d 6 ,d 4 ,d 2 ,d 0 ), (d 6 ,d 4 ,d 2 ,d 0 ) io 1 =(d 7 ,d 5 ,d 3 ,d 1 ), (d 7 ,d 5 ,d 3 ,d 1 ) d out0 d out1 14. m 7 -m 0 : mode bits. dual input address: io 0 =(a 22 ,a 20 ,a 18 ,a 16 ,a 14 ,a 12 ,a 10 ,a 8 )(a 6 ,a 4 ,a 2 ,a 0 ,m 6 ,m 4 ,m 2 ,m 0 ) io 1 =(a 23 ,a 21 ,a 19 ,a 17 ,a 15 ,a 13 ,a 11 ,a 9 )(a 7 ,a 5 ,a 3 ,a 1 ,m 7 ,m 5 ,m 3 ,m 1 ) bus c y cle-2 bus c y cle-3 15. quad output data: io 0 =(d 4 ,d 0 ), (d 4 ,d 0 ), (d 4 ,d 0 ), (d 4 ,d 0 ) io 1 =(d 5 ,d 1 ), (d 5 ,d 1 ), (d 5 ,d 1 ), (d 5 ,d 1 ) io 2 =(d 6 ,d 2 ), (d 6 ,d 2 ), (d 6 ,d 2 ), (d 6 ,d 2 ) io 3 =(d 7 ,d 3 ), (d 7 ,d 3 ), (d 7 ,d 3 ), (d 7 ,d 3 ) d out0 d out1 d out2 d out3
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 13/43 16. m 7 -m 0 : mode bits. quad input address: io 0 =(a 20 ,a 16 ,a 12 ,a 8 ,a 4 ,a 0 ,m 4 ,m 0 ) io 1 =(a 21 ,a 17 ,a 13 ,a 9 ,a 5 ,a 1 ,m 5 ,m 1 ) io 2 =(a 22 ,a 18 ,a 14 ,a 10 ,a 6 ,a 2 ,m 6 ,m 2 ) io 3 =(a 23 ,a 19 ,a 15 ,a 11 ,a 7 ,a 3 ,m 7 ,m 3 ) bus c y cle-2 fast read quad i/o data: bus cycle-3 io 0 = (x, x), (x, x), (d 4 ,d 0 ), (d 4 ,d 0 )(d 4 ,d 0 ), (d 4 ,d 0 ), (d 4 ,d 0 ), (d 4 ,d 0 ) io 1 = (x, x), (x, x), (d 5 ,d 1 ), (d 5 ,d 1 )(d 5 ,d 1 ), (d 5 ,d 1 ), (d 5 ,d 1 ), (d 5 ,d 1 ) io 2 = (x, x), (x, x), (d 6 ,d 2 ), (d 6 ,d 2 )(d 6 ,d 2 ), (d 6 ,d 2 ), (d 6 ,d 2 ), (d 6 ,d 2 ) io 3 = (x, x), (x, x), (d 7 ,d 3 ), (d 7 ,d 3 )(d 7 ,d 3 ), (d 7 ,d 3 ), (d 7 ,d 3 ), (d 7 ,d 3 ) d out0 d out1 d out2 d out3 d out4 d out5 bus c y cle-4 17. the instruction is initiated by executing comm and code, followed by address bits into si (sio 0 ) before d in , and then input data to bidirectional io pins (sio 0 ~ sio 3 ). quad input data: io 0 =(d 4 ,d 0 ), (d 4 ,d 0 ), (d 4 ,d 0 ), (d 4 ,d 0 ) io 1 =(d 5 ,d 1 ), (d 5 ,d 1 ), (d 5 ,d 1 ), (d 5 ,d 1 ) io 2 =(d 6 ,d 2 ), (d 6 ,d 2 ), (d 6 ,d 2 ), (d 6 ,d 2 ) io 3 =(d 7 ,d 3 ), (d 7 ,d 3 ), (d 7 ,d 3 ), (d 7 ,d 3 ) d in0 d in1 d in2 d in3
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 14/43 ce sck si 0 1 2 3 4 5 6 7 8 1516 2324 3132 39 40 4748 55 56 6 3 64 80 n+ 4 d ou t n+ 3 d ou t n+2 d out n+1 d out n d ou t msb msb msb high impenance so 0b add. add. a dd . mod e3 mode0 71 72 x no te : x = dummy byte : 8 clocks input dummy (v il or v ih ) read (33mhz) the read instruction supports up to 33 mhz, it outputs the data starting from the specified a ddress location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce . the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address spac e, i.e. for 8mbit density, once the data from address location 0fffffh had been read, the next output will be from address location 000000h. the read instruction is initiat ed by executing an 8-bit command, 03h, followed by address bits [a 23 -a 0 ]. ce must remain active low for the duration of the read cycle. see figure 2 for the read sequence. figure 2: read sequence fast read (50 mhz ~ 100 mhz) the fast read instruction suppor ting up to 100 mhz is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce must remain active low for the duration of the fast read cycle. see figure 3 for the fast read sequence. following a dummy byte (8 clo cks input dummy cycle), the fast read instruction outputs the dat a starting from the specified address location. the data output st ream is continuous through all addresses until terminated by a low to high transition on ce . the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 8mbit density, once t he data from address location 0fffffh has been read, the next output will be from address location 000000h. figure 3: fast read sequence ce sck si 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 6 3 64 70 n+ 4 d ou t n+ 3 d ou t n+2 d out n+1 d out n d ou t msb msb msb high impendance so 03 add. add. a dd . mod e3 mode0
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 15/43 fast read dual output (50 mhz ~ 100 mhz) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruct ion except the data is output on bidirectional i/o pins (sio 0 and sio 1 ). this allows data to be transferred from the device at tw ice the rate of standard spi devices. this instruction is for quickly downloading code from flash to ram upon power-up or for applications that cache code- segments to ram for execution. the fast read dual output instru ction is initiated by executing an 8-bit command, 3bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce must remain active low for the duration of the fast read dual output cycle. see figure 4 for the fast read dual output sequence. figure 4: fast read dual output sequence ce sck sio 0 012345678 1516 2324 3132 3940 4344 47 48 51 52 n+4 d out n+3 d ou t n+ 2 d ou t n+ 1 d out n d out msb msb high impenance sio 1 3b add. add. add. mode3 mode0 55 56 6420 75 3 1 6420 75 3 1 6420 75 3 1 6420 75 3 1 75 64 dum my note: the input data durin g the dummy clocks is ?don?t care?. howev er , the io 0 pin should be high-impefance piror to th e falling edge of the first data clock. io 0 switches from in put to ouput
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 16/43 fast read dual i/o (50 mhz ~ 100 mhz) the fast read dual i/o (bbh) instru ction is similar to the fast read dual output (3bh) instruct ion, but with the capability to input address bits [a 23 -a 0 ] two bits per clock. to set mode bits [m 7 -m 0 ] after the address bits [a 23 -a 0 ] can further reduce instruction overhead (see figure 5). the upper mode bits [m 7 ?m 4 ] controls the length of next fast read dual i/o instruction with/without the first byte command code (bbh). the lower mode bits [m 3 ?m 0 ] are ?don?t care?. if [m 7 ?m 0 ] = ?axh?, the next fast re ad dual i/o instruction (after ce is raised and the lowered) doesn?t need the command code (see figure 6). this way let the instruction sequence reduce 8 clocks and allows to enter address immediately after ce is asserted low. if [m 7 ?m 0 ] are the value other than ?axh?, the next instruction need the first byte command code, thus returning to normal operation. a mode bit reset (ffh) also can be used to reset mode bits [m 7 ?m 0 ] before issuing normal instructions. figure 5: fast read dual i/o sequence ([m 7 -m 0 ] = 0xh or not axh) figure 6: fast read dual i/o sequence ([m 7 -m 0 ] = axh) ce sck sio 0 n+ 4 d out n+ 3 d out n+2 d out n+1 d ou t n d out msb hig h impenance sio 1 bb mode3 mode0 6420 75 3 1 6420 75 3 1 6420 75 3 1 6420 75 3 1 75 64 io 0 switches from input to ouput 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 64 2 0 7531 0 1 2 3 4 5 6 7 8 9 10 11 1 2 1 3 1 4 15 16 1 7 1 8 19 2 0 21 2 2 23 24 27 28 31 32 35 3 6 39 4 0 a 23-16 a 15-8 a 7- 0 64 75 m 7-0 note: the mode bits [m3 -m0] are ?d on?t care?. however , the io pins sh ould be high-impefance p iror to the falling edge of the first data clock. ce sck sio 0 n+4 d out n+3 d out n+ 2 d ou t n+1 d out n d out sio 1 mode3 mode0 6420 75 3 1 6420 75 3 1 6420 75 3 1 6420 75 3 1 75 64 io 0 switches from in put to ouput 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 64 2 0 7531 a 23-16 a 15 - 8 a 7-0 64 75 m 7-0 note: the mode bits [m3 -m0] are ?don?t care?. however , the io pins sh ould be high-impe fance piror to the fa ll ing edge of the fi rst data clock. 0 1 2 3 4 5 6 7 8 9 10 11 121314 15 16 1920 2324 2728 3132
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 17/43 fast read quad output (50 mhz ~ 100 mhz) the fast read quad output (6b) in struction is similar to the fast read dual output (3bh) instruct ion except the data is output on bidirectional i/o pins (sio 0 , sio 1 , sio 2 and sio 3 ). a quad enable (qe) bit of status regist er-1 must be set ?1? to enable quad function. this allows data to be transferred from the device at four times the rate of standard spi devices. the fast read quad output instruct ion is initiated by executing an 8-bit command, 6bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce must remain active low for the duration of the fast read dual output cycle. see figure 7 for the fast read quad output sequence. figure 7: fast read quad output sequence high impenance sio 1 51 5 1 51 5 1 51 ce sck sio 0 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 43 44 45 46 47 48 n+4 d out n+3 d ou t n+2 d out n+1 d out n d ou t msb msb 6b add. add. a dd. mod e3 mode0 40 4 0 40 4 0 40 dum my note: the input data du ring the dummy clocks is ?don?t care?. however , the io pins should be high-impefance piror to the fal ling edge o f the first data clock. io 0 switches from input to ouput high impenance sio 2 62 high impenance sio 3 73 4142
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 18/43 fast read quad i/o (50 mhz ~ 100 mhz) the fast read quad i/o (ebh) inst ruction is similar to the fast read quad output (6bh) instructi on, but with the capability to input address bits [a 23 -a 0 ] four bits per clock. a quad enable (qe) bit of status register-1 must be set ?1? to enable quad function. to set mode bits [m 7 -m 0 ] after the address bits [a 23 -a 0 ] can further reduce instruction overhead (see figure 8). the upper mode bits [m 7 ?m 4 ] controls the length of next fast read quad i/o instruction with/without the first byte command code (ebh). the lower mode bits [m 3 ?m 0 ] are ?don?t care?. if [m 7 ?m 0 ] = ?axh?, the next fast re ad quad i/o inst ruction (after ce is raised and the lowered) doesn?t need the command code (see figure 9). this way let the instruction sequence reduce 8 clocks and allows to enter address immediately after ce is asserted low. if [m 7 ?m 0 ] are the value other than ?axh?, the next instruction need the first byte command code, thus returning to normal operation. a mode bit reset (ffh) also can be used to reset mode bits [m 7 ?m 0 ] before issuing normal instructions. figure 8: fast read quad i/o sequence ([m 7 -m 0 ] = 0xh or not axh) figure 9: fast read quad i/o sequence ([m 7 -m 0 ] = axh) high impenance sio 1 51 51 51 21 17 13 9 51 51 ce sck sio 0 msb eb mode3 mode0 40 4 0 40 io 0 switches from input to ouput 20 16 12 8 404 0 0 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 14 15 1 6 1 7 18 19 20 21 2 2 23 24 25 note: the mode bits [m3 -m0] are ?don?t care?. how eve r , the io p ins sh ould be hi g h-im p efance p i r o r to the f all in g ed g eofthefi r st data clock. hi gh imp enan ce sio 2 62 62 62 22 18 14 10 62 62 n+2 d out n+1 d out n d out hi gh imp enan ce sio 3 7373 73 23 19 15 11 7373 a 23 - 0 m 7-0 dummy sio 1 51 51 51 21 1 7 13 9 51 51 ce sck sio 0 mod e3 mode0 40 4 0 40 io 0 switches from input to oup ut 20 16 12 8 404 0 0 1 2 3 4 5 6 7 8 9 1 0 11 12 13 1 4 15 16 note: the mode bits [m3 -m0] are ?don?t care?. how eve r , the io p ins sh ould be hi g h-im p efance p i r o r to the fallin g ed g eofthefi r st data clock. sio 2 62 62 62 22 18 14 10 62 62 n+2 d ou t n+1 d out n d out sio 3 7373 73 23 19 15 11 7373 a 23-0 m 7-0 dum my
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 19/43 page program (pp) the page program instruction allows many bytes to be programmed in the memory. the bytes must be in the erased state (ffh) when initiating a program operation. a page program instruction applied to a protected memory area will be ignored. prior to any write operation, the write enable (wren) instruction must be executed. ce must remain active low for the duration of the page program instruction. the page program instruction is initiated by executing an 8-bit command, 02h, followed by address bits [a 23 -a 0 ]. following the address, at least one byte data is input (the maximum of input data can be up to 256 bytes). if the 8 least significant address bits [a 7 -a 0 ] are not all zero, all transmitted data that goes beyo nd the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [a 7 -a 0 ] are all zero). if more than 256 bytes data are s ent to the device, previously latched data are discarded and the last 256 bytes data are guaranteed to be programmed correctly within the same page. if less than 256 bytes data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. ce must be driven high before t he instruction is executed. the user may poll the busy bit in the so ftware status register or wait t pp for the completion of the internal self-timed page program operation. while the page program cy cle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept ot her instructions again. after the page program cycle has finished, the write-enable-latch (wel) bit in the status register-1 is cleared to 0. see figure 10 for the page program sequence. figure 10: page program sequence
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 20/43 quad page program the quad page program instruction allows many bytes to be programmed in the memory by using four i/o pins (sio 0 , sio 1 , sio 2 and sio 3 ). the instruction can improve programmer performance and the effectiveness of application that have slow clock speed <20mhz. for system with faster clock, this instruction can?t provide more ac tual favors, because the required internal page program time is far more than the time data flows in. therefore, we suggest that user can execute this command while the clock speed <20mhz. prior to quad page program operat ion, the write enable (wren) instruction must be executed and qu ad enable (qe) bit of status register must be set ?1?. the other function descriptions are as same as standard page program. see figure 11 for the quad page program sequence. figure 11: quad page program sequence sio 1 51 5 1 51 5 1 51 ce sck sio 0 012345678 1516 2324 31323334 d in3 d in2 d in 1 d in 0 msb msb 32 add. add. add. mod e3 mode0 40 4 0 40 4 0 40 sio 2 62 sio 3 73 35 36 37 3839 d in255 ss ss ss ss ss
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 21/43 mode bit reset mode bits [m 7 ?m 0 ] are issued to further reduce instruction overhead for fast read dual/quad i/o operation. if [m 7 ?m 0 ] = ?axh?, the next fast read d ual/quad i/o instruction doesn?t need the command code. if the system controller is rese t during operation, it will send a standard instruction (such as read id) to the flash memory. however, the device doesn?t have a hardware reset pin, so if [m 7 ?m 0 ] = ?axh?, the device will not recognize any standard spi instruction. after a system rese t, it is recommended to issue a mode bit reset instruction first to release the status of [m 7 ?m 0 ] = ?axh? and allow the device to recogn ize standard spi instruction. see figure 12 for the mode bit reset instruction. figure 12: mode bit reset instruction sck 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode3 mode0 sio 0 ff ff ce sio 1 note: to reset mode bits dur ing quad i/o operation, only eight cl ocks are needed. the command code is ?ffh?. to reset mode bits durin g dua l i/o operation, sixteen clocks are needed to shift in command code ?ffffh?. sio 2 sio 3 mode bit reset for dual i/o mode bit reset for quad i/o
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 22/43 64k byte block erase the 64k-byte block erase instruction clears all bits in the selected block to ffh. a block erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write enable (w ren) instruction must be executed. ce must remain active low for the duration of the any command sequence. the block erase instruction is initiated by executing an 8-bit command, d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 16 ] (a ms = most significant address) are used to determine the block address (ba x ), remaining address bits can be v il or v ih . ce must be driven high before the instruction is executed. the us er may poll the busy bit in the software status register or wait t be for the completion of the internal self-timed block erase cycle. see figure 13 for 64k byte block erase sequence. ce sck si msb high impenance so d8 mode3 mode0 012345678 15 16 23 24 31 add. msb add. add. figure 13: 64k-byte block erase sequence 32k byte block erase the 32k-byte block erase instruction clears all bits in the selected block to ffh. a block erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write enable (w ren) instruction must be executed. ce must remain active low for the duration of the any command sequence. the block erase instruction is initiated by executing an 8-bit command, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] (a ms = most significant address) are used to determine the block address (ba x ), remaining address bits can be v il or v ih . ce must be driven high before the instruction is executed. the us er may poll the busy bit in the software status register or wait t be for the completion of the internal self-timed block erase cycle. see figure 14 for 32k byte block erase sequence. ce sck si msb high impenance so 52 mode3 mode0 012345678 15 16 23 24 31 add. msb add. add. figure 14: 32k-byte block erase sequence
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 23/43 4k byte sector erase the sector erase instruction clears all bits in the selected sector to ffh. a sector erase instructi on applied to a protected memory area will be ignored. prior to an y write operation, the write enable (wren) instruction must be executed. ce must remain active low for the duration of the any command sequence. the sector erase instruction is in itiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih . ce must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t se for the completion of the internal self-timed sector erase cycle. see figure 15 for the sector erase sequence. ce sck si msb high impenance so 20 mode3 mode0 012345678 15 16 23 24 31 add. msb add. add. figure 15: 4k-byte sector erase sequence chip erase the chip erase instruction clears all bits in the device to ffh. a chip erase instruction will be ignored if any of the memory area is protected. prior to any write oper ation, the write enable (wren) instruction must be executed. ce must remain active low for the duration of the chip erase instruction sequence. the chip erase instruction is initiated by executing an 8-bit command, 60h or c7h. ce must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the internal self-timed chip erase cycle. see figure 16 for the chip erase sequence. figure 16: chip erase sequence ce sck si 01234567 msb hi gh impenan ce so 60 or c7 mod e3 mode0
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 24/43 erase suspend the erase suspend instruction allo ws the system to interrupt a sector or block erase operati on and then read from any other sector or block. the write status register instruction and sector / block erase instructions are not allowed during suspend. erase suspend is valid only during the sector or block erase operation. if written during the chip erase or program operat ion, the erase suspend instruction is ignored. a maximum of t sus is required to suspend the erase operation. the busy bit in the software status register will clear to ?0? after erase suspend. a power-off during the suspend period will reset the device and release the suspend status. figure 17: erase suspend instruction erase resume the erase resume instruction mu st be written to resume the sector or block erase operation after erase suspend. after issued the busy bit in the software status register will be set to ?1? and the sector or block will complete the erase operation. erase resume instruction will be ignored unless an erase suspend operation is active. figure 18: erase resume instruction sck 01234567 mod e3 mode0 si ce t sus msb 75 accept r ead o r p r o g r am inst r ucti on so high impedance sck 01234567 mod e3 mode0 si ce msb 7a r esume secto r o r bl ock e r ase
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 25/43 write enable (wren) the write enable (wren) instru ction sets the write-enable- latch bit in the software status register to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (program/erase) operation. ce must be driven high before the wren instruction is executed. figure 19: write enable (wren) sequence write disable (wrdi) the write disable (wrdi) instruct ion resets the write-enable- latch bit to 0 disabling any new write operations from occurring or exits from otp mode to normal mode. ce must be driven high before the wrdi instruction is executed. figure 20: write disable (wrdi) sequence ce sck si 01234567 msb hi gh im penan ce so 06 mod e3 mode0 ce sck si 01234567 msb hi gh im penan ce so 04 mod e3 mode0
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 26/43 write status register (wrsr) the write status register instru ction writes new values to the bp3, bp2, bp1, bp0, qe and bpl (sta tus register-1) bits of the status register. ce must be driven low before the command sequence of the wrsr instruct ion is entered and driven high before the wrsr instru ction is executed. ce must be driven high after the eighth bit of data that is clocked in. if it is not done, the wrsr instruction will not be issued. see figure 21 for wren and wrsr instruction sequences. executing the write st atus register instruction will be ignored when wp is low and bpl bit is set to ?1?. when the wp is low, the bpl bit can only be set from ?0? to ?1? to lock down the status register, but cannot be reset from ?1? to ?0?. when wp is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, bp1, bp2 and bp3 bits in the status register can all be changed. as long as bpl bit is set to 0 or wp pin is driven high (v ih ) prior to the low-to-high transition of the ce pin at the end of the wrsr inst ruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0; bp1, bp2 and bp3 bits at the same time. see table 4 for a summary description of wp and bpl functions. figure 21: write enable (wren) and write status register (wrsr) read status register (rdsr) the read status register (rdsr) instruction allows reading of the status register. t he status register may be read at any time even during a write (program/era se) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce must be driven low before the rdsr instruction is entered and remain low until the stat us data is read. the rdsr-1 instruction code is ?05h? for status register-1. the rdsr-2 instruction code is ?35h? for status register-2. read status register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the ce . see figure 22 for the rdsr instruction sequence. figure 22: read status register (rdsr-1 or rdsr-2) sequence sck 01234567891011121314 mod e3 mode0 si ce msb 05 or 35 so msb high impedance bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 status r e g iste r -1 o r -2 data out ce sck si 01234567 msb msb high impenance so 06 mode3 mode0 76 5 4 32 1 0 01 0123456789 10 11 12 13 14 15 stauts register-1 da ta in
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 27/43 enter otp mode (enso) the enso (b1h) instruction is for entering the additional 512 bytes secured otp mode. the additional 512 bytes secured otp sector is independent from main array, which may use to store unique serial number for system i dentifier. user must unprotect whole array (bp0=bp1=bp2=bp3 =0), prior to any program operation in otp sector. after entering the secured otp mode, only the secured otp sector can be accessed and user can only follow the read or program procedure with otp address range (address bits [a 23 ?a 9 ] must be ?0?). the secured otp data cannot be updated again once it is lock down or has been programmed. in secured ot p mode, wrsr command will ignore the input data and lock down the secured otp sector (otp_lock bit =1). to exit secured otp mode, user must execute wrdi command. res can be used to verify the secured otp status as shown in table 6. figure 23: enter otp mode (enso) sequence otp sector address size address range 512 bytes 000000h ~ 0001ffh note: the otp sector is an independent sector.
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 28/43 deep power down (dp) the deep power down instruction is for minimizing power consumption (the standby current is reduced from i sb1 to i sb2 .). this instruction is initiated by executing an 8-bit command, b9h, and then ce must be driven high. after ce is driven high, the device will enter to deep power down within the duration of t dp . once the device is in deep power do wn status, all instructions will be ignored except the release from deep power down instruction (rdp) and read elec tronic signature instruction (res). the device always power-up in the normal operation with the standby current (i sb1 ). see figure 24 for the deep power down instruction. figure 24: deep power down instruction release from deep power down (rdp) and read electronic-signature (res) the release form deep power down and read electronic-signature instruction is a multi-purpose instruction. the instruction can be used to re lease the device from the deep power down status. this instruction is initiated by driving ce low and executing an 8-bit command, abh, and then drive ce high. see figure 25 for rdp inst ruction. release from the deep power down will take the duration of t res1 before the device will resume normal operation and other instructions are accepted. ce must remain high during t res1 . the instruction also can be used to read the 8-bit electronic- signature of the device on the so pi n. it is initiated by driving ce low and executing an 8-bit command, abh, followed by 3 dummy bytes. the electronic-signat ure byte is then output from the device. the electronic-signat ure can be read continuously until ce go high. see figure 26 for res sequence. after driving ce high, it must remain high during for the duration of t res2 , and then the device will resume normal operation and other instructions are accepted. the instruction is executed while an erase, program or wrsr cycle is in progress is ignored and has no effect on the cycle in progress. in otp mode, user al so can execute res to confirm the status of otp. sck 01234567 mod e3 mode0 si ce standard current t dp msb b9 deep power down current (i sb 2 )
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 29/43 figure 25: release from deep power down (rdp) instruction figure 26: read electronic -signature (res) sequence table 6: electronic signature data command mode electronic signature data normal 13h in secured otp mode & non lock down (otp_lock =0) 33h res in secured otp mode & lock down (otp_lock =1) 73h sck 01234567 mod e3 mode0 si ce standby current t res1 msb ab deep power down current ( i sb 2 ) so high impedance sck 0123456789 mod e3 mode0 si ce standby current t res2 msb ab deep power down current ( i sb2 ) so high impedance ss 30 31 32 3 3 34 35 36 37 38 ss electronic-signature data out ss msb 3dummybytes
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 30/43 jedec read-id the jedec read-id instructi on identifies the device as f25l08qa and the manufactur er as esmt. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturer?s id, 8ch, is output from the device. after that, a 16-bit device id is shifted out on the so pin. byte1, 8ch, identifies the manufacturer as esmt. byte2, 40h, identifies the memory type as spi flash. byte3, 14h, identifies the device as f25l08qa. the instruction sequence is shown in figure 27. the jedec read id instruction is terminated by a low to high transition on ce at any time during data output. if no other command is issued after executing the jedec read-id instruction, issue a 00h (nop) command before going into standby mode ( ce =v ih ). figure 27: jedec read-id sequence table 7: jedec read-id data device id manufacturer?s id (byte 1) memory type (byte 2) memory capacity (byte 3) 8ch 40h 14h ce sck si msb high impenance so 9f mode3 mode0 01 23 45 67 89 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031 8c msb 40 14 msb msb
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 31/43 read-id (rdid) the read-id instruction (rdid) identifies the devices as f25l08qa and manufacturer as esmt. this command is backward compatible to all esmt spi devices and should be used as default device identification when multiple versions of esmt spi devices are used in one design. the device information can be read from executing an 8-bit command, 90h, followed by address bits [a 23 -a 0 ]. following the read-id instruction, the manufacturer?s id is located in address 000000h and the device id is located in address 000001h. once the device is in read-id mode, the manufacturer?s and device id output data toggles between address 000000h and 000001h until terminated by a low to high transition on ce . figure 28: read id sequence table 8: product id data address byte1 byte2 8ch 13h 000000h manufacturer?s id device id esmt f25l08qa 13h 8ch 000001h device id esmt f25l08qa manufacturer?s id ce sck si 012345678 15 16 23 24 31 32 39 40 47 4 8 55 56 63 msb msb high impenance so 90 0 0 00 add 1 mode3 mode0 note: the manufacture?s an d device id o utput stream i s continu ous until terminated by a low to high transition on ce. 1. 00h will output the manufacture?s id first a nd 01h will output device id first b efore toggling between the two. . high im pena nce 8c 8c 13 13 msb
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 32/43 ? electrical specifications absolute maximum stress ratings (applied conditions are greater than those listed under ?a bsolute maximum stress ratings? may cause permanent damage to the dev ice. this is a stress rating only and functional operation of the device at these conditions or conditi ons greater than those define d in the operational sections of this datas heet is not implied. exposure to absolute maxi mum stress rating conditions may affect device reliability.) storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to vdd+0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to vdd+2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c output short circuit current (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma ( note 1: output shorted for no more than one se cond. no more than one output shorted at a time. ) table 9: ac conditions of test table 10: operating range parameter symbol value unit operating supply voltage v dd 2.7 ~ 3.6 v ambient operating temperature t a -40 ~ +85 table 11: dc operating characteristics limits symbol parameter min max unit test condition standard 9 dual 10.5 i ddr1 read current @ 33mhz quad 12 ma ce =0.1 v dd /0.9 v dd , so=open standard 10 dual 12 i ddr2 read current @ 50mhz quad 13.5 ma ce =0.1 v dd /0.9 v dd , so=open standard 15 dual 16.5 i ddr3 read current @ 86mhz quad 18 ma ce =0.1 v dd /0.9 v dd , so=open standard 22 dual 23.5 i ddr4 read current @ 100mhz quad 25 ma ce =0.1 v dd /0.9 v dd , so=open i ddw program and write status register current 20 ma ce =v dd sector and block erase current 20 ma ce =v dd i dde chip erase current 20 ma ce =v dd i sb1 standby current 25 a ce =v dd , v in =v dd or v ss i sb2 deep power down current 10 a ce =v dd , v in =v dd or v ss i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage -0.5 0.3 x v dd v v ih input high voltage 0.7 x v dd v dd +0.4 v v ol output low voltage 0.4 v i ol =1.6 ma v oh output high voltage v dd -0.2 v i oh =-100 a input rise/fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . . . . c l = 15 pf for R 75mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c l = 30 pf for Q 50mhz see figures 34 and 35
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 33/43 table 12: latch up characteristic symbol parameter minimum unit test method i lth 1 latch up 100 + i dd ma jedec standard 78 note 1: this parameter is measured only for initial qualification and after a design or process change that could affect this p arameter. table 13: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 output pin capacitance v out = 0v 8 pf c in 1 input capacitance v in = 0v 6 pf note 1: this parameter is measured only for initial qualificati on and after a design or process change that could affect this p arameter. table 14: ac operating characteristics normal 33mhz fast 50 mhz fast 86 mhz fast 100 mhz symbol parameter min max min max min max min max unit f clk serial clock frequency 33 50 86 100 mhz t sckh serial clock high time 13 9 6 4 ns t sckl serial clock low time 13 9 6 4 ns t clch 2 clock rise time (slew rate) 0.1 0.1 0.1 0.1 v/ns t chcl 2 clock fall time (slew rate) 0.1 0.1 0.1 0.1 v/ns t ces 1 ce active setup time 5 5 5 5 ns t ceh 1 ce active hold time 5 5 5 5 ns t chs 1 ce not active setup time 5 5 5 5 ns t chh 1 ce not active hold time 5 5 5 5 ns t cph ce deselect time 10 10 10 10 ns t chz ce high to high-z output 7 7 7 7 ns t clz sck low to low-z output 0 0 0 0 ns t ds data in setup time 2 2 2 2 ns t dh data in hold time 1 1 1 1 ns t hls hold low setup time 5 5 5 5 ns t hhs hold high setup time 5 5 5 5 ns t hlh hold low hold time 5 5 5 5 ns t hhh hold high hold time 5 5 5 5 ns t hz 3 hold low to high-z output 8 8 8 8 ns t lz 3 hold high to low-z output 8 8 8 8 ns
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 34/43 table 14: ac operating characteristics - continued normal 33mhz fast 50 mhz fast 86 mhz fast 100 mhz symbol parameter min max min max min max min max unit t oh output hold from sck change 0 0 0 0 ns t v output valid from sck 12 8 8 8 ns t whsl 4 write protect setup time before ce low 20 20 20 20 ns t shwl 4 write protect hold time after ce high 100 100 100 100 ns t dp 3 ce high to deep power down mode 3 3 3 3 us t res1 3 ce high to standby mode ( for dp) 3 3 3 3 us t res2 3 ce high to standby mode (for res) 1.8 1.8 1.8 1.8 us t sus 3 ce high to next instru ction after suspend 20 20 20 20 us note: 1. relative to sck. 2. t sckh + t sckl must be less than or equal to 1/ f clk . 3. value guaranteed by characteriza tion, not 100% tested in production. 4. only applicable as a constraint for a wr ite status register instruction when block- protection-look (bpl) bit is set at 1. table 15: erase and pr ogramming performance limit parameter symbol typ 2 max 3 unit sector erase time (4kb) t se 90 250 ms block erase time (32kb) t be1 500 1000 ms block erase time (64kb) t be2 0.75 1.5 s chip erase time t ce 7 15 s write status register time t w 10 15 ms page programming time t pp 1.5 5 ms erase/program cycles 1 100,000 - cycles data retention 20 - years notes: 1. not 100% tested, excludes external system level over head. 2. typical values measured at 25c, 3v. 3. maximum values measured at 85c, 2.7v.
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 35/43 figure 29: serial input timing diagram figure 30: serial output timing diagram
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 36/43 ce sck so si hold figure 31: hold timing diagram figure 32: write protect setup and hold timing during wrsr when bpl = 1 ce sck si high impenance so t whs l t shwl wp
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 37/43 time v dd v dd (max) v dd (min) v wi t puw t vsl reset state read command is allowed device is fully accessible program, erase and write command is ignored ce must track v dd figure 33: power-up timing diagram table 16: power-up timing and v wi threshold parameter symbol min. max. unit v dd (min) to ce low t vsl 10 us time delay before write instruction t puw 1 10 ms write inhibit threshold voltage v wi 1 2.5 v note: these parameters are characterized only.
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 38/43 figure 34: ac input/output reference waveforms figure 35: a test load example input timing re f erence le v el output timing reference level 0.8vdd 0. 2vdd 0. 7v dd 0. 3vdd 0. 5v dd ac measurement level no te : i n p ut p ulse rise an d f all time are <5ns
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 39/43 packaging dimensions 8-lead soic ( 150 mil ) b e 0 l detail "x" a a1 seating plane d a2 l1 "x" c 1 4 e h 85 0.25 gauge plane dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a 1.35 1.60 1.75 0.053 0.063 0.069 d 4.80 4.90 5.00 0.189 0.193 0.197 a 1 0.10 0.15 0.25 0.004 0.006 0.010 e 3.80 3.90 4.00 0.150 0.154 0.157 a 2 1.25 1.45 1.55 0.049 0.057 0.061 l 0.40 0.66 0.86 0.016 0.026 0.034 b 0.33 0.406 0.51 0.013 0.016 0.020 e 1.27 bsc 0.050 bsc c 0.19 0.203 0.25 0.0075 0.008 0.010 l 1 1.00 1.05 1.10 0.039 0.041 0.043 h 5.80 6.00 6.20 0.228 0.236 0.244 ? ? 0 --- ? 8 ? 0 --- ? 8 controlling dimension : millimenter
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 40/43 packing dimensions 8-lead soic 200 mil ( o fficial name ? 208 mil ) a1 a2 seating plane d b e e 1 4 8 5 detail "x" l1 l a e1 dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a --- --- 2.16 --- --- 0.085 e 7.70 7.90 8.10 0.303 0.311 0.319 a 1 0.05 0.15 0.25 0.002 0.006 0.010 e 1 5.18 5.28 5.38 0.204 0.208 0.212 a 2 1.70 1.80 1.91 0.067 0.071 0.075 l 0.50 0.65 0.80 0.020 0.026 0.032 b 0.36 0.41 0.51 0.014 0.016 0.020 e 1.27 bsc 0.050 bsc c 0.19 0.20 0.25 0.007 0.008 0.010 l 1 1.27 1.37 1.47 0.050 0.054 0.058 d 5.13 5.23 5.33 0.202 0.206 0.210 ? ? 0 --- ? 8 ? 0 --- ? 8 controlling dimension : millimenter
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 41/43 packing dimensions 8-contact wson ( 6x5 mm ) pin# 1 pin# 1 e2 d e e a a1 b l "a" "b" detail : "b" detail : "a" d2 symbol dimension in mm dimension in inch min norm max min norm max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.45 0.014 0.016 0.018 d 5.90 6.00 6.10 0.232 0.236 0.240 d2 2.50 2.60 2.70 0.098 0.102 0.106 e 4.90 5.00 5.10 0.193 0.197 0.201 e2 2.10 2.20 2.30 0.083 0.087 0.091 e 1.27 bsc 0.050 bsc l 0.55 0.60 0.65 0.022 0.024 0.026 controlling dimension : millimete r
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 42/43 revision history revision date description 0.1 2011.09.30 original 0.2 2012.02.13 1.add wson package 2.modify the specification of t se , t be1 , t be2 ,t ce and t pp 1.0 2012.09.24 1. delete "preliminary" 2. modify ambient operating temperature 3. correct the description of block protection and block protection lock-down 1.1 2012.10.11 correct the description of erase suspend 1.2 2013.11.29 1. modify the figures of read sequence and fast read dual i/o sequence ([m7 -m0] = axh) 2. correct max. value of twhsl and tshwl to min. value
esmt f25l08qa (2s) elite semiconductor memory technology inc. publication date : nov. 2013 revision : 1.2 43/43 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docum ent are believed to be accurate at the time of publication. esmt assu mes no responsibilit y for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of o ur products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. no license, either express, implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of esmt or others. any semiconductor devices may have i nherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for us e in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.

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