? semiconductor components industries, llc, 2012 october, 2012 ? rev. 2 1 publication order number: nttfs3a08p/d nttfs3a08pz power mosfet ? 20 v, ? 15 a, single p ? channel, 8fl features ? ultra low r ds(on) to minimize conduction losses ? 8fl 3.3 x 3.3 x 0.8 mm for space saving and excellent thermal conduction ? esd protection level of 5 kv per jesd22 ? a114 ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? battery switch ? high side load switch ? optimized for power management applications for portable products such as media tablets, ultrabook pcs and cellphones maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain ? to ? source voltage v dss ? 20 v gate ? to ? source voltage v gs 8 v continuous drain current r ja (note 1) steady state t a = 25 c i d ? 15 a t a = 85 c ? 11 power dissipation r ja (note 1) t a = 25 c p d 2.3 w continuous drain current r ja 10 s (note 1) t a = 25 c i d ? 22 a t a = 85 c ? 16 power dissipation r ja 10 s (note 1) t a = 25 c p d 4.9 w continuous drain current r ja (note 2) t a = 25 c i d ? 9 a t a = 85 c ? 7 power dissipation r ja (note 2) t a = 25 c p d 0.84 w pulsed drain current t a = 25 c, t p = 10 s i dm ? 46 a operating junction and storage temperature t j , t stg ? 55 to +150 c esd (hbm, jesd22 ? a114) v esd 5000 v source current (body diode) i s ? 3 a lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface ? mounted on fr4 board using 1 sq ? in pad, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. ordering information http://onsemi.com device package shipping ? v (br)dss r ds(on) max i d max ? 20 v 6.7 m @ ? 4.5 v ? 15 a p ? channel mosfet ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. wdfn8 ( 8fl) case 511ab marking diagram 9.0 m @ ? 2.5 v NTTFS3A08PZTAG wdfn8 (pb ? free) 1500 / tape & reel (note: microdot may be in either location) 1 3a08 = specific device code a = assembly location y = year ww = work week = pb ? free package 1 nttfs3a08pztwg wdfn8 (pb ? free) 5000 / tape & reel 3a08 ayww d d d d s s s g d g s
nttfs3a08pz http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? ambient ? steady state (note 3) r ja 55 c/w junction ? to ? ambient ? steady state (note 4) r ja 148 junction ? to ? ambient ? (t 10 s) (note 3) r ja 26 3. surface ? mounted on fr4 board using 1 sq ? in pad, 1 oz cu. 4. surface ? mounted on fr4 board using the minimum recommended pad size (40 mm 2 , 1 oz. cu). electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a ? 20 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 6 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = ? 16 v t j = 25 c ? 1 a gate ? to ? source leakage current i gss v ds = 0 v, v gs = 5 v 5 a on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = ? 250 a ? 0.4 ? 1.0 v negative threshold temperature coefficient v gs(th) /t j 3.3 mv/ c drain ? to ? source on resistance r ds(on) v gs = ? 4.5 v i d = ? 12 a 4.9 6.7 m v gs = ? 2.5 v i d = ? 10 a 6.9 9.0 forward transconductance g fs v ds = ? 1.5 v, i d = ? 8 a 62 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = ? 10 v 5000 pf output capacitance c oss 600 reverse transfer capacitance c rss 540 total gate charge q g(tot) v gs = ? 4.5 v, v ds = ? 10 v, i d = ? 8 a 56 nc threshold gate charge q g(th) 2.0 gate ? to ? source charge q gs 6.5 gate ? to ? drain charge q gd 15.4 switching characteristics (note 6) turn ? on delay time t d(on) v gs = ? 4.5 v, v ds = ? 10 v, i d = ? 8 a, r g = 6.0 13 ns rise time t r 60 turn ? off delay time t d(off) 250 fall time t f 170 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = ? 3 a t j = 25 c ? 0.65 ? 1.0 v reverse recovery time t rr v gs = 0 v, d is /d t = 100 a/ s, i s = ? 6 a 207 ns charge time t a 45 discharge time t b 162 reverse recovery charge q rr 234 nc 5. pulse test: pulse width = 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
nttfs3a08pz http://onsemi.com 3 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics ? v ds , drain ? to ? source voltage (v) ? v gs , gate ? to ? source voltage (v) 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage ? v gs , gate voltage (v) ? i d , drain current (a) 4.0 3.5 3.0 4.5 2.5 2.0 1.5 1.0 0 0.01 0.03 0.04 0.05 0.07 0.08 0.10 40 30 20 10 0 0 0.005 0.010 0.015 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) ? v ds , drain ? to ? source voltage (v) 125 100 75 50 25 0 ? 25 ? 50 0.7 0.8 0.9 1.1 1.2 1.3 1.5 1.6 18 16 12 10 8 6 4 2 100 1000 10,000 100,000 ? i d , drain current (a) ? i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , normalized drain ? to ? source resistance ( ) ? i dss , leakage (na) v gs = ? 1.8 v ? 2 v ? 4.5 v to ? 2.5 v v ds ? 10 v t j = 125 c t j = 25 c t j = ? 55 c v gs = ? 1.8 v t j = 25 c v gs = ? 2.5 v v gs = ? 4.5 v 0.02 0.06 0.09 r ds(on) , drain ? to ? source resistance ( ) t j = 25 c i d = ? 12 a 150 1.0 1.4 v gs = ? 4.5 v i d = ? 12.0 a 14 20 t j = 125 c t j = 85 c
nttfs3a08pz http://onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge ? v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 18 14 10 8 6 4 2 0 0 800 1600 3200 4800 5600 6400 8000 60 50 40 30 20 10 0 0 1 2 3 4 5 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) ? v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1000 0.9 0.8 1.0 0.7 0.6 0.5 0.4 0.3 0.1 1 10 figure 11. threshold voltage figure 12. single pulse maximum power dissipation t j , temperature ( c) single pulse time (s) 125 100 75 50 25 0 ? 25 ? 50 0.15 0.25 0.35 0.45 0.55 0.75 0.85 0.95 1.e+02 1.e ? 02 1.e ? 04 0 50 100 150 200 300 350 400 c, capacitance (pf) ? v gs , gate ? to ? source voltage (v) t, time (ns) ? i s , source current (a) ? v gs(th) (v) power (w) 12 16 20 2400 4000 7200 v gs = 0 v t j = 25 c f = 1 mhz c iss c oss c rss 0 4 2 6 14 18 8 10 12 16 ? v ds , drain ? to ? source voltage (v) v ds = ? 10 v i d = ? 8 a t j = 25 c q t v gs q gs q gd v ds v gs = ? 4.5 v v dd = ? 10 v i d = ? 8 a t d(off) t f t r t d(on) t j = 125 c t j = 25 c t j = ? 55 c 0.65 150 i d = ? 250 a 250 1.e+00
nttfs3a08pz http://onsemi.com 5 typical characteristics figure 13. maximum rated forward biased safe operating area ? v ds , drain ? to ? source voltage (v) 100 10 1 0.1 0.01 0.1 1 10 100 figure 14. fet thermal response t, time (s) 1e ? 06 0 10 20 30 40 50 60 ? i d , drain current (a) r(t), effective transient thermal response 1e ? 05 1e ? 04 1e ? 03 1e ? 02 1e ? 01 1e+00 1e+01 1e+02 1e+03 r ja = 55 c/w single pulse duty cycle = 0.5 0.01 0.02 0.05 0.10 0.20 100 s 1 ms dc 10 ms v gs = ? 8 v single pulse t c = 25 c r ds(on) limit thermal limit package limit
nttfs3a08pz http://onsemi.com 6 package dimensions wdfn8 3.3x3.3, 0.65p case 511ab issue d m 1.40 1.50 0 ??? 1.60 12 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 5 6 top view side view bottom view d1 e1 d e b a 0.20 c 0.20 c 2x 2x dim min nom millimeters a 0.70 0.75 a1 0.00 ??? b 0.23 0.30 c 0.15 0.20 d d1 2.95 3.05 d2 1.98 2.11 e e1 2.95 3.05 e2 1.47 1.60 e 0.65 bsc g 0.30 0.41 k 0.65 0.80 l 0.30 0.43 l1 0.06 0.13 a 0.10 c 0.10 c detail a 14 8 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 6x c 4x c seating plane 5 max 0.80 0.05 0.40 0.25 3.15 2.24 3.15 1.73 0.51 0.95 0.56 0.20 m *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 0.42 0.75 2.30 3.46 package 8x 0.055 0.059 0 ??? 0.063 12 0.028 0.030 0.000 ??? 0.009 0.012 0.006 0.008 0.116 0.120 0.078 0.083 0.116 0.120 0.058 0.063 0.026 bsc 0.012 0.016 0.026 0.032 0.012 0.017 0.002 0.005 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.020 0.037 0.022 0.008 min nom inches max 7 8 pitch 3.60 0.57 0.47 outline dimension: millimeters 3.30 bsc 3.30 bsc 0.130 bsc 0.130 bsc 2.37 0.66 4x e3 0.23 0.30 0.40 0.009 0.012 0.016 e3 4x on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nttfs3a08p/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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