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this is information on a product in full production. november 2013 docid025551 rev 1 1/17 STL7N80K5 n-channel 800 v, 0.95 typ., 3.6 a zener-protected supermesh? 5 power mosfet in a powerflat? 5x6 vhv package datasheet ? production data figure 1. internal schematic diagram features ? outstanding r ds(on) *area ? worldwide best fom (figure of merit) ? ultra low gate charge ? 100% avalanche tested ? zener protected applications ? switching applications description this n-channel zener-protected power mosfet is designed using st's revolutionary avalanche- rugged very high voltage supermesh? 5 technology, based on an innovative proprietary vertical structure. the result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. am15540v1 5 6 7 8 12 34 top view d(5, 6, 7, 8) g(4) s(1, 2, 3) powerflat? 5x6 vhv 1 2 3 4 order code v ds r ds(on)max. i d STL7N80K5 800 v 1.2 3.6 a table 1. device summary order code marking package packaging STL7N80K5 7n80k5 powerflat? 5x6 vhv tape and reel www.st.com
contents STL7N80K5 2/17 docid025551 rev 1 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 docid025551 rev 1 3/17 STL7N80K5 electrical ratings 17 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v gs gate-source voltage 30 v i d (1) 1. the value is rated according to r thj-case and limited by package. drain current (continuous) at t c = 25 c 3.6 a i d (1) drain current (continuous) at t c = 100 c 2.3 a i dm (1),(2) 2. pulse width limited by safe operating area. drain current (pulsed) 14 a p tot (1) total dissipation at t c = 25 c 42 w i ar (3) 3. pulse width limited by t jmax avalanche current, repetitive or not- repetitive (pulse width limited by t j max) 2a e as (4) 4. starting t j =25 c, i d =i ar , v dd =50 v single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 88 mj dv/dt (5) 5. i sd 3.6 a, di/dt 100 a/s, v ds(peak) v (br)dss peak diode recovery voltage slope 4.5 v/ns dv/dt (6) 6. v ds 640 v mosfet dv/dt ruggedness 50 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 3 c/w r thj-amb (1) 1. when mounted on 1inch2 fr-4 board, 2 oz cu. thermal resistance junction-amb max 59 c/w electrical characteristics STL7N80K5 4/17 docid025551 rev 1 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 1 ma 800 v i dss zero gate voltage drain current (v gs = 0) v ds = 800 v v ds = 800 v, t c =125 c 1 50 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 3 a 0.95 1.2 ? table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 - 360 - pf c oss output capacitance - 30 - pf c rss reverse transfer capacitance -1-pf c o(tr) (1) 1. c oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss equivalent capacitance time related v ds = 0 to 640 v, v gs = 0 -47-pf c o(er) (2) 2. c oss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss equivalent capacitance energy related -20-pf r g intrinsic gate resistance f = 1 mhz, i d =0 - 6 - ? q g total gate charge v dd = 640 v, i d = 6 a, v gs = 10 v (see figure 16 ) -13.4-nc q gs gate-source charge - 3.7 - nc q gd gate-drain charge - 7.5 - nc docid025551 rev 1 5/17 STL7N80K5 electrical characteristics 17 the built-in back-to-back zener diodes have been specifically designed to enhance not only the device's esd capability, but also to make them capable of safely absorbing any voltage transients that may occasionally be applied from gate to source. in this respect, the zener voltage is appropriate to achieve efficient and cost-effective protection of device integrity. the integrated zener diodes thus eliminate the need for external components. table 6. switching times symbol parameter test conditions min. typ. max unit t d(on) turn-on delay time v dd = 400 v, i d = 3 a, r g = 4.7 w, v gs = 10 v (see figure 15 ), (see figure 20 ) - 11.3 - ns t r rise time - 8.3 - ns t d(off) turn-off delay time - 23.7 - ns t f fall time - 20.2 - ns table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd source-drain current - 3.6 a i sdm source-drain current (pulsed) - 14 a v sd (1) 1. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 6 a, v gs = 0 - 1.5 v t rr reverse recovery time i sd = 6 a, di/dt = 100 a/s v dd = 60 v (see figure 17 ) -315 ns q rr reverse recovery charge - 2.8 c i rrm reverse recovery current - 17.5 a t rr reverse recovery time i sd = 6 a, di/dt = 100 a/s v dd = 60 v, t j = 150 c (see figure 17 ) -480 ns q rr reverse recovery charge - 3.8 c i rrm reverse recovery current - 16 a table 8. gate-source zener diode symbol parameter test conditions min typ. max unit v (br)gso gate-source breakdown voltage i gs = 1ma, i d =0 30 - - v electrical characteristics STL7N80K5 6/17 docid025551 rev 1 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance i d 10 1 0.1 0.01 0.1 1 100 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 10s 100s 1ms 10ms tj=150c tc=25c single pulse am17897v1 single pulse =0.5 0.05 0.02 0.01 0.1 0.2 k 10 t p (s) -4 10 -3 10 -2 10 -1 10 -5 10 -3 10 -2 10 -1 10 0 pcb 10 1 zthpowerflat_5x6_27 figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on-resistance ) ' 9 ' 6 9 $ 9 9 9 9 9 * 6 9 $ 0 y ) ' 9 * 6 9 $ 9 ' 6 9 $ 0 y 6 * 6 4 j q & |