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data sheet, rev. 1.0, december 2007 automotive power spider - TLE7232GS spi driver for enhanced relay control
data sheet 2 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS table of contents 1product summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.3 inductive output clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.6 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.2 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.5 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 diagnostic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.1 diagnosis timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.1.1 open load behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.1.2 short to ground behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.3 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.5 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4.6 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table of contents
pg-ssop-24-6 type package marking spider - TLE7232GS pg-ssop-24-6 TLE7232GS data sheet 3 rev. 1.0, 2007-12-18 spi driver for enhanced relay control eight channel low-side switch spider - TLE7232GS 1product summary features table 1 product summary supply voltage supply voltage for so buffer on-state resistance at 150 v dd 4.5 ? 5.5 v v vso 3.0 ? 5.5 v r ds(on, max) 2.1 ? i l(nom, min) 240 ma i ds(lim, min) 1 a i dd(rst, max) 5 i ds(off, max) 1 v ds(cl, min) 48 v f sclk(max) 5 mhz
spi driver for enhanced relay control spider - TLE7232GS product summary data sheet 4 rev. 1.0, 2007-12-18 protective functions ? short circuit protection ? overload protection, configurable behavior (limitation or shutdown) ? thermal shutdown, configurable behavior (latch or restart) ? electrostatic discha rge protection (esd) diagnostic functions ? diagnostic information via spi ? open load detection in off-state ? shorted to gnd detection in off-state ? overtemperature in on-state ? overload in on-state applications ? especially designed for driving relays in automotive applications ? all types of capacitive, resistive and inductive loads description the spider - TLE7232GS is an eight chan nel low-side relay switch (typ. 1.0 : per channel) in pg-ssop-24-6 package providing embedded protective functions. the 16 bit serial peri pheral interface (spi) is utilized for control and diagnosis of the device and the loads. the spi interface provides da isy-chain capability in order to assemble multiple devices in one spi chain by using the same number of micro-controller pins. the spider - TLE7232GS is equipped with three input pins that can be individually routed to the output control of some channels (please refer to section 5.1.2 for details) thus o ffering complete flexibility in design and pcb- layout. the input mapping as well as the boolean oper ation between input signal an output control signal is configured via spi. the device provides full diagnosis of the load, which is open load, short to gnd as well as short circuit to v bat detection and overload / overtemperature indication. the sp i diagnosis flags indicate la tched fault conditions that may have occurred. each output stage is protected against short circuit. in case of overload, th e current of the affected channel is limited. there is a temperature sensor available for each channel to protect the device in case of overtemperature. the shut down behavior in case of overload or over temperature can be configured via spi for each channel individually.
overview_gs . emf cs si sclk so spi control, diagnostic and protective functions open load detection temperature sensor gate control short circuit detection gnd in3 rst vdd out7 out6 out5 out4 out3 out2 out1 out0 hardware configuration output monitor boolean operation input map output control diagnosis register vso reset / stand-by in0 in2 data sheet 5 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block diagram 2 block diagram figure 1 block diagram
ter m s _45 . em f v cs v scl k v in1 v si i so so i scl k i si sclk si i cs cs v so gnd i gnd out0 v ds0 i d1 out1 out2 v ds2 v ds1 i d3 out3 v ds3 i d0 i d2 v bat v vso i vso vso v rst i rst rst i dd vdd v dd out4 v ds4 i d5 out5 out6 v ds6 v ds5 i d7 out7 v ds7 i d4 i d6 i in0 in0 i in2 in2 i in3 in3 v in2 v in3 spider - TLE7232GS spi driver for enhanced relay control spider - TLE7232GS block diagram data sheet 6 rev. 1.0, 2007-12-18 2.1 terms following figure shows all term s used in this data sheet. figure 2 terms in all tables of electrical characteristics is valid: channe l related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds7 ). all spi register bits are marked as follows: addr.parameter (e.g. ctl.out0 ). in spi register description, the values in bold letters (e.g. 0 ) are default values.
pg-ssop-2 4 -6 . e m f ( top view) 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 18 17 16 15 11 12 14 13 in0 out2 out3 gnd cs gnd gnd gnd out4 out5 vso so vdd out1 out0 rst out7 out6 si sclk in2 in3 nc nc data sheet 7 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS pin configuration 3 pin configuration 3.1 pin assignment figure 3 pin configuration 3.2 pin definitions and functions pin symbol i/o function power supply 17 v dd ? power supply 5 v so ? power supply for so buffer 1, 2, 11, 12 gnd ? ground power stages 14 out0 o drain of power transistor channel 0 15 out1 o drain of power transistor channel 1 22 out2 o drain of power transistor channel 2 23 out3 o drain of power transistor channel 3 3 out4 o drain of power transistor channel 4 4 out5 o drain of power transistor channel 5 9 out6 o drain of power transistor channel 6 10 out7 o drain of power transistor channel 7
spi driver for enhanced relay control spider - TLE7232GS pin configuration data sheet 8 rev. 1.0, 2007-12-18 inputs 18 rst i reset input pin (active low) 16 in0 i input multiple xer input pin for output out0 20 in2 i input multiple xer input pin for output out2 21 in3 i mappable input pin for all outputs, default out3 spi 19 cs i spi chip select (active low) 7 sclk i serial clock 8 si i serial data in 6 so o serial data out not used 13, 24 nc ? not connected pin symbol i/o function
data sheet 9 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS general product characteristics 4 general product characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 q c to 150 q c; v dd = 4.5 v to 5.5 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. power supply 4.1.1 power supply voltage v dd -0.3 5.5 v ? 4.1.2 v so supply voltage v vso -0.3 v dd + 0.3 v 2) 4.1.3 power supply voltage for full short circuit protection (single pulse) v bat(sc) 0 ? 20 28 v ovl = 0 3) ovl = 1 power stages 4.1.4 load current i d -1 1 a ? 4.1.5 voltage at power transistor v ds ?48v? 4.1.6 maximum energy dissipation one channel single pulse e as mj 4) ?65 t j(0) = 85 q c i d(0) = 0.35 a ?30 t j(0) = 150 q c i d(0) = 0.25 a maximum energy dissipation one channel repetitive pulses e ar mj 4) t j(0) = 150 q c 1 10 4 cycles ? 18 i d(0) = 0.20 a 1 10 6 cycles ? 13 i d(0) =0.17 a logic pins 4.1.7 voltage at input pins v in -0.3 5.5 v ? 4.1.8 voltage at reset pin v rst -0.3 5.5 v ? 4.1.9 voltage at chip select pin v cs -0.3 5.5 v ? 4.1.10 voltage at serial clock pin v sclk -0.3 5.5 v ? 4.1.11 voltage at serial input pin v si -0.3 5.5 v ? 4.1.12 voltage at serial output pin v so -0.3 5.5 v ? temperatures 4.1.13 junction temperature t j -40 150 q c? 4.1.14 dynamic temperature increase while switching ' t j ?60 q c? 4.1.15 storage temperature t stg -55 150 q c?
pos. parameter symbol spi driver for enhanced relay control spider - TLE7232GS general product characteristics data sheet 10 rev. 1.0, 2007-12-18 note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . esd susceptibility 4.1.16 esd capability of all pins versus gnd v esd -2 2 kv hbm 5) 1) not subject to production test, specified by design. 2) v dd + 0.3 v < 5.5 v 3) details on configuration of protecti ve function olcr.ovl can be found in section 5.2.5 4) pulse shape represents inductive switch off: i d (t) = i d (0) (1 - t / t pulse ); 0 < t < t pulse 5) esd susceptibility, hbm acco rding to eia/jesd 22-a114b limit values unit conditions min. typ. max. 4.2.17 junction to solder point r thjsp ? ? 25 k/w pin 1, 2, 11, 12 1) 1) specified r thjsp value is simulated at natural convection on a cold pl ate setup (all pins are fix ed to ambient temperature). t a = 25 c. ls0 to ls7 are dissipating 1 w power (0.125 w each). 4.2.18 junction to ambient (1s0p+600mm 2 cu) r thja ?64?k/w 1)2) 2) specified r thja value is according to jedec jesd51-2,-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm 2 and 70 m thickness. t a = 25 c, ls0 to ls7 are dissipating 1 w power (0.125 w each). 4.2.19 junction to ambient (2s2p) r thja ?55?k/w 1)3) 3) specified r thja value is according to jedec jesd51-2,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). t a = 25 c, ls0 to ls7 are dissipating 1 w power (0.125 w each). absolute maximum ratings (cont?d) 1) t j = -40 c to 150 c; v dd = 4.5 v to 5.5 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
data sheet 11 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5 block description and el ectrical characteristics 5.1 power stages the spider - TLE7232GS is an eight channel low-side relay switch. the power stages are built by n-channel vertical power mosfet transistors. 5.1.1 power supply the spider - TLE7232GS is supplied by power supply line v dd which is used for the digital as well as the analog functions of the device including th e gate control of the power stages. there is a power-on reset function implemented for the supply line. after start-up of the power supply, all spi registers are reset to their default values. a capacitor at pins v dd to gnd is recommended. the pin v so is the supply pin of the digital output buffer at pin so. v so can therefore be used to vary the high state output vo ltage of the so pin, in order to be compatible to 3.3 v and 5 v microcontrollers. if v so supply voltage is missing the device is fully functional, only the so pin has no output. there is a reset pin available. at low le vel at this pin, all registers are set to their default values and the quiescent supply current is minimized.
channel 7 channel 6 channel 5 channel 4 i nput logic_gs . emf in2 i in in3 i in in0 i in channel 3 & or out3 bol3 map3 gate control sle3 map0 out0 bol0 sle0 channel 1 & or map1 out1 bol1 gate control sle1 map0 out0 bol0 sle0 channel 2 & or map2 out2 bol2 gate control sle2 map0 out0 bol0 sle0 channel 0 & or map0 out0 bol0 gate control sle0 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 12 rev. 1.0, 2007-12-18 5.1.2 input circuit there are three input pins available at spi der - TLE7232GS to control the output stages. figure 4 input mapping and boolean operator the input signal of in3 can be configured to be used as control signal of the output stages for each channel separately. the channels 0 to 2 differ from the channels 3 to 7 in the mapping behavior. in0 is a direct input to channel out0, while in2 is a direct input to out2. out0 can be switched with the spi flag map0 to the mappable input in3, default is in0. out2 can be switched with the spi flag map2 to the mappable input in3, default is in2. out3 is controlled by default with in3, but in3 can be programmed to each channel. therefore after power up the inputs are always mapped to their corresponding outputs. please refer to figure 4 for details. the current sink to ground at the input pins ensures that the channels switch off in ca se of open pin. the zener diode protects the input ci rcuit against esd pulses.
out put clamp . emf v bat i d v ds( cl ) out v ds gnd l , r l data sheet 13 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5.1.3 inductive output clamp when switching off inductive loads, the potential at pin out rises to v ds(cl) potential, because the inductance intends to continue driving the current. the voltage clampi ng is necessary to prevent destruction of the device, see figure 5 for details. nevertheless, the maxi mum allowed load inductance is limited. figure 5 output clamp implementation maximum load inductance cs v ds t switchon.emf t on t off t 20% 80% spi: on spi: off during demagnetization of inductive loads, energy has to be dissipated in the spider - TLE7232GS. this energy can be calculated with following equation: (1) the equation simplifies under the assumption of r l = 0: (2) the energy, which is converted into heat, is limited by the thermal design of the component. 5.1.4 timing diagrams the power transistors are switched on and off with a dedicated slope via the out bits of the serial peripheral interface spi. the switching times t on and t off are designed equally. figure 6 switching a resistive load when the input mapping is configured accordingly, a high sign al at the input pin is equivalent to a spi on command. ev ds(cl) v bat v ? ds(cl) r l --------------------------------- - ln ? r l i d ? v bat v ? ds(cl) --------------------------------- - ? ?? ?? i d + l r l ------ ?? e 1 2 -- - li d 2 1 v bat v bat v ? ds(cl) --------------------------------- - ? ?? ?? ?
spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 14 rev. 1.0, 2007-12-18 5.1.5 electrical characteristics electrical characteristics: power stages t j = -40 q c to 150 q c; v dd = 4.5 v to 5.5 v (unless otherwise specified); a ll voltages with respect to ground, positive current flowing into pin; typical values: v dd = 5.0 v, t j = 25 q c pos. parameter symbol limit values unit conditions min. typ. max. power supply 5.1.1 power supply voltage v dd 4.5 ? 5.5 v ? 5.1.2 power supply current i dd(on) ?35maall channels on 5.1.3 power supply reset current i dd(rst) ??5 p a v rst = 0 v v in = 0 v v sclk = 0 v v si = 0 v v cs = v dd 5.1.4 power-on reset threshold voltage v dd(po) ??4.5v? output characteristics 5.1.5 on-state resistance per channel r ds(on) ?1.01.2 2.1 : t j = 25 q c 1) t j = 150 q c i l = 500 ma v dd = 5 v 5.1.6 nominal load current i l(nom) 240??ma 1) all channels on based on r thja = 64 k/w r ds(on) = 2.1 : t a = 85 q c t j,max = 150 q c 5.1.7 output leakage current in stand-by mode (per channel) i d(rst) ? ? ? ? ? ? 1 2 5 p a v ds = 13.5 v t j = 25 q c 1) t j = 125 q c t j = 150 q c 1) 5.1.8 output clamping voltage v ds(cl) 48 ? 60 v ? input characteristics 5.1.9 l level of pin in v in(l) 0?1.0v? 5.1.10 h level of pin in v in(h) 2.0 ? v dd v? 5.1.11 input voltage hysteresis at pin in ' v in ?0.1?v 1) 5.1.12 l-input pull-down current through pin in i in(l) 10 ? 100 p a 1) v in = 1 v 5.1.13 h-input pull-down current through pin in i in(h) 20 50 100 p a v in = 5 v
data sheet 15 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics note: characteristics show the deviat ion of parameter at the given supply voltage and junction temperature. typical values show the typical param eters expected from manufacturing. reset 5.1.14 l level of pin rst v rst(l) 0?1v? 5.1.15 h level of pin rst v rst(h) 2? v dd v? 5.1.16 l-input pull-up current through pin rst i rst(l) 0?10 p a v rst = 1 v 5.1.17 h-input pull-up current through pin rst i rst(h) 20 50 100 p a v rst = 2 v timings 5.1.18 power-on wake-up time t wu(po) ??200 p s? 5.1.19 reset duration t rst(l) 10 ? ? p s? 5.1.20 turn-on time v ds = 20% v bat t on ? ? ? ? 15 60 p s v bat = 14 v i ds = 500 ma, resistive load sle = 0 sle = 1 5.1.21 turn-off time v ds = 80% v bat t off ? ? ? ? 15 60 p s v bat = 14 v i ds = 500 ma, resistive load sle = 0 sle = 1 1) not subject to production test, specified by design. electrical characteristics: power stages (cont?d) t j = -40 q c to 150 q c; v dd = 4.5 v to 5.5 v (unless otherwise specified); a ll voltages with respect to ground, positive current flowing into pin; typical values: v dd = 5.0 v, t j = 25 q c pos. parameter symbol limit values unit conditions min. typ. max.
field bits type description mapn (n = 7-0) field bits type description boln (n = 7-0) field bits type description slen (n = 7-0) spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 16 rev. 1.0, 2007-12-18 5.1.6 command description imcr input mapping configurati on register reset value: 08 h 76543210 map7 map6 map5 map4 map3 map2 map1 map0 rw rw rw rw rw rw rw rw nrw input mapping configuration channel n 0 channel n can not be controlled with mappable input pin in3. out0 is controlled by in0. out2 is controlled by in2. out3 is controlled by the ma ppable in3 (default value). 1 channel n can be controlled with mapable input pin in3, depending on additional set-up. bocr boolean operator configuration register reset value: 00 h 76543210 bol7 bol6 bol5 bol4 bol3 bol2 bol1 bol0 rw rw rw rw rw rw rw rw nrw boolean operator configuration channel n 0 logic ?or? for channel n (default value). 1 logic ?and? for channel n. srcr slew rate configuration register reset value: 00 h 76543210 sle7 sle6 sle5 sle4 sle3 sle2 sle1 sle0 rw rw rw rw rw rw rw rw nrw slew rate configuration channel n 0 channel n is switched fast (default value). 1 channel n is switched slowly.
field bits type description outn (n = 7-0) prot ect ion. emf outn input mapping mapn boln outn in2 temperature monitor current limitation gate control ovtn t tn cln ovln & & delay gnd in0 in3 data sheet 17 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5.2 protection functions the device provides embedded protecti ve functions. integrated protection f unctions are designed to prevent ic destruction under fault conditions described in this data sheet. fault conditions ar e considered as ?outside? normal operating range. protection functions are no t designed for continuou s repetitive operation. there is an overload and overtemperature protection im plemented in the spider - TLE7232GS. the behavior of the protective functions can be set-up via spi. following fi gure gives an overview about the protective functions. figure 7 protective functions ctl output control register reset value: 00 h 76543210 out7 out6 out5 out4 out3 out2 out1 out0 rw rw rw rw rw rw rw rw nrw output control channel n 0 channel n is switched off (default value). 1 channel n is switched on, depending on additional set-up.
overloadtiming . emf in i d t t t d(fault) l = 1 b l = 0 b i d( l im) in i d t t t d(off) l = 1 b l = 0 b i d(lim) olcr.ovl = 0 olcr.ovl = 1 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 18 rev. 1.0, 2007-12-18 5.2.1 overload protection the spider - TLE7232GS is protected in case of overload or short circuit of the load. the behavior in case of overload can be configured as follows: 1. the current is limited to i ds(lim) . after time t d(fault) , the according overload flag cln is set. the channel may shut down due to overtemperature. 2. the current is limited to i ds(lim) . after time t d(off) , the overloaded channel n switches off and the according overload flag cln is set. the overload flag ( cln ) of the affected channel is cleared by a low-hi gh transition of the input signal. for timing information, please refer to figure 8 for details. figure 8 overload behavior 5.2.2 overtemperature protection a temperature sensor for each channel causes an overheated channel n to switch off immediately to prevent destruction. the behavior in case of over temperature can be configured as follows: 1. after cooling down, the channel is sw itched on again with thermal hysteresis ? t j . 2. the affected channel stays switched off until the overtemperature flag is cleared. the overtemperature flag of the affected channel is cl eared by a low-high transition of the input signal. 5.2.3 reverse polarity protection in case of reverse polarity, the intrinsic body diode of the power transistor causes power dissipation. the reverse current through the intrinsic body diode has to be limited by the connected load. the v dd supply pin must be protected against reverse pola rity externally. the overtemperature protecti on as well as other protective functions are not active during reverse polarity.
pos. parameter symbol field bits type description ovln (n = 7-0) field bits type description ovtn (n = 7-0) data sheet 19 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5.2.4 electrical characteristics 5.2.5 command description electrical characteristics: protection functions v dd = 4.5 v to 5.5 v, t j = -40 c to 150 c, all voltages with respect to ground , positive current flowing into pin (unless otherwise specified); typical values: v dd = 5.0 v, t j = 25 c limit values unit conditions min. typ. max. overload protection 5.2.1 overload current limitation i d(lim) 1?2a ovl = 0 5.2.2 overload shut-down delay time t d(off) 10 ? 50 s ovl = 1 overtemperature protection 5.2.3 overtemperature shut-down threshold t j(ot) 170 ? 200 c 1) 1) not subject to production test, specified by design. 5.2.4 thermal hysteresis ? t j(ot) ?10?k 1) olcr overload configuration register reset value: 00 h 76543210 ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 rw rw rw rw rw rw rw rw nrw overload configuration channel n 0 channel n limits the current in case of overload (default value). 1 channel n shuts down in case of overload. otcr overtemperature configuration register reset value: 00 h 76543210 ovt7 ovt6 ovt5 ovt4 ovt3 ovt2 ovt1 ovt0 rw rw rw rw rw rw rw rw nrw overtemperature configuration channel n 0 autorestart (default value) 1 latched shut down
outn i ds( pd) sgn vdd v ds( sg ) i ds( sg ) diagnosis . emf protective functions cln tn or spi mux 00 01 10 oln v ds( o l ) chn outn sta. gate control pn gnd spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 20 rev. 1.0, 2007-12-18 5.3 diagnostic features the spi of spider - TLE7232GS provides diagnosis information about the device and about the load. there are following diagnosis flags implemented: ? the diagnosis information of th e protective functions (flags cln and tn ) of channel n is latched in the diagnosis flag pn . ? the open load diagnosis of channel n is latched in the diagnosis flag oln . ? the short to gnd monitor information of channel n is latched in the diagnosis flag sgn . all flags are cleared after a successful spi transmission. there is an output state monito r implemented in the device that indicates th e switch state of the device in register sta . depending on the voltage level at input pin and protective functions the bits are high or low. please see figure 9 for details: figure 9 block diagram diagnosis
openloadtiming . emf in v ds t t t d ( fa u lt) ol n = 1 b open load occures here in v ds t t t d(fault) ol n = 1 b v ds( o l ) open load occures here v ds( o l ) short toground . emf in v ds t t t d(fault) sg n = 1 b short to ground occures here in v ds t t t d(fault) ol n = 1 b v ds( o l ) short to ground occures here data sheet 21 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5.3.1 diagnosis timing the spider - TLE7232GS offers 2 differen t diagnosis for each channel in off mode. 5.3.1.1 open load behavior the device offers a open load diagnosis for each channel in off mode. the time t d(fault) is applied to filter short time events. figure 10 open load timing 5.3.1.2 short to ground behavior the device offers a short to ground detection for each channel in off mode. the time t d(fault) is applied to filter short time events. figure 11 short to ground timing
pos. parameter symbol field bits type description outn (n = 7-0) spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 22 rev. 1.0, 2007-12-18 5.3.2 electrical characteristics 5.3.3 command description electrical characteristics: diagnostic v dd = 4.5 v to 5.5 v, t j = -40 c to 150 c, all voltages with respect to ground , positive current flowing into pin (unless otherwise specified); typical values: v dd = 5.0 v, t j = 25 c limit values unit conditions min. typ. max. off state diagnosis 5.3.1 open load detection threshold voltage v ds(ol) v dd - 2.5 v dd - 2 v dd - 1.3 v ? 5.3.2 output pull-down diagnosis current per channel i d(pd) 50 90 150 a? 5.3.3 short to gnd detection threshold voltage v ds(sg) v dd - 3.4 v dd - 3.0 v dd - 2.6 v ? 5.3.4 output diagnosis current for short to gnd per channel i d(sg) -150 -100 -50 a v ds = 0 v 5.3.5 fault delay time t d(fault) 50 100 200 s? sta output status monitor reset value: 00 h 76543210 out7 out6 out5 out4 out3 out2 out1 out0 rrrrrrrr nr output status 0 voltage level at channel n: v ds > v ds(ol) . 1 voltage level at channel n: v ds < v ds(ol) .
14 13 12 11 14 13 12 11 msb msb spi.emf lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 10 9 8 10 9 8 7 7 so si cs sclk time data sheet 23 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5.4 serial peripheral interface (spi) the diagnosis and control interface is based on a serial peripheral interface (spi). the spi is a full duplex synchronous serial slave in terface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the data rate given by sclk. the falling edge of cs indicates the beginning of a data access. data is sampled in on line si at the falling ed ge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. the interf ace provides daisy chain capability. figure 12 serial peripheral interface the spi protocol is described in section 5.4.5 . it is reset to the default values after power-on reset or a low signal at pin rst. 5.4.1 spi signal description cs - chip select: the system microcontroller selects the spider - TLE7232GS by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the diagnosis information is transferred into the shift register. cs low to high transition: ? command decoding is only done, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. ? data from shift register is transfer red into the input matrix register. ? the diagnosis flags are cleared. sclk - serial clock: this input pin clocks the internal shift register . the serial input (si) transfers data into the shift register on the fa lling edge of sclk while the serial output (so) shifts diagnostic information out on the rising edge of the serial clock. it is es sential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shifted in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the 16 bi t input data consist of two parts (c ontrol and data). please refer to section 5.4.5 for further information. so serial output: data is shifted out serially at th is pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appear at th e so pin following the rising edge of sclk. please refer to section 5.4.5 for further information. the high state ou tput voltage depends on the voltage at pin v so .
si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _dasychain. emf mi mo mcs mclk si device 3 si device 2 si device 1 so device 3 so device 2 so device 1 time spi _dasychain2. emf spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 24 rev. 1.0, 2007-12-18 5.4.2 daisy chain capability the spi of spider - TLE7232GS provid es daisy chain capability. in this configuration several devices are activated by the same cs signal mcs . the si line of one device is connected with the so line of another device (see figure 13 ), which builds a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the ma ster device provides the master clock mclk, which is connected to the sclk line of each device in the chain. figure 13 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out can be seen at so. after 16 sclk cycles, the data transfer for one device has been finished. in single chip configuration, the cs line must go high to make the device a ccept the transferred data. in daisy chain configuration the data shifted out at device #1 has been sh ifted in to device #2. when using three devices in daisy chain, three times 16 bits have to be shi fted through the devices. after that, the mcs line must go high (see figure 14 ). figure 14 data transfer in daisy chain configuration
cs sclk si t cs(lead) t cs( td ) t cs(lag) t scl k( h) t scl k( l ) t scl k( p) t si( su ) t si( h ) so t so( v) t so( d is) 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd spi timing. emf data sheet 25 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5.4.3 timing diagrams figure 15 timing diagram 5.4.4 electrical characteristics electrical characteristics: spi v dd = 4.5 v to 5.5 v, t j = -40 v dd = 5.0 v, t j = 25 pos. parameter symbol limit values unit conditions min. typ. max. power supply 5.4.1 power supply voltage for so buffer v vso 3.0 ? 5.5 v ? input characteristics (cs , sclk, si) 5.4.2 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) 0?1v? 5.4.3 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 2? v dd v? 5.4.4 l-input pull-up current through cs i cs(l) 10 20 50 v cs = 0 v 5.4.5 h-input pull-up current through cs i cs(h) 5?50 v cs = 2 v 5.4.6 l-input pull-down current through pin sclk si i sclk(l) i si(l) 5 5 ? ? 50 50 v sclk = 1 v v si = 1 v
spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 26 rev. 1.0, 2007-12-18 5.4.7 h-input pull-down current through pin sclk si i sclk(h) i si(h) 10 10 20 20 50 50 p a v sclk = 5 v v si = 5 v output characteristics (so) 5.4.8 l level output voltage v so(l) 0?0.4v i so = -2.5 ma 5.4.9 h level output voltage v so(h) ? 4.6 2.4 ? ? ? ? 5 3 ? i so = 2 ma v vso = 5 v v vso = 3 v 5.4.10 output trista te leakage current i so(off) -10 ? 10 p a v cs = v dd timings 5.4.11 serial clock frequency f sclk 0?5mhz? 5.4.12 serial clock period t sclk(p) 200 ? ? ns ? 5.4.13 serial clock high time t sclk(h) 50 ? ? ns ? 5.4.14 serial clock low time t sclk(l) 50 ? ? ns ? 5.4.15 enable lead time (falling cs to rising sclk) t sclk(lead) 250 ? ? ns ? 5.4.16 enable lag time (falling sclk to rising cs ) t sclk(lag) 250 ? ? ns ? 5.4.17 transfer delay time (rising cs to falling cs ) t cs(del) 250 ? ? ns ? 5.4.18 data setup time (required time si to falling sclk) t si(su) 20 ? ? ns ? 5.4.19 data hold time (falling sclk to si) t si(h) 20 ? ? ns ? 1) not subject to production test, specified by design. electrical characteristics: spi (cont?d) v dd = 4.5 v to 5.5 v, t j = -40 q c to 150 q c, all voltages with respect to ground , positive current flowing into pin (unless otherwise specified); typical values: v dd = 5.0 v, t j = 25 q c pos. parameter symbol limit values unit conditions min. typ. max.
field bits type description cmd addr data field bits type description chn (n = 7-0) data sheet 27 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics 5.4.5 spi protocol the spi protocol of the spider - TLE7232GS provides tw o types of registers. the control registers and the diagnosis registers. after power-on reset, all register bits set to default values. si reset value: xxxx h 1514131211109876543210 cmd 0 0 0 addr data 15:14 command 00 diagnosis only: the requested data is shifted out at so. this command does not change any register setting. 01 read register: th e register content of th e addressed register will be sent in the next frame. 10 reset registers: all registers are reset to their default values. 11 write register: the data of the si word will be written to the addressed register. 10:8 address pointer to register for read and write command 7:0 data data written to or read from register selected by address addr so standard diagnosis reset value: xxxx h 1514131211109876543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 (2n+1):2n standard diagnosis for channel n 00 short circuit to gnd 01 open load 10 overload, overtemperature 11 normal operation so second frame of read command reset value: xxxx h 1514131211109876543210 0 1 0 0 0 addr data
field bits type description addr data name w/ r addr 7 6 5 4 3 2 1 0 default 1) imcr bocr olcr otcr srcr sta ctl spi driver for enhanced relay control spider - TLE7232GS block description and electrical characteristics data sheet 28 rev. 1.0, 2007-12-18 note: reading a register needs two spi frames. in the first frame the rd command is sent. in the second frame the output at spi signal so will cont ain the requested information. a ne w command can be executed in the second frame. 5.4.6 register overview due to the default value of the mapping regist er the in3 is mapped to out3 after power up. 10:8 address pointer to register for read and write command 7:0 data data written to or read from register selected by address addr 1) the default values are set after reset. w/r 001 b map7 map6 map5 map4 map3 map2 map1 map0 08 h w/r 010 b bol7 bol6 bol5 bol4 bol3 bol2 bol1 bol0 00 h w/r 011 b ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 00 h w/r 100 b ovt7 ovt6 ovt5 ovt4 ovt3 ovt2 ovt1 ovt0 00 h w/r 101 b sle7 sle6 sle5 sle4 sle3 sle2 sle1 sle0 00 h r110 b out7 out6 out5 out4 out3 out2 out1 out0 00 h w/r 111 b out7 out6 out5 out4 out3 out2 out1 out0 00 h
tle7230/32gs v so out 0 out 1 out 2 out 3 gnd in 0 in 2 in 3 cs rst vreg tle4678g 13 2 7 3-5,10-12 6 8 1 14 9 w atchdog in w atchdog out reset out q wdo wdi rvcc dgnd reset adjust w atchdog adjust input r wa 100k ? c d 100nf c q 22 f v bat c i 100nf c xc2287 out 4 out 5 out 6 out 7 sclk si so v dd c s 100nf data sheet 29 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS application circuit 6 application circuit figure 16 application circuit
gps01214 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 3) jedec registration mo-137 variation ae 8.65 ?.1 0.65 0.25 2) m c 0.17 b 24x ?.05 a a index marking b (1.47) 1.75 max. 0.1 b seating plane ?.1 3.9 1) 0.35 x 45? 8? max. ?.25 0.64 ?.2 c 6 m 0.2 8? max. -0.1 0.2 0?...8? +0.06 0.19 8 ? max. c -0.1 0.2 0?...8? 1) spi driver for enhanced relay control spider - TLE7232GS package outlines data sheet 30 rev. 1.0, 2007-12-18 7 package outlines figure 17 pg-ssop-24-6 (plastic green shrink small outline package) green product (rohs compliant) for further information on alternativ e packages, please visit our website: . dimensions in mm to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. gree n products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020).
revision date changes rev. 1.0 data sheet 31 rev. 1.0, 2007-12-18 spi driver for enhanced relay control spider - TLE7232GS revision history 8 revision history 2007-12-18 layout completely updated (a4 page size) application circuit added nominal load current inserted (page 14) thermal resistance section (page 15) updated
edition 2007-12-18 published by infineon technologies ag 81726 munich, germany ? 2007 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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