november 2013 ?2011 fairchild semiconductor corporation FDMC7678 rev. c2 www.fairchildsemi.com 1 FDMC7678 n-channel power trench ? mosfet FDMC7678 n-channel power trench ? mosfet 30 v, 19.5 a, 5.3 m features ? max r ds(on) = 5.3 m at v gs = 10 v, i d = 17.5 a ? max r ds(on) = 6.8 m at v gs = 4.5 v, i d = 15.0 a ? high performance technology for extremely low r ds(on) ? termination is lead-free and rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced power trench ? process that has been especially tailored to mini mize the on-state resistance. this device is well suited for power management and load switching applications common in notebook computers and portable battery packs. application ? dc - dc buck converters ? notebook battery power management ? load switch in notebook g s s s d d d d 5 6 7 8 3 2 1 4 1 2 3 4 5 dd d d g s s s bottom top mlp 3.3x3.3 6 7 8 pin 1 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 30 v v gs gate to source voltage (note 3) 20 v i d drain current -continuous (package limited) t c = 25 c 19.5 a drain current -continuous (silicon limited) t c = 25 c 63 -continuous t a = 25 c (note 1a) 17.5 -pulsed 70 e as single pulse avalanche energy (note 4) 54 mj p d power dissipation t c = 25 c 31 w power dissipation t a = 25 c (note 1a) 2.3 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 4.0 c/w r ja thermal resistance, junction to ambient (note 1a) 53 device marking device package reel size tape width quantity FDMC7678 FDMC7678 mlp 3.3x3.3 13 ?? 12 mm 3000 units
www.fairchildsemi.com 2 ?2011 fairchild semiconductor corporation FDMC7678 rev. c2 FDMC7678 n-channel power trench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 21 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a i gss gate to source leakage current, forward v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 1.2 1.5 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 17.5 a 4.2 5.3 m v gs = 4.5 v, i d = 15.0 a 5.1 6.8 v gs = 10 v, i d = 17.5 a t j = 125 c 5.7 7.2 g fs forward transconductance v dd = 5 v, i d = 17.5 a 90 s c iss input capacitance v ds = 15 v, v gs = 0 v f = 1mhz 1810 2410 pf c oss output capacitance 620 820 pf c rss reverse transfer capacitance 75 110 pf r g gate resistance 0.7 2.5 t d(on) turn-on delay time v dd = 15 v, i d = 17.5 a v gs = 10 v, r gen = 6 10 19 ns t r rise time 410ns t d(off) turn-off delay time 26 41 ns t f fall time 310ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 15 v i d = 17.5 a 28 39 nc total gate charge v gs = 0 v to 4.5 v 14 19 nc q gs gate to source charge 4.4 nc q gd gate to drain ?miller? charge 3.9 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 1.9 a (note 2) 0.7 1.2 v v gs = 0 v, i s = 17.5 a (note 2) 0.8 1.2 t rr reverse recovery time i f = 17.5 a, di/dt = 100 a/ s 30 49 ns q rr reverse recovery charge 13 23 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0 %. 3. as an n-ch device, the negative v gs rating is for low duty cycle pulse occurence only. no continuous rating is implied. 4. e as of 54 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 19 a, v dd = 27 v, v gs = 10 v. a. 53 c/w when mounted on a 1 i n 2 p a d o f 2 o z c o p p e r b.125 c/w when mounted on a minimum pad of 2 oz copper
www.fairchildsemi.com 3 ?2011 fairchild semiconductor corporation FDMC7678 rev. c2 FDMC7678 n-channel power trench ? mosfet typical characteristics t j = 25c unless otherwise noted figure 1. 0.0 0.5 1.0 1.5 2.0 0 10 20 30 40 50 60 70 v gs = 3 v v gs = 3.5 v v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 6 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 10203040506070 0 1 2 3 4 v gs = 3 v v gs = 6 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 3.5 v v gs = 4.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 i d = 17.5 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 2 4 6 8 10 12 t j = 125 o c i d = 17.5 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.0 1.5 2.0 2.5 3.0 3.5 0 10 20 30 40 50 60 70 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 4 ?2011 fairchild semiconductor corporation FDMC7678 rev. c2 FDMC7678 n-channel power trench ? mosfet figure 7. 0 5 10 15 20 25 30 0 2 4 6 8 10 i d = 17.5 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v gate charge characteristics figure 8. 0.1 1 10 30 30 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 100 1 10 30 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 10 20 30 40 50 60 70 limited by package v gs = 4.5 v r t jc = 4.0 o c/w v gs = 10 v i d , drain current (a) t c , c ase temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 100 p s 10 ms 10 s 100 ms dc 1 s 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c figure 12. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 1000 2000 single pulse r t ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25c unless otherwise noted
www.fairchildsemi.com 5 ?2011 fairchild semiconductor corporation FDMC7678 rev. c2 FDMC7678 n-channel power trench ? mosfet figure 13. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.0005 0.001 0.01 0.1 1 2 d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25c unless otherwise noted
www.fairchildsemi.com 6 ?2011 fairchild semiconductor corporation FDMC7678 rev. c2 FDMC7678 n-channel power trench ? mosfet dimensional outlin e and pad layout b top view 0.10 c 0.10 c 2x 2x pin1 ident a ? ? keep out area (3.40) 2.37 0.45(4x) (1.70) 2.15 (0.65) 0.42(8x) 0.70(4x) 0.65 1.95 (0.40) 4 1 8 5 notes: a.except as noted, package conforms to jedec registration mo-240 variation ba.. b.dimensions are in millimeters. c.dimensions and tolerances per asme y14.5m,1994. d.seating plane is defined by terminal tips only e.body dimensions do not include mold flash protrusions nor gateburrs. f.flange dimensions include interterminal flash or protrusion. interterminal flash or protrusion shall not exceed 0.25mm per side. g.it is recommended to have no traces or via within the keep out area. h.drawing filename: mkt-mlp08trev3. i.general radii for all corners shall be 0.20mm max. j.fairchild semiconductor. 0.10 c a b 0.05 c bottom view 0.08 c 0.05 0.00 side view seating plane 0.10 c (0.20) 8 5 1.95 0.65 0.32 + 0.05 4 1 (8x) 2.27 + 0.05 0.45 + 0.05 (4x) (1.20) 0.45 + 0.05 (3x) 2.05 + 0.05 (0.40) ? 0 $ ; c 0.8max recommended land pattern a a
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