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rt8152c/d 1 ds8152c/d-00 july 2009 www.richtek.com single-phase pwm controller for cpu / gpu core power supply general description the rt8152c/d is a single phase pwm controller with integrated mosfet drivers. moreover, it is compliant with intel imvp6.5 voltage regulator specification to fulfill its mobile cpu core and render core voltage regulator requirements. the rt8152c/d adopts g-navp (green- native avp), which is a richtek's proprietary topology derived from finite dc gain compensator constant on-time mode, making it an easy-setting pwm controller meeting all intel avp (active voltage positioning) mobile cpu/ render requirements. the output voltage of the rt8152c/ d is set by 7-bit vid code. the built-in high accuracy dac converts the vid code ranging from 0v to 1.5v with 12.5mv per step. the system accuracy of the controller can reach 1.5%. the part supports vid on-the-fly and mode change on-the-fly functions that are fully compliant with imvp6.5 specification. it operates in single phase and diode emulation modes. it can reach up to 90% efficiency in different modes according to different loading conditions. the droop load-line can be easily programmed by setting the dc gain of the error amplifier. with proper compensation, the load transient can achieve optimized avp performance. this chip controls soft-start and output transition slew rate via a capacitor. it supports both dcr and sense-resistor current sensing. the rt8152c/d provides power good and thermal throttling output signals for imvp6.5 render core specification, and additional clock enabling for cpu core specification. it also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and thermal shutdown. the rt8152c/d is available in wqfn-32l 5x5 small foot print package. features z z z z z single phase pwm controller with integrated mosfet driver. z z z z z low-gain compensator with ccrcot topology (constant current ripple constant on time) z z z z z 7-bit dac z z z z z 0.8% dac accuracy z z z z z 1.5% or 11.5mv system accuracy z z z z z fixed v boot (for cpu core only) z z z z z differential remote voltage sensing z z z z z g-navp topology (green-native avp) z z z z z programmable output transition slew rate control z z z z z system thermal compensated avp z z z z z ringing free mode at light load condition z z z z z fast transient response z z z z z imvp6.5 compatible power management states z z z z z power good z z z z z clock enable output (for cpu core only) z z z z z thermal throttling z z z z z current monitor output z z z z z switching frequency up to 1mhz z z z z z ovp, uvp, ocp, otp, uvlo, nvp z z z z z 32-lead wqfn package z z z z z rohs compliant and halogen free applications z imvp6.5 cpu / render core voltage regulator z avp step-down converter z notebook / desktop computer / servers note : richtek green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ordering information package type qw : wqfn-32l 5x5 (w-type) operating temperature range g : green (halogen free with commer- cial standard) rt8152 vron power c : 1.05v d : 3.3v free datasheet http:///
rt8152c/d 2 ds8152c/d-00 july 2009 www.richtek.com typical application circuit pin configurations (top view) wqfn-32l 5x5 figure 1. cpu core voltage regulator ntc vron dprslpvr ocset boot pgnd phase ugate cm cmset vsen fb vid0 vid1 vid2 vid3 pgood pvdd lgate rgnd comp vid4 vcc gnd isen_n vid5 isen vid6 soft ton 33 gnd 24 23 22 21 1 2 3 4 10 11 12 13 31 30 29 28 20 19 5 6 9 32 14 27 18 7 15 26 16 25 17 8 vrtt clken v o u t v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 + 5 v 2 9 2 3 2 2 2 0 2 7 2 8 2 1 1 5 5 2 v i d 0 v i d 1 v i d 2 v i d 3 u g a t e i s e n _ n r t 8 1 5 2 c / d v i d 4 l g a t e p g n d 3 1 3 0 p v d d 2 4 1 7 v c c r g n d b o o t p g o o d 7 p h a s e o c s e t i s e n 1 6 r 1 1 p w r g d + 3 . 3 v l 1 v i n c 5 r 7 c 7 c 1 r 1 c 4 q 1 q 2 r 4 r 5 r 8 5 v t o 2 5 v r 6 c 6 d 1 c o u t c m s e t 1 1 1 2 c o m p 1 4 v s e n r 1 8 r 1 9 c 1 3 c 1 2 r 2 0 n t c 1 v o u t c 1 0 s o f t 8 9 r 1 7 r 1 6 r 1 5 n t c 2 v c c c p u v s s _ s n s r 2 2 d p r s l p v r 3 d p r s l p v r g n d 18, 33, exposed pad (33) c 9 1 9 c 2 c 3 t o n r 2 r 3 v i d 5 v i d 6 2 5 2 6 v i d 5 v i d 6 r 2 1 c p u v c c _ s n s r 1 3 1 3 f b c m r 1 2 c 1 1 c m 1 0 clken vrtt 6 32 r 1 0 r 9 v c c p clken vrtt r 1 4 1 n t c v r o n 4 v r o n c p u v s s _ s n s free datasheet http:///
rt8152c/d 3 ds8152c/d-00 july 2009 www.richtek.com functional pin description pin no. pin name pin function 1 ntc thermal detection input for vrtt circuit. connect this pin with a resistor divider from vcc using ntc on the top to set the thermal management threshold level. 2 ocset over current protection setting. connect a resistor voltage divider from vcc to ground, the joint of the resistor divider is connected to ocset pin, with a voltage vocset, to set the over current threshold i lim . 3 dprslpvr deeper sleep mode signal. 4 vron voltage regulator enabler. 5 pgood power good indicator. 6 clken inverted clock enable. pull high by a resistor for cpu core application. this open-drain pin is an output indicating the start of the pll locking of the clock chip. connect to gnd for render application. 7 vcc chip power. 8 soft soft-start. this pin provides soft-start function and slew rate controller. the feedback voltage of the converter follows the ramping voltage on the soft pin during soft-start and other voltage transitions according to different mode of operation and vid change. 9 rgnd return ground. this pin is the negative node of the differential remote voltage sensing. to be continued figure 2. render core voltage regulator v o u t v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 + 5 v 2 9 2 3 2 2 2 0 2 7 2 8 2 1 1 5 5 2 v i d 0 v i d 1 v i d 2 v i d 3 u g a t e i s e n _ n r t 8 1 5 2 c / d v i d 4 l g a t e p g n d 3 1 3 0 p v d d 2 4 1 7 v c c r g n d b o o t p g o o d 7 p h a s e o c s e t i s e n 1 6 r 1 1 p w r g d + 3 . 3 v l 1 v i n c 5 r 7 c 7 c 1 r 1 c 4 q 1 q 2 r 4 r 5 r 8 5 v t o 2 5 v r 6 c 6 d 1 c o u t c m s e t 1 1 1 2 c o m p 1 4 v s e n r 1 8 r 1 9 c 1 3 c 1 2 r 2 0 n t c 1 v o u t c 1 0 s o f t 8 9 r 1 7 r 1 6 r 1 5 n t c 2 v c c g p u v s s _ s n s r 2 2 d p r s l p v r 3 d p r s l p v r g n d 18, 33, exposed pad (33) c 9 1 9 c 2 c 3 t o n r 2 r 3 v i d 5 v i d 6 2 5 2 6 v i d 5 v i d 6 r 2 1 g p u v c c _ s n s r 1 3 1 3 f b c m r 1 2 c 1 1 c m 1 0 clken vrtt 6 32 r 9 v c c p vrtt r 1 4 1 n t c v r o n 4 v r o n gpu v ss_sns free datasheet http:///
rt8152c/d 4 ds8152c/d-00 july 2009 www.richtek.com pin no. pin name pin function 10 cm current monitor output. this pin output s a voltage proportional to the output current. 11 cmset current monitor output gain externally setting. connect this pin with one resistor to vsen while cm pin is connected to ground with one another resistor. in such way, current monitor output gain can be set by the ratio of these two resistors. 12 vsen positive voltage sensing pin. this pin is the positive node of the differential voltage sensing. 13 fb feedback. this is the negative input node of the error amplifier. 14 comp compensation. this pin is t he output node of the error amplifier. 15 isen_n negative input of the current sense. 16 isen positive input of the current sense. 17 ton connect this pin to vin with one resistor. 18, 33 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 19 pvdd driver power. 20 lgate lower gate drive. this pin drives the gate of the low-side mosfets. 21 pgnd driver ground. 22 phase this pin is return node of the high-side mosfet driver. connect this pin to the high-side mosfet sources together with the low-side mosfet drains and the inductor. 23 ugate upper gate drive. this pin drives the gate of the high-side mosfets. 24 boot bootstrap power input. this pin powers the high-side mosfet drivers. connect this pin to bootstrap capacitor. 25 to 31 vid6 to vid0 voltage id. dac voltage identification inputs for imvp6.5. the logic threshold is 30% of the vccp as the maximum value for low state and 70% of the vccp as the minimum value for the high state. 32 vrtt voltage regulator thermal throttling. this open-drain output pin w ill be pulled low when the preset temperature level is exceeded. free datasheet http:///
rt8152c/d 5 ds8152c/d-00 july 2009 www.richtek.com vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 0 0 0 0 0 0 1.5000v 0 0 0 0 0 0 1 1.4875v 0 0 0 0 0 1 0 1.4750v 0 0 0 0 0 1 1 1.4625v 0 0 0 0 1 0 0 1.4500v 0 0 0 0 1 0 1 1.4375v 0 0 0 0 1 1 0 1.4250v 0 0 0 0 1 1 1 1.4125v 0 0 0 1 0 0 0 1.4000v 0 0 0 1 0 0 1 1.3875v 0 0 0 1 0 1 0 1.3750v 0 0 0 1 0 1 1 1.3625v 0 0 0 1 1 0 0 1.3500v 0 0 0 1 1 0 1 1.3375v 0 0 0 1 1 1 0 1.3250v 0 0 0 1 1 1 1 1.3125v 0 0 1 0 0 0 0 1.3000v 0 0 1 0 0 0 1 1.2875v 0 0 1 0 0 1 0 1.2750v 0 0 1 0 0 1 1 1.2625v 0 0 1 0 1 0 0 1.2500v 0 0 1 0 1 0 1 1.2375v 0 0 1 0 1 1 0 1.2250v 0 0 1 0 1 1 1 1.2125v 0 0 1 1 0 0 0 1.2000v 0 0 1 1 0 0 1 1.1875v 0 0 1 1 0 1 0 1.1750v 0 0 1 1 0 1 1 1.1625v 0 0 1 1 1 0 0 1.1500v 0 0 1 1 1 0 1 1.1375v 0 0 1 1 1 1 0 1.1250v 0 0 1 1 1 1 1 1.1125v 0 1 0 0 0 0 0 1.1000v table 1. imvp6.5 vid code table vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 1 0 0 0 0 1 1.0875v 0 1 0 0 0 1 0 1.0750v 0 1 0 0 0 1 1 1.0625v 0 1 0 0 1 0 0 1.0500v 0 1 0 0 1 0 1 1.0375v 0 1 0 0 1 1 0 1.0250v 0 1 0 0 1 1 1 1.0125v 0 1 0 1 0 0 0 1.0000v 0 1 0 1 0 0 1 0.9875v 0 1 0 1 0 1 0 0.9750v 0 1 0 1 0 1 1 0.9625v 0 1 0 1 1 0 0 0.9500v 0 1 0 1 1 0 1 0.9375v 0 1 0 1 1 1 0 0.9250v 0 1 0 1 1 1 1 0.9125v 0 1 1 0 0 0 0 0.9000v 0 1 1 0 0 0 1 0.8875v 0 1 1 0 0 1 0 0.8750v 0 1 1 0 0 1 1 0.8625v 0 1 1 0 1 0 0 0.8500v 0 1 1 0 1 0 1 0.8375v 0 1 1 0 1 1 0 0.8250v 0 1 1 0 1 1 1 0.8125v 0 1 1 1 0 0 0 0.8000v 0 1 1 1 0 0 1 0.7875v 0 1 1 1 0 1 0 0.7750v 0 1 1 1 0 1 1 0.7625v 0 1 1 1 1 0 0 0.7500v 0 1 1 1 1 0 1 0.7375v 0 1 1 1 1 1 0 0.7250v 0 1 1 1 1 1 1 0.7125v 1 0 0 0 0 0 0 0.7000v 1 0 0 0 0 0 1 0.6875v to be continued free datasheet http:///
rt8152c/d 6 ds8152c/d-00 july 2009 www.richtek.com vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 0 0 0 0 1 0 0.6750v 1 0 0 0 0 1 1 0.6625v 1 0 0 0 1 0 0 0.6500v 1 0 0 0 1 0 1 0.6375v 1 0 0 0 1 1 0 0.6250v 1 0 0 0 1 1 1 0.6125v 1 0 0 1 0 0 0 0.6000v 1 0 0 1 0 0 1 0.5875v 1 0 0 1 0 1 0 0.5750v 1 0 0 1 0 1 1 0.5625v 1 0 0 1 1 0 0 0.5500v 1 0 0 1 1 0 1 0.5375v 1 0 0 1 1 1 0 0.5250v 1 0 0 1 1 1 1 0.5125v 1 0 1 0 0 0 0 0.5000v 1 0 1 0 0 0 1 0.4875v 1 0 1 0 0 1 0 0.4750v 1 0 1 0 0 1 1 0.4625v 1 0 1 0 1 0 0 0.4500v 1 0 1 0 1 0 1 0.4375v 1 0 1 0 1 1 0 0.4250v 1 0 1 0 1 1 1 0.4125v 1 0 1 1 0 0 0 0.4000v 1 0 1 1 0 0 1 0.3875v 1 0 1 1 0 1 0 0.3750v 1 0 1 1 0 1 1 0.3625v 1 0 1 1 1 0 0 0.3500v 1 0 1 1 1 0 1 0.3375v 1 0 1 1 1 1 0 0.3250v 1 0 1 1 1 1 1 0.3125v 1 1 0 0 0 0 0 0.3000v vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 1 0 0 0 0 1 0.2875v 1 1 0 0 0 1 0 0.2750v 1 1 0 0 0 1 1 0.2625v 1 1 0 0 1 0 0 0.2500v 1 1 0 0 1 0 1 0.2375v 1 1 0 0 1 1 0 0.2250v 1 1 0 0 1 1 1 0.2125v 1 1 0 1 0 0 0 0.2000v 1 1 0 1 0 0 1 0.1875v 1 1 0 1 0 1 0 0.1750v 1 1 0 1 0 1 1 0.1625v 1 1 0 1 1 0 0 0.1500v 1 1 0 1 1 0 1 0.1375v 1 1 0 1 1 1 0 0.1250v 1 1 0 1 1 1 1 0.1125v 1 1 1 0 0 0 0 0.1000v 1 1 1 0 0 0 1 0.0875v 1 1 1 0 0 1 0 0.0750v 1 1 1 0 0 1 1 0.0625v 1 1 1 0 1 0 0 0.0500v 1 1 1 0 1 0 1 0.0375v 1 1 1 0 1 1 0 0.0250v 1 1 1 0 1 1 1 0.0125v 1 1 1 1 0 0 0 0.0000v 1 1 1 1 0 0 1 0.0000v 1 1 1 1 0 1 0 0.0000v 1 1 1 1 0 1 1 0.0000v 1 1 1 1 1 0 0 0.0000v 1 1 1 1 1 0 1 0.0000v 1 1 1 1 1 1 0 0.0000v 1 1 1 1 1 1 1 0.0000v free datasheet http:///
rt8152c/d 7 ds8152c/d-00 july 2009 www.richtek.com function block diagram comp rgnd soft ovp trip point vid1 vid3 vid4 vid5 vid0 vid2 fb pgood vcc gnd error amp ocp setting soft start nvp trip point power on reset & central logic vsen vron ocset ntc vid6 mode selection dprslpvr v boot uvp trip point otp + - vcc mux dac + - + - + - + - + - isen_n pwmcp driver logic control pgnd lgate pvdd phase ugate boot isen cm - + - + 10 c l k e n v r t t cm cmset ccrcot on-time generator ton fb mode selection vdac offset cancellation free datasheet http:///
rt8152c/d 8 ds8152c/d-00 july 2009 www.richtek.com electrical characteristics to be continued (v cc = 5v, t a = 25 c, unless otherwise specified) recommended operating conditions (note 3) z supply voltage, v cc ----------------------------------------------------------------------------------------- 4.5v to 5.5v z battery voltage, v in ----------------------------------------------------------------------------------------- 5v to 25v z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vcc to gnd --------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z rgnd, pgnd to gnd --------------------------------------------------------------------------------------- ? 0.3v to 0.3v z vidx to gnd --------------------------------------------------------------------------------------------------- ? 0.3v to v cc + 0.3v z dprslpvr, vron to gnd ------------------------------------------------------------------------------- ? 0.3v to v cc + 0.3v z pgood, clken, vrtt to gnd --------------------------------------------- ----------------------------- ? 0.3v to v cc + 0.3v z vsen, fb, comp, soft, ocset, cm, cmset, ntc to gnd ----------------------------------- ? 0.3v to v cc + 0.3v z isen, isen_n to gnd -------------------------------------------------------------------------------------- ? 0.3v to v cc + 0.3v z pvdd to pgnd ----------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z lgate to pgnd dc ---------------------------------------------------------------------------------------------------------------- ? 0.3v to pvdd+ 0.3v <20ns ----------------------------------------------------------------------------------------------------------- ? 2.5v to 7.5v z phase to pgnd dc ---------------------------------------------------------------------------------------------------------------- ? 0.3v to 28v <20ns ----------------------------------------------------------------------------------------------------------- ? 8v to 38v z boot to phase --------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z ugate to phase dc ---------------------------------------------------------------------------------------------------------------- ? 0.3v to boot ? phase <20ns ----------------------------------------------------------------------------------------------------------- ? 5v to 7.5v z ton to gnd --------------------------------------------------------------------------------------------------- ? 0.3v to 28v z power dissipation, p d @ t a = 25 c wqfn ? 32l 5x5 ----------------------------------------------------------------------------------------------- 2.778w z package thermal resistance (note 4) wqfn ? 32l 5x5, ja ----------------------------------------------------------------------------------------- 36 c/w wqfn ? 32l 5x5, jc ----------------------------------------------------------------------------------------- 7 c/w z junction temperature ---------------------------------------------------------------------------------------- 150 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z esd susceptibility (note 2) hbm (human body mode) --------------------------------------------------------------------------------- 2kv mm (ma chine mode) ----------------------------------------------------------------------------------------- 200v parameter symbol test conditions min typ max unit supply input supply current i vcc + i pvdd r ton = 130k, v ron = 3.3v, no loading current -- -- 10 ma free datasheet http:///
rt8152c/d 9 ds8152c/d-00 july 2009 www.richtek.com to be continued parameter symbol test conditions min typ max u nit shutdown current i vcc + i pvdd v ron = 0v -- -- 5 a soft start/slew rate control (based on 10nf c ss ) soft-start / soft-shutdown i ss1 soft = 1.5v -- 20 -- a normal vid change slew current i ss2 soft = 1.5v 40 50 60 a deeper sleep exit/vid change slew current i ss3 for render mode only, soft = 1.5v 80 100 120 a reference and dac v dac = 0.7500 ? 1.5000 (no load, active mode ) ? 0.8 0 0.8 %vid dc accuracy v fb v dac = 0.5000 ? 0.7500 ? 7.5 0 7.5 mv rt8152c 1.089 1.1 1.111 boot voltage v boot RT8152D 1.188 1.2 1.212 v error amplifier dc gain r l = 47k (note 5) 70 80 -- db gain-bandwidth product gbw c load = 5pf (note 5) -- 10 -- mhz slew rate sr comp c load = 10pf (gain = ? 4, r f = 47k, v ou t = 0.5v ? 3v) -- 5 -- v/ s output voltage range v comp r l = 47k 0.5 -- 3.6 v maximum source current v comp = 2v 200 250 -- a maximum sink current i outea_comp v comp = 2v -- 20 -- ma current sense amplifier input offset voltage v os cs i sen = i sen_n = 1.5v ? 1 -- 1 mv impedance at neg. input r isen_n i sen_n = 1.5v 1 -- -- m impedance at pos input r isen i sen = 1.5v 1 -- -- m dc gain -- 10 -- v/v input range v isen_in v dac = 1.1v, v isen_in = i sen - i sen_n ? 50 -- 80 mv ton setting ton pin output voltage v to n r ton = 80k, v ton = v dac = v boot ? 5 0 5 % on-time setting t on i rton = 80 a, v ton = v dac = v boot -- 350 -- ns r ton current range i rton v to n = v dac = v boot 25 -- 280 a mi ni mum off time t off i rton = 80 a, v dac = v boot 250 -- 500 ns protection under voltage lock-out threshol d v uvlo falling edge, 80mv hysteresis 3.9 4.1 4.3 v absolute over voltage protection threshold v ova bs (respect to 1.5v, +/- 50mv) 1.45 1.5 1.55 v relative over voltage protection threshold v ov (respect to v dac , +/- 50mv) 250 300 350 mv free datasheet http:///
rt8152c/d 10 ds8152c/d-00 july 2009 www.richtek.com to be continued parameter symbol test conditions min typ max unit under voltage protection threshold v uv measured at vsen respect to unloaded output voltage (uov) (for 0.8 < uov < 1.5) ? 450 ? 400 ? 350 mv negative voltage protection threshold v nv measured at vsen respect to gnd ? 100 -- -- mv current limit threshold voltage v ili m v isen ? v isen _n = v ili m , v ocset = 2v, 40 x v ili m = v ocset 46.5 50 53.5 mv thermal shutdown threshold t sd typical hysteresis is 10c -- 160 -- c logic inputs vron threshold v ih rt8152c respect to 1.05v, 70% 0.735 -- -- v RT8152D respect to 3.3v, 70% 2.31 -- -- v il rt8152c respect to 1.05v, 30% -- -- 0.315 RT8152D respect to 3.3v, 30% -- -- 0.99 leakage current of vron ? 1 -- 1 a dac (vid0 ? vid6) and dprslpvr v ih respect to 1.05v, 70% 0.77 -- -- v v il respect to 1.05v, 30% -- -- 0.33 v leakage current of dac (vid0 ? vid6) and dprslpvr ? 1 -- 1 a power good pgood threshold v th_pgood cpu core : vsen ? v boot -- ? 100 -- mv render : vsen ? v dac -- ? 100 -- pgood low voltage v pgood i pgood = 4ma -- -- 0.4 v pgood delay t pg ood cpu core, clken low to pgood high 3 -- 20 ms render mode vron high to pgood hi g h 3 -- 20 ms clock enable clken low voltage v clk en for cpu core only, i clken = 4ma -- -- 0.4 v thermal throttling thermal throttling threshold v ot measure at ntc respect to v cc -- 8 0 -- %v dd thermal throttling threshold -h y steresis v ot_hy at v cc = 5 v -- 23 0 -- mv vrt t output voltage v vrtt i vrtt = 40ma -- -- 0.4 v current monitor current monitor output voltage in operating range v dac = 0.9v, v rcmset = 0.82v, r cm = 7 .5k, r cmset = 1.5k 770 800 830 mv current monitor maximum out p ut volta g e -- -- 1.1 5 v free datasheet http:///
rt8152c/d 11 ds8152c/d-00 july 2009 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution is recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the wqfn package. note 5. guaranteed by design. parameter symbol test conditions min typ max u nit gate driver upper driver source r ugatesr v boot ? v ph ase = 5v v boot ? v ugate = 1v -- 0.7 -- upper driver sink r ugatesk v ugate = 1v -- 0.6 -- lower driver source r lgatesr v pvdd = 5v, v pvdd ? v lgate = 1v -- 0.75 -- lower driver sink r lgatesk v lgate = 1v -- 0.5 -- upper driver source/sink current i ugate v boot ? v ph ase = 5v v ugate = 2.5v -- 3 -- a lower driver source current i lgatesr v lgate = 2.5v -- 3 -- a lower driver sink current i lgatesk v lgate = 2.5v -- 5 -- a internal boot charging switch on-resistance r boot pvdd to boot -- 30 -- free datasheet http:///
rt8152c/d 12 ds8152c/d-00 july 2009 www.richtek.com typical operating characteristics v in = 12.6v, r ton = 150 , l = 0.36 h, c out = 330 f, no load, t a = 25 c, unless otherwise specified. ccm efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 3 6 9 12 15 18 21 24 27 30 load current (a) efficiency (%) vid = 1.15v, dprslpvr = low v in = 8v v in = 12v v in = 19v ccm vcc_sense vs. load current 1.04 1.06 1.08 1.10 1.12 1.14 1.16 0 3 6 9 12 15 18 21 24 27 30 load current ( a ) vcc_sense (v) vid = 1.15v, dprslpvr = low v in = 8v v in = 12v v in = 19v v cm vs. load current 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 5 10 15 20 25 30 load current (a) v cm (v) vid = 0.9375v, dprslpvr = low v in = 8v v in = 12v v in = 19v rfm efficiency vs. load current 50 55 60 65 70 75 80 85 90 95 100 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 load current (a) efficiency (%) vid = 0.85v, dprslpvr = high v in = 8v v in = 12v v in = 19v ccm vcc_sense vs. load current 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 0 3 6 9 12 15 18 21 24 27 30 load current (a) vcc_sense (v) vid = 0.9375v, dprslpvr = low v in = 8v v in = 12v v in = 19v ccm efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 3 6 9 12 15 18 21 24 27 30 load current (a) efficiency (%) vid = 0.9375v, dprslpvr = low v in = 8v v in = 12v v in = 19v free datasheet http:///
rt8152c/d 13 ds8152c/d-00 july 2009 www.richtek.com cpu mode power on vcc_sense (1v/div) time (1ms/div) pgood (5v/div) vron (5v/div) vid = 0.9375v, clken pull high to 3.3v clken (5v/div) render mode power on vcc_sense (1v/div) time (1ms/div) pgood (5v/div) vron (5v/div) clken (5v/div) vid = 0.9375v, clken pull low to gnd ccm vid change down vcc_sense (100mv/div) time (20 s/div) ugate (20v/div) lgate (5v/div) vid change from 0.9375v to 0.85v vid0 (5v/div) cpu mode power down vcc_sense (1v/div) time (100 s/div) pgood (5v/div) vron (5v/div) vid = 0.9375v, clken pull high to 3.3v clken (5v/div) cpu-rfm vid change down vcc_sense (100mv/div) time (20 s/div) ugate (20v/div) lgate (5v/div) vid change from 0.9375v to 0.85v clken pull high to 3.3v vid0 (5v/div) clken pull high to 3.3v ccm vid change up vcc_sense (100mv/div) time (20 s/div) ugate (20v/div) lgate (5v/div) vid change from 0.85v to 0.9375v vid0 (5v/div) clken pull high to 3.3v free datasheet http:///
rt8152c/d 14 ds8152c/d-00 july 2009 www.richtek.com ccm load transient response vcc_sense (50mv/div) time (10 s/div) ugate (20v/div) lgate (5v/div) vid = 0.9375v, i load = 28a to 5a clken pull high to 3.3v (cpu) dpslpvr = high over current protection vcc_sense (1v/div) time (10 s/div) phase (10v/div) pwrgd (2v/div) i load (20a/div) clken pull high to 3.3v (cpu), dpslpvr = low c4 entry / exit with vid change vcc_sense (100mv/div) time (40 s/div) vid0 (5v/div) dprslpvr (5v/div) dpslpvr = high i load-dprslpvr = 1a, i load-ccm = 21a vid = 0.9375v and 0.85v, clken pull high to 3.3v i load (40a/div) over voltage protection vcc_sense (1v/div) time (10 s/div) lgate (10v/div) pwrgd (2v/div) clken pull high to 3.3v (cpu), dpslpvr = low ugate (20v/div) under voltage protection vcc_sense (1v/div) time (10 s/div) lgate (10v/div) pwrgd (2v/div) clken pull high to 3.3v (cpu), dpslpvr = low ugate (20v/div) ccm load transient response vcc_sense (50mv/div) time (10 s/div) ugate (20v/div) lgate (5v/div) vid = 0.9375v, i load = 5a to 28a clken pull high to 3.3v (cpu) dpslpvr = low free datasheet http:///
rt8152c/d 15 ds8152c/d-00 july 2009 www.richtek.com application information the rt8152c/d is a single-phase pwm controller with embedded gate driver. it is compliant with intel imvp6.5 voltage regulator specification to fulfill its mobile cpu and render voltage regulator power supply requirement. inductor current are continuously sensed for loop control, droop tuning, and over-current protection. the 7-bit vid dac and a low offset differential amplifier allow the controller to maintain high regulating accuracy to meet intel?s imvp6.5 specification. design tool to help users to reduce the efforts and errors caused by manual calculations using the design concept below, a user-friendly design tool is now available on request. this design tool calculates all necessary design parameters by entering user's requirements. please contact richtek's representatives for details. operation modes table 2 shows the rt8152c/d operation modes. when vron is enable (=1), and within 10 s the rt8152c/d will detect the clken to determine which operation mode is applied. if the clken is low, the rt8152c/d will operate in render core voltage regulator mode. if the clken is high, the ic will operate in cpu core voltage regulator mode. dprslpvr determines the operation mode of the controller operation in ccm or rfm. the controller enters rfm (ring free mode) when dprslpvr = 1 and enters ccm when dprslpvr = 0. table 2. control signal truth table for operation modes of the rt8152c/d clken dprslpvr operation mode 0 render ccm 0 (gnd) 1 render rfm 0 cpu ccm 1 (pull high) 1 cpu rfm differential remote sense connection the rt8152c/d includes differential, remote-sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes and socket contacts. cpu contains on-die sense pins v cc_sense and v ss_sense . connect rgnd to v ss_sense . connect fb to v cc_sense with a resistor to build the negative input path of the error amplifier. connect vsen to v cc_sense for clken, pgood, ovp, and uvp detection. the 7 bit vid dac and the precision voltage reference are referred to rgnd for accurate remote sensing. current sense setting the rt8152c/d is continuously sensing the inductor current. therefore, the controller can be less noise sensitive. low offset amplifiers are used for loop control and over current detection. the internal current sense amplifier gain (a i ) is fixed to be 10. the isen and isen_n denote the positive and negative input of the current sense amplifier. users can either use a current-sense resistor or the inductor's dcr for current sensing. using inductor's dcr allows higher efficiency as shown in figure 3. to let x x l rc dcr = (1) x 0.36uh r3.6k 1m 1 0 0 n f == ? (2) then the transient performance will be optimum. for example, chose l = 0.36uh with 1m dcr and c x = 100nf, yields for r x : figure 3. lossless inductor current sensing phase isen isen_n v out l dcr r x c x + v x - free datasheet http:///
rt8152c/d 16 ds8152c/d-00 july 2009 www.richtek.com considering the inductance tolerance, the resistor r x has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, r x is chosen too small. vice versa, with a resistance too large, the output voltage transient has only a small initial dip and the recovery is too fast causing a ring-back. using current-sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. considering the equivalent inductance (l esl ) of the current- sense resistor, a rc filter is recommended. the rc filter calculation method is similar to the above-mentioned inductor dcr sensing method. loop control the rt8152c/d adopts richtek's proprietary g-navp tm topology. g-navp tm is based on the finite-gain current mode with ccrcot (constant current ripple constant on time) topology. the output voltage, v out , will decrease with increasing output load current. the control loop consists of pwm modulator with power stage, current sense amplifier and error amplifier as shown in figure 4. figure 4. simplified schematic for droop and remote sense in ccm the hs_fet on-time is determined by ccrcot on-time generator. when load current increases, v cs increases, the steady state comp voltage also increases and makes the v out decrease, achieving avp. a near-dc offset cancellation is added to the output of ea to cancel the inherent output offset of finite-gain current mode controller. in rfm, hs_fet is turned on with constant t on when v cs is lower than v comp2 . once the hs_fet is turned off, ls_fet is turned on automatically. by ringing-free technique, the ls_fet allows only partial of negative current when the inductor free-wheeling current reaches negative. the switching frequency will be proportionately reduced, thus the conduction and switching losses will be greatly reduced. output voltage droop setting (with temperature compensation) it's very easy to achieve the active voltage positioning (avp) by properly setting the error amplifier gain due to the native droop characteristics. the target is to have v out = v dac ? i load x r droop (3) , then solving the switching condition v comp2 = v cs in figure 4 yields the desired error amplifier gain as i sense v droop ar r2 a r1 r == (4) where a i is the internal current sense amplifier gain. r sense is the current sense resistor. if no external sense resistor present, it is the dcr of the inductor. r droop is the resistive slope value of the converter output and is the desired static output impedance. figure 5. error amplifier gain (av) influence on v out a v1 a v2 a v2 > a v1 v out load current 0 v out ccrcot pwm logic ugate lgate + - isen isen_n ai + - cmp v cs comp2 v in rt8152c/d hs_fet ls_fet l r x c x c ea v cc_sense - + v ss_sense fb soft rgnd comp c2 c1 r2 r1 c soft vdac + - offset cancellation free datasheet http:///
rt8152c/d 17 ds8152c/d-00 july 2009 www.richtek.com since the dcr of inductor is highly temperature dependent, it affects the output accuracy at hot conditions. temperature compensation is recommended for the lossless inductor dcr current-sense method. figure 6 shows a simple but effective way of compensating the temperature variations of the sense resistor using an ntc thermistor placed in the feedback path. figure 6. loop setting with temperature compensation usually, r1a is set to equal r ntc (25 o c). r1b is selected to linearize the ntc's temperature characteristic. for a given ntc, design is to get r1b and r2 and then c1 and c2. according to (4), to compensate the temperature variations of the sense resistor, the error amplifier gain (av) should have the same temperature coefficient with r sense . hence v, hot sense, hot v, cold sense, cold ar ar = (5) fr om (4), we can have av at any temperature (t) as v, t ntc, t r2 a r1a // r r1b = + (6) ( ) ( ) { } 11 t+273 298 ntc, t ntc, 25 rr e ?? ? ?? ?? = (7) the standard formula for the resistance of ntc thermistor as a function of temperature is given by : where r ntc, 25 is the thermistor's nominal resistance at room temperature, (beta) is the thermistor's material constant in kelvins, and t is the thermistor's actual temperature in celsius. to calculate dcr value at different temperature can use equation as below : dcr t = dcr 25 x [1+0.00393 x (t ? 25)] (8) where the 0.00393 is the temperature coefficient of the copper. for a given ntc thermistor, solving (6) at room temperature (25 c) yields r2 = a v, 2 5 x (r1b + r1a // r ntc, 25 ) (9) where a v, 2 5 is the error amplifier gain at room temperature and can be obtained from (4). r1b can be obtained by substituting (9) to (5), sense, hot ntc, hot ntc, cold sense, cold sense, hot sense, cold r1b r (r1a // r ) (r1a // r ) r r 1 r = ? ?? ? ?? ?? (10) loop compensation optimized compensation of the rt8152c/d allows for best possible load step response of the regulator's output. a compensator with one pole and one zero is adequate for a proper compensation. figure 4 shows the compensation circuit. prior design procedure shows how to decide the resistive feedback components of error amplifier gain, the c1 and c2 must be calculated for the compensation. the target is to achieve the constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : p c 1 f 2cr = (11) where c is the capacitance of output capacitor, and r c is the esr of output capacitor. c2 can be calculated as follows : c cr c2 r2 = (12) (13) () ntc, 25 sw 1 c1 r1b r1a // r f = + the zero of compensator has to be placed at half of the switching frequency to filter the switching-related noise. such that, ton setting high frequency operation optimizes the application for the smaller component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at the expense of component size and board space.figure 5 v cc_sense - + v ss_sense fb soft rgnd comp rt8152c/d c2 c1 r2 r1b c soft ea r1a ntc + - vdac free datasheet http:///
rt8152c/d 18 ds8152c/d-00 july 2009 www.richtek.com shows the on-time setting circuit. connect a resistor (r ton ) between vin and ton to set the on-time of ugate: (14) 12 ton on in 14.5 10 r 2 t (v vdac) ? = ? where t on is ugate turn on period, v in is input voltage of converter, vdac is dac voltage. on-time translate only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in external hs-fet. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in ccm (dprslpvr = 0), and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the phase goes high earlier than normal, extending the on-time by a period equal to the hs-fet rising dead time. for better efficiency of the given load range, the maximum switching frequency is suggested to be : (15) s(max) on hs-delay (max) load(max) on _ ls-fet l droop (max) load(max) on _ ls-fet on _ hs-fet 1 f tt vdac i r dcr r vin i r r = ? ?? + +? ?? ?? + ? ?? where ` fs max is the maximum switching frequency ` t hs- delay is the turn on delay of hs-fet ` vdac (max) is the maximum vdac of application ` vin max is the maximum application input voltage ` i load(max) is the maximum load of application ` r on_ls-fet is the low-side fet r ds(on) ` r on_hs-fet is the high-side fet r ds(on) ` dcr l is the inductor dcr ` r droop is the load line setting figure 7. on-time setting with rc filter soft-start and mode transition slew rates the rt8152c/d uses 3 slew rates for various modes of operation. the three slew rates are internally determined by commanding one of three bi-directional current sources (i ss ) on to the soft pin. the 7 bit vid dac and the precision voltage reference are referred to rgnd for accurate remote sensing. hence, connect a capacitor (c soft ) from soft pin to rgnd for controlling the slew rate as shown in figure 6. the voltage (v soft ) on the soft pin is the reference voltage of the error amplifier and is, therefore, the commanded system voltage. the first current is typically 20 a used to charge or discharge the c soft during soft-start, and soft-shutdown. the second current is typically 50 a used during other voltage transitions, including vid change and transitions between operation modes. the third current is typically 100 a used during render rfm with vid change up transitions. the imvp-6.5 specification specifies the critical timing associated with regulating the output voltage. the symbol, slewrate, as given in the imvp-6.5 specification will determine the choice of the soft capacitor, c soft, by the following equation : (16) ss soft i c slewrate = ccrcot on-time generator ton v in r ton r1 c1 vdac on-time power-up sequence with the controller's vcc voltage rises above the por threshold (typ. 4.3v), the power-up sequence begins when vron goes high. if clken = 1 (pull high), the rt8152c/d will enter cpu mode power-up sequence. if the clken = 0 (connect to gnd), the controller will enter render mode power-up sequence. after the rt8152c/d enters cpu mode, vsen starts ramping up to v boot within 1ms. the slew rate during power-up is 20 a/c soft . the rt8152c/d pulls clken low after vsen gets across v boot ? 0.1v for 73 s. right after clken goes low, vsen starts ramping to first vdac value. after clken goes low for approximately 4.7ms, pgood is asserted high. dprslpvr are valid right after pgood is asserted. uvp is masked as long as vsen is less than v boot ? 0.1v. free datasheet http:///
rt8152c/d 19 ds8152c/d-00 july 2009 www.richtek.com figure 8. cpu mode timing diagram for power-up and power-down after the rt8152c/d enters render mode, vsen starts ramping up to vdac within 1ms. the slew rate during power-up is 20 a/c soft . pgood is asserted high after vsen exceeds vdac ? 100mv for 4.77ms (typ.). dprslpvr are valid right after pgood is asserted. uvp is masked as long as vsen is less than vdac ? 100mv. figure 9. render mode timing diagram for power-up and power-down vron vcc 4.3v 4.1v vid valid xx xx vsen pgood 73us typ. 4.7ms typ. por 0.2v v boot v boot - 0.1v dprslpvr valid xx xx pwm dprslpvr defined ccm pull down ccm hi-z clken vron vcc 4.3v 4.1v vid valid xx xx vsen pgood 4.77ms typ. por 0.2v vdac vdac-100mv dprslpvr valid xx xx pwm dprslpvr defined ccm pull down ccm hi-z free datasheet http:///
rt8152c/d 20 ds8152c/d-00 july 2009 www.richtek.com r equ, t = r1a // r ntc, t (23) power-down when vron goes low, the rt8152c/d enters low-power shutdown mode. pgood is pulled low immediately and the v soft ramps down with slew rate of 20 a/c soft . vsen also ramps down following v soft . after v vsen is lower than 200mv, the rt8152c/d turns off high-side fets and low- side fets. an internal discharge resistor at vsen will be enabled and the analog part will be turned off. deeper sleep mode transitions after dprslpvr goes high, the rt8152c/d enters deeper sleep mode operation. if the vids are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. the internal target v soft still ramps as before, and uvp, ocp and ovp are masked for 73 s. over current protection setting the rt8152c/d compares a programmable current limit set point to the voltage from the current sense amplifier output for over current protection (ocp). the voltage applied to ocset pin defines the desired current limit threshold i lim : v ocset = 40 x i lim x r sense (17) connect a resistor voltage divider from vcc to gnd, the joint of the resistor divider is connected to ocset pin as shown in figure 10. for a given r oc2 , then (18) cc oc1 oc2 ocset v rr 1 v ?? = ? ?? ?? figure 10. ocp setting without temperature compensation ocset v cc r oc1 r oc2 rt8152c/d provides current limit function and over current protection. the current limit function is trggered when inductor current exceeds the current limit threshold i lim defined by v ocset . when current limit function is tripped, high-side mosfet will be forced off until the over current condition is cleared. figure 11. ocp setting with temperature compensation ocset v cc r oc1b r oc2 r oc1a ntc ocset, hot sense, hot ocset, cold sense, cold vr vr = (19) generally, the r oc1a must be selected to be equal to thermistor's nominal resistance at room temperature. ideally, v ocset has same temperature coefficient with r sense (inductor dcr): (20) oc2 equ, hot equ, cold equ, 25 cc ocset, 25 r rr (1)r v (1 ) v = ? + ? ? (21) oc1b oc2 equ, hot equ, cold r (1)r r r (1 ) = ? + ? ? where sense, hot 25 hot sense, cold 25 cold r dcr [1 0.00393 (t 25)] r dcr [1 0.00393 (t 25)] = + ? = + ? (22) if the current limit function is triggered for 15 switching cycles, ocp will be tripped. once ocp is tripped, both high-side and low-side mosfet will be turn off, and the internal discharge resistor at the vsen pin will be enabled to discharge output capacitors. ocp is a latched protection, it can only be reset by cycling vron or vcc. if inductor dcr is used as current sense component, then temperature compensation is recommended for proper protection under all conditions. figure 11 shows a typical ocp setting with temperature compensation. free datasheet http:///
rt8152c/d 21 ds8152c/d-00 july 2009 www.richtek.com figure 12. thermal throttling setting principle ntc v cc ntc r tt + - + 0.8 x v cc vrtt cmp for example, the following design parameters are given : dcr = 1m , v cc = 5v, i l,ripple = 9a r oc1a = r ntc, 25 = 10k , ntc = 3450 for ? 20 c to 100 c operation range, to set ocp trip current i trip = 28a lim ocset, 25 9a i 28a 32.5a 2 v 40 33a 1m 1.297v =+= = = r ntc, ? 20 c = 78.4k , r ntc,100 c = 0.98k r sense,-20 c = 0.82m , r sense,100 c = 1.29m r oc2 = 4.7k , r oc1b = 8.46 k over-voltage protection (ovp) the ovp circuit is triggered under two conditions: ` condition 1 : when v vsen exceeds 1.52v. ` condition 2 : when v vsen exceeds v dac by 300mv (typ.). if either condition is valid, the rt8152c/d latches the lgate = 1 and ugate = 0 as crowbar to the output voltage of vr. turn on all ls_fets can lead to very large reverse inductor current and potentially result in negative output voltage of vr. to prevent the cpu from damaging by negative voltage. the rt8152c/d turns off all ls_fets when v vsen falls below -100mv. under-voltage protection (uvp) if v vsen is lower than v dac by 400mv (typ.) a uvp fault will be tripped. once uvp is tripped, both high-side and low-side mosfet will be turnde off, and the internal discharge resistor at vsen pin will be enabled. uvp is a latched protection, it can only be reset by cycling vron or vcc. negative voltage protection (nvp) during the state that v vsen is lower than -100mv, the controller will force lgate = 0 and ugate = 0 for preventing negative voltage. once v vsen recovers to be higher than 0v, nvp will be suspended and lgate = 1 will be enabled again. ? over-temperature protection (otp) over-temperature protection prevents the vr from damaging. otp is considered to be the final protection stage against overheating of the vr. the thermal throttling vrtt shall be set to be asserted prior to otp to manage the vr power. when this measure was insufficient to keep the die temperature of the controller below the otp threshold, otp will be asserted and latches. the die temperature of the controller is monitored internally by a temperature sensor. as a result of otp triggering, a soft shutdown will be launched and v vsen will be monitored. when v vsen is less than 200mv, the driver remains in high impedance state and the discharging resistor at vsen pin will be enabled. a reset can be executed by cycling vcc or vron. thermal throttling control intel imvp-6.5 technology supports thermal throttling of the processor to prevent catastrophic thermal damage. the rt8152c/d includes a thermal monitoring circuit to detect an exceeded user-defined temperature on a vr point. the thermal monitoring circuit senses the voltage change across ntc pin. figure 12 shows the principle of setting the temperature threshold. connect an external resistor divider between vcc and gnd. this divider uses a negative temperature coefficient (ntc) thermistor and a resistor. the joint of the resistor divider is connected to the ntc pin in order to generate a voltage that is inversely proportional to temperature. the rt8152c/d pulls vrtt low if the voltage on the ntc pin is greater than 0.8 x v cc . the internal vrtt comparator has a hysteresis of 200mv (typ.) to prevent high frequency vrtt oscillation when the temperature is near the setting point. the minimum assertion/de-assertion time for vrtt toggling is 1.6ms (typ.). free datasheet http:///
rt8152c/d 22 ds8152c/d-00 july 2009 www.richtek.com users can use the same ntc thermistor for both thermal- throttling and current limit setting as shown in figure 13. just divide the r oc1b into r tta and r ttb , and write the v ntc equation at thermal-throttling temperature tt c : r tta + r ttb = r oc1b (24) oc2 ttb cc cc oc2 oc1b oc1a ntc, tt rr v0.8v rr r//r + = ++ (25) solving (27) and (28) for r tta and r ttb as: r ttb = 4 x (r oc1a // r ntc, tt ) ? r oc2 (26) r tta = r oc1b ? r ttb (27) figure 13. using single ntc thermistor for thermal- throttling and current limit setting ntc + - + 0.8 x v cc vrtt cmp v cc r tta r ttb r oc1a ntc r oc2 ocset current monitor figure 14 shows the current monitor setting principle. current monitor needs to meet imvp6.5 specification, the rt8152c/d is based on the relation between r droop and load current to provide an easily setting and high accuracy current monitor indicator. the current monitor indication voltage v cm equation is shown as : load droop cm cm cmset 2i r r v r = (28) where i load is the output load current, r droop is the load line setting of applications, r cm and r cmset is the current monitor current setting resistor. to find r cm and r cmset base on : cm(max) cm cmset (max) droop v r r2ir = (29) the v cm(max) must be kept equal to 1v, i (max) is needed to follow the setting current of the imvp6.5 definition with various cpu. the r droop is the load line setting of applications. the v cm(max) is clamped not higher than 1.15v. there is a example for current monitor, the following design parameters are given : i (max) = 30a, r droop = 3m , v cm(max) = 1v, r cmset = 10k r cm = 55.6k ? figure 14. current monitor setting principle vsen v cc_sense current monitor generator r cmset cmset v cm r cm c1 rgnd cm inductor selection the switching frequency and ripple current determine the inductor value as follows : in out (min) on ripple max vv lt i ? ? = (30) where t on is the ugate turn on period. higher inductance yields in less ripple current and hence in higher efficiency. the flaw is the slower transient response of the power stage to load transients. this might increase the need for more output capacitors driving the cost up. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the core must be large enough not to be saturated at the peak inductor current. output capacitor selection output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. usually, the cpu manufacturer recommends a capacitor configuration. two different kinds of output capacitors can be found including, bulk capacitors closely located to the inductors and ceramic output capacitors in free datasheet http:///
rt8152c/d 23 ds8152c/d-00 july 2009 www.richtek.com close proximity to the load. latter ones are for mid- frequency decoupling with especially small esr and esl values while the bulk capacitors have to provide enough stored energy to overcome the low-frequency bandwidth gap between the regulator and the cpu. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt8152c/d, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-32l 5x5 package, the thermal resistance ja is 36 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (12 c ? 25 c ) / (36 c/w) = 2.778w for wqfn-32l 5x5 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for rt8152c/d package, the figure 15 of derating curve allows the designer to see the effect of rising ambient temperature on the maximum power allowed. layout considerations careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for optimum pc board layout : ` keep the high-current paths short, especially at the ground terminals. ` keep the power traces and load connections short. this is essential for high efficiency. ` the slew rate control capacitor should be connected from soft to rgnd, and it should be placed physically close to ic. connect slew-rate control capacitor at soft pin to rgnd. ` when trade-offs in trace lengths must be ma de, it?s preferable to allow the inductor charging path to be made longer than the discharging path. ` place the current sense component close to the controller. isen and isen_n connections for current limit and voltage positioning must be made using kelvin sense connections to guarantee the current sense accuracy. the pcb trace from the sense nodes should be parallel back to controller. ` route high-speed switching nodes away from sensitive analog areas (soft, comp, fb, vsen, isen, isen_n, cm, etc...) figure 15. derating curve for rt8152c/d package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) four layers pcb wqfn-32l 5x5 free datasheet http:///
rt8152c/d 24 ds8152c/d-00 july 2009 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension e d 1 d2 e2 l b e a a1 a3 see detail a note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 4.950 5.050 0.195 0.199 d2 3.400 3.750 0.134 0.148 e 4.950 5.050 0.195 0.199 e2 3.400 3.750 0.134 0.148 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 32l qfn 5x5 package free datasheet http:///

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