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description the a8651 is an adjustable frequency, high output current, pwm regulator that integrates a high-side, p-channel mosfet and a low-side, n-channel mosfet. the a8651 incorporates current-mode control to provide simple compensation, excellent loop stability, and fast transient response. the a8651 utilizes external compensation to accommodate a wide range of power components to optimize transient response without sacrificing stability. the a8651 regulates input voltages from 2.5 to 5.5 v, down to output voltages as low as 0.8 v and is able to supply up to 2 a of load current per regulator. the a8651 features include an externally adjustable and synchronizable switching frequency, an externally-set soft start time to minimize inrush currents, independent en inputs, and independent npor outputs with 7.5 ms delay. the sleep mode current of the a8651 control circuitry is less than 5 a. protection features include vin undervoltage lockout (uvlo), cycle-by-cycle overcurrent protection (ocp), hiccup mode short-circuit protection (hic), overvoltage protection (ovp), and thermal shutdown (tsd). in addition, the a8651 provides open-circuit, adjacent pin short-circuit, and short-to-ground a8651-ds features and benefits ? aec-q100 qualified ? operating voltage range: 2.5 to 5.5 v ? uvlo stop threshold: 2.25 v (max) ? dual outputs with up to 2 a output current per regulator ? adjustable output voltage as low as 0.8 v ? internal 80 m high-side switching mosfet ? internal 55 m low-side switching mosfet ? adjustable switching frequency ( f sw ): 0.35 to 2.2 mhz ? synchronizes to external clock: 1.2 to 1.5 f osc ? 180 phase shift between switching regulators ? sleep mode supply current less than 5 a ? soft start time externally set via the ss pin ? pre-biased startup capable ? externally adjustable compensation ? stable with ceramic output capacitors ? independent enable inputs and npor output pins ? adjustable current limiting (ocp) for each regulator ? hiccup mode short-circuit protection (hic) ? overvoltage and overtemperature protection ? open-circuit and adjacent pin short-circuit tolerant ? short-to-ground tolerant at every pin low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor typical application diagram a8651 package: 20-pin tssop with exposed thermal pad (suffix lp) not to scale continued on the next page? ? gps/infotainment ? automotive audio ? home audio ? network and telecom applications: fb1 l o1 pgnd1 pgnd2 v in vin1 gnd sw1 npor1 comp1 iset1 r z1 c z1 c ss1 c p1 en1 ss1 v out1 v out2 c in1 c sync d sync en1 20 16 17 19 2 3 4 1 18 15 a8651 c o1 c o2 r set1 5 fset/sync syncin vin2 c in2 11 13 12 9 8 7 r pu1 npor1 fb2 r fb4 r fb3 r fb2 r fb1 r fset r pu2 l o2 sw2 npor2 npor2 10 14 6 comp2 iset2 r z2 c z2 c ss2 c p2 en2 ss2 en2 r set2
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings 1 characteristic symbol notes rating unit vin1 and vin2 to gnd v in ?0.3 to 6.0 v sw1 and sw2 to gnd 2 v sw continuous ?0.3 to v in + 0.3 v t < 50 ns ?1.0 to v in +2.0 v all other pins ? ?0.3 to 6.0 v operating ambient temperature t a k temperature range ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc 1 operation at levels beyond the ratings listed in this table may cause permanent damage to the device. the absolute maximum rati ngs are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reli ability. 2 sw1 and sw2 have internal clamp diodes to gnd and v in . applications that forward bias these diodes should take care not to exceed the a8651 package power dissipation limits. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja on 4-layer pcb based on jedec standard 32 oc/w *additional thermal information available on the allegro website. protection at every pin to satisfy the most demanding automotive applications. the a8651 device is available in a 20-pin tssop package with exposed thermal pad for enhanced thermal dissipation (suffix lp). it is lead (pb) free, with 100% matte tin leadframe plating. description (continued) selection guide part number operating ambient temperature range t a , (c) package packing* leadframe plating a8651klptr-t ?40 to 125 20-pin tssop with exposed thermal pad 4000 pieces per 13-in. reel 100% matte tin *contact allegro? for additional packing options.
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table of contents specifications 2 thermal characteristics 2 pin-out diagram and terminal list 2 absolute maximum ratings 2 top level functional block diagram 4 detailed functional block diagram 5 pin-out diagram and terminal list 6 electrical characteristics 7 characteristic performance 10 timing diagram 12 functional description 13 overview 13 reference voltage 13 oscillator/switching frequency (r fset , f osc ) 13 transconductance error amplifier 13 slope compensation 13 en x , vin x , and sleep mode 14 synchronization (fset/sync) 14 power mosfets 14 pulse width modulation (pwm) 14 current sense amplifier 14 soft start (startup) and inrush current control 14 pre-biased startup 15 active low power-on reset (nporx) 16 protection features 16 undervoltage lockout (uvlo) 16 thermal shutdown (tsd) 16 overvoltage protection (ovp) 16 pulse-by-pulse overcurrent protection (ocp) 16 design and component selection 20 setting the output voltage (v out1 , r fbx ) 20 pwm switching frequency (r fset ) 20 output inductor (l o ) 21 output capacitors 22 input capacitors 22 soft start and hiccup mode timing (c ss1 ) 23 compensation components (rz, cz, cp) 24 a generalized tuning procedure 26 power dissipation and thermal calculations 28 pcb component placement and routing 30
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com switcher #1 (sw1) adjustable v out synchronous buck fb1 sw1 vin 1 comp1 clk0 ss 1 80 m npor1 tsd vi n1 uvl o v ref & por vin1 star t vin1 stop 55 m en1 iset1 fset / sync fb2 sw2 vin2 comp2 ss 2 80 m npor2 vi n2 uvlo switcher #2 (sw2) adjustable v out synchronous buck 55 m en2 iset 2 clk180 por & v ref note: vin1 supplies the bandgap (v ref ), oscillator , tsd , and other critical circuits oscillator 180 shift w/ sync i sense 2 i sense 1 pgnd1 pgnd2 gnd a8651 2 2 tsd tsd vin2 star t vin2 stop top level functional block diagram
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com detailed functional block diagram isetx ga in off off s r q q fault = 1 if: en = 0 o r uv lo = 1 ovp comp hiccup = 1 if: fb < 700m v and 7 ocp events vref current enx ssx fbx uv / ov 125ns reset dom ov min_toff gndx fault + - falling de lay slope ad j com p os cillator clkin adj2 fsw adj1 adj3 uv lox vssoffs compx pwm offs e t uv uv comp + - + error am p nporx + - 7.5m s tsd 92% x vref 88% x vref a8651 1 of 2 regulators shown 115% x vref 111% x vref vinx 10ns 1.5k 2k por 200m v vin vin pwm comp 20ua 10ua off clkx clam p 1.65vtyp 1.25vtyp 55m protections en_ocp_count uvlo en / clr hiccup latched hic rst current ocp fbx + - 380m v 80m hiccup non- ov erl ap fbx 100k swx pgndx 150na ocp + - en off off clamp active enx ocp if vfb > 400mv, fsw = clkx if vfb < 400mv, fsw = clkx/2 if vfb < 400m v & clamp active & ocp, fsw = clkx/4 clamp active pad
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram terminal list table number name function 1, 10 sw1, sw2 the drains of the internal high-side p-channel mosfets. the output inductors should be connected to these pins. the output inductors should be placed as close as possible to these pins and be connected with relatively wide traces. 2, 9 pgnd1, pgnd2 power ground pins for switcher 1 and switcher 2. 3, 8 en1, en2 inputs to enable switcher 1 and/or enable switcher 2. 4, 7 iset1, iset2 pulse?by-pulse current limit setting pins. 5 fset/sync a resistor, r fset , from this pin to gnd sets the base pwm switching frequency (f osc ). if an external clock is ac-coupled to this pin by a 22 pf capacitor, the switching frequency of the regulator can be increased higher than f osc . 6, 15 npor2, npor1 active low, open-drain fault indication outputs, with fixed delay. 11, 20 vin2, vin1 power inputs for the control circuits and the sources of the internal high-side p-channel mosfets. vin1 is the primary supply and must be present for the a8651 to operate. at least one high quality ceramic capacitor must be placed very close to these pins. 12, 19 ss2, ss1 soft-start pins. connect a capacitor, from these pins to gnd to set the soft-start time. these capacitors also determine the hiccup period during an overcurrent condition. 13, 17 comp2, comp1 outputs of the error amplifiers and compensation nodes for the current mode control loops. connect a series rc network from these pins to gnd for loop compensation. see the design and component selection section of this datasheet for further details. 14, 18 fb2, fb1 feedback (negative) inputs to the error amplifiers. connect a resistor divider from the converter output nodes to these pins to program the output voltages. 16 gnd ground. ?pad exposed pad of the package providing enhanced thermal dissipation. this pad must be connected to the ground plane(s) of the pcb with at least 6 vias, directly in the pad. pad 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 sw1 pgnd1 en1 iset1 fset/sync npor2 iset2 en2 pgnd2 sw2 vin1 ss1 fb1 comp1 gnd npor1 fb2 comp2 ss2 vin2
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid at vin1 = vin2 = 5 v, ?40c t a = t j 125c; unless otherwise specified characteristic symbol test conditions min. typ. max. unit input voltage specifications operating input voltage range v in 2.5 ? 5.5 v undervoltage lockout (uvlo) start threshold v instart v in1 = v in2 , rising 2.00 2.22 2.45 v undervoltage lockout (uvlo) stop threshold v instop v in1 = v in2 , falling 1.80 2.02 2.25 v undervoltage lockout (uvlo) hysteresis v uvlo(hys) ? 200 ? mv input currents input quiescent current i q v en1 = v en2 = 5 v, v fb1 = v fb2 = 1.0 v, no pwm switching ? 36ma input sleep supply current i qsleep v inx = v swx = 5 v, v en1 = v en2 0.4 v ? 0.2 5 a reference voltage reference (feedback) voltage v ref 2.5 v < v in1 = v in2 < 5.5 v, v fbx = v compx 792 800 808 mv error amplifier feedback input bias current (1) i fb v compx = 1.5 v, v fbx regulated so that i compx = 0 a ? ?150 ?300 na open loop voltage gain (2) a vol ? 65 ? db transconductance g m i compx = 0 a, v ssx > 500 mv 550 750 950 a/v 0 v < v ssx < 500 mv ? 250 ? a/v source current i ea(src) v fbx < 0.8 v, v compx = 1.5 v ? ?50 ? a sink current i ea(sink) v fbx > 0.8 v, v compx = 1.5 v ? +50 ? a maximum output voltage v eavo(max) 1.00 1.25 1.50 v comp pull down resistance r comp fault = 1, hiccup = 1 or v en1 = v en2 0.4 v ? 1.5 ? k pulse width modulation (pwm) pwm ramp offset v pwmoffset v compx for 0% duty cycle ? 380 ? mv high-side mosfet minimum controllable on-time t on(min) ? 65 105 ns low-side mosfet minimum on-time t off(min) does not include total gate driver non-overlap time, 2 x t off ? 50 100 ns gate driver non-overlap time (2) t off ? 15 ? ns comp to sw current gain g mpower ? 4.5 ? a/v slope compensation (2) s e r setx = 41.2 k , f sw = 2.0 mhz 2.1 2.5 2.9 a/ s r setx = 41.2 k , f sw = 0.35 mhz 0.36 0.44 0.51 a/ s r setx = 30.9 k , f sw = 2.0 mhz 1.0 1.4 1.9 a/ s r setx = 30.9 k , f sw = 0.35 mhz 0.17 0.25 0.35 a/ s note 1: for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). note 2: ensured by design and characterization, not production tested. continued on the next page?
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at vin1 = vin2 = 5 v, ?40c t a = t j 125c; unless otherwise specified characteristic symbol test conditions min. typ. max. unit mosfet parameters high-side mosfet on-resistance r ds(on)hs i dsx = 100 ma ? 80 ? m sw node rise time (2) t r(sw) ? 12 ? ns high-side mosfet leakage current i dss(hs) v enx 0.4 v, v swx = 0 v, v inx = 5 v, ?40 ? c < t a = t j < 85 ? c (3) ?? 4 a v enx 0.4 v, v swx = 0 v, v inx = 5 v, t a = t j = 125 ? c ?? 25 a low-side mosfet on resistance r ds(on)ls i dsx = 100 ma ? 55 ? m low-side mosfet leakage current i dss(ls) v enx 0.4 v, v swx = 5 v, ?40 ? c < t a = t j < 85 ? c (3) ?? 1 a v enx 0.4 v, v swx = 5 v, t a = t j = 125 ? c ?? 10 a oscillator frequency oscillator frequency f osc r fset = 10.2 k 1.98 2.20 2.45 mhz r fset = 24.9 k 0.90 1.00 1.10 mhz r fset = 82.5 k ? 350 ? khz sw1 to sw2 phase delay (2) 1,2 ? 180 ? deg. fset/sync input fset/sync high threshold v fsetsync(h) ?? 1.8 v fset/sync low threshold v fsetsync(l) 0.4 ?? v fset/sync pin voltage v fsetsync without external syncin signal ? 0.8 ? v fset/sync pin current i fsetsync without external syncin signal 9 ? 90 a maximum sync frequency f syncm ?? 2.5 mhz sync frequency range (2) f sync 1.2 f osc ? 1.5 f osc ? synchronization minimum on-time t onsync 150 ?? ns synchronization minimum off-time t offsync 150 ?? ns enable inputs en high threshold v enih v enx rising ?? 1.8 v en low threshold v enil v enx falling 0.8 ?? v en hysteresis v enhys v enih ? v enil ? 200 ? mv en input resistance r en 50 100 ? k en shutdown delay (2) t den(sd) from en x transitioning low to swx switching stops 0510 s note 2: ensured by design and characterization, not production tested. note 3: specifications at 25c or 85c are ensured by design and characterization, not production tested at these temperatures . continued on the next page?
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at vin1 = vin2 = 5 v, ?40c t a = t j 125c; unless otherwise specified characteristic symbol test conditions min. typ. max. unit overcurrent protection (ocp) and hiccup mode pulse-by-pulse current limit i lim r set = 41.2 k , duty cycle = 5% 3.5 4.1 4.7 a r set = 41.2 k , duty cycle = 90% (2) 2.2 3.0 3.8 a r set = 30.9 k , duty cycle = 5% 1.9 2.4 2.9 a r set = 30.9 k , duty cycle = 90% (2) 1.1 1.8 2.3 a hiccup disable threshold v hicdis v fbx rising ? 740 ? mv hiccup enable threshold v hicen v fbx falling ? 700 ? mv ocp / hiccup count limit ocp limit hiccup enabled (see functional block diagram), ocp pulses ? 7 ? counts soft start (ss pin) soft start offset voltage v ssoffs v ssx rising due to i sssu 100 200 270 mv soft start fault/hiccup reset voltage v ssreset v ssx falling due to i sshic ? 100 140 mv soft start startup (source) current i sssu v ssx = 1 v, hiccup = fault = 0 (see functional block diagram) ? 10 ?20 ? 30 a soft start hiccup (sink) current i sshic v ssx = 0.5v, hiccup = 1 (see functional block diagram) 51020 a soft start input resistance r ss fault (see functional block diagram) = 1 or enx = 0 ? 2 ? k soft start to v out delay time t ss(delay) c ssx = 10 nf ? 85 ? s v out soft start ramp time t ss c ssx = 10 nf ? 400 ? s soft start switching frequency f sw(ss) 0 v < v fbx < 400 mv, v compx = v eavo(max) , i dsx > i limx (2) ? f osc / 4 ?? 0 v < v fbx < 400 mv ? f osc / 2 ?? v fbx > 400 mv ? f osc ?? npor outputs npor undervoltage threshold v nporuv percentage of v ref , v fbx rising 89 92 95 % npor undervoltage hysteresis v nporuvhys percentage of v ref , v fbx falling 2 4 6 % npor overvoltage threshold v nporov percentage of v ref , v fbx rising 112 115 118 % npor overvoltage hysteresis v nporovhys percentage of v ref , v fbx falling 2 4 6 % npor rising delay t npor 4.0 7.5 11 ms npor low output voltage v npor(l) 2.5 v < vin1 = vin2 < 5 v, i npor = 4 ma ? ? 400 mv vin1 = vin2 =1.2 v, i npor = 2 ma ? ? 800 mv npor leakage current (1) i npor(leak) v nporx = 3.3 v ? ? 1 a thermal protection (tsd) thermal shutdown threshold (2) t sd(th) temperature rising 155 170 185 oc thermal shutdown hysteresis (2) t sd(hys) temperature falling ? 20 ? oc note 1: for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). note 2: ensured by design and characterization, not production tested.
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance oscillator frequency versus temperature vin uvlo start and stop thresholds versus temperature npor overvoltage and undervoltage thresholds versus temperature pulse-by-pulse current limit at t on(min) versus temperature error amplifier transconductance versus temperature 792 794 796 798 800 802 804 806 808 -50 -25 0 25 50 75 100 125 150 reference voltage, v ref (mv) temperature (c) 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 -50 -25 0 25 50 75 100 125 150 oscillator frequency, f osc (mhz) temperature (c) 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -50 -25 0 25 50 75 100 125 150 input voltage, v in (v) temperature (c) uvlo start threshold, v instart uvlo sto p threshold, v instop 80 85 90 95 100 105 110 115 120 -50 -25 0 25 50 75 100 125 150 threshold (% of v fb ) temper ature (c) v nporov , v fb rising v nporov , v fb f alling v nporuv , v fb rising v nporuv , v fb f alling 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 -50-25 0 255075100125150 current limit , i lim (a) temper ature (c) 550 600 650 700 750 800 850 900 950 -50 -25 0 25 50 75 100 125 150 transconductance, g m ( a/v) temperature (c) reference voltage versus temperature f osc = 2.2 mhz f osc = 1 mhz
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com enable high and low thresholds versus temperature soft start startup and hiccup currents versus temperature npor low output voltage versus temperature hiccup enable and disable thresholds versus temperature input sleep supply current versus temperature high- and low-side mosfets leakage current versus temperature 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -50 -25 0 25 50 75 100 125 150 en pin threshold (v) temperature (c) en high threshold, v enih en low threshold, v enil 5 7 9 11 13 15 17 19 21 23 25 -50-25 0 255075100125150 ss pin current ( a) temperature (c) ss startup current, i sssu ss hiccup current, i sshic 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 150 npor low output voltage, v npor(l) (mv) temperature (c) i npor = 4 ma i npor = 2 ma 550 575 600 625 650 675 700 725 750 775 800 825 850 -50 -25 0 25 50 75 100 125 150 hiccup threshold (mv) hiccup enable threshold,v hicen hiccup disable threshold, v hicdis 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 -25 0 25 50 75 100 125 150 input sleep supply current, i qsleep ( a) temperature (c) 0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125 150 leakage current ( a) temperature (c) high-side mosfet leakage curent, i dss(hs) low-side mosfet leakage curent, i dss(ls) temperature (c)
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com x 7 x 7 vout shorted to gnd mode enx tsd hic _ enx hiccup x vinx voutx ssx compx swx f / 4 ss pwm o c hiccup o c ss pwm pwm pwm s s f / 2 ss ss off / tsd ocx fsw ss pwm off / uvlo off / disabled off / uvlo off / disabled hiccup en glitches low fo r more than td en , sd v in dropout f / 2 fsw f / 2 fsw f / 2 fsw f / 2 fsw f / 4 tsd v ss , reset v ss , offs pwm offset hic dis hic en vin stop en vil vin start nporx t npor npor set below vin stop ea vo ( max ) td en , sd timing diagram (one of two regulators shown)
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 13 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description overview the a8651 is a dual synchronous pwm regulator that incorpo- rates all the control and protection circuitry necessary to satisfy a wide range of applications. the a8651 employs current mode control to provide fast transient response, simple compensa- tion, and excellent stability. the features of the a8651 include, for each of the two regulators: a precision reference, an adjust- able switching frequency, a transconductance error amplifier, an enable/synchronization input, integrated high-side and low-side mosfets, adjustable soft start, pre-bias startup, low current sleep mode, and a power-on reset output (npor). the protec- tion features of the a8651 include undervoltage lockout (uvlo), pulse-by-pulse overcurrent protection (ocp), hiccup mode short-circuit protection (hic), overvoltage protection (ovp), and thermal shutdown (tsd). in addition, the a8651 provides open- circuit, adjacent pin short-circuit, and pin-to-ground short circuit protection. reference voltage the a8651 incorporates an internal reference that allows output voltages as low as 0.8 v. the accuracy of the internal reference is 1% across the operating temperature range. the output voltage for each of the regulators is adjusted by connecting a resistor divider (r fb1 -r fb2 and r fb3 -r fb4 in the typical application diagram) from v outx to the corresponding fbx pin of the a8651. oscillator/switching frequency (r fset , f osc ) the pwm switching frequency of the a8651 is adjustable from 350 khz to 2.2 mhz and has an accuracy of about 10% across the operating temperature range. connecting a resistor ( r fset ) from the fset/sync pin to gnd, as shown in the typical application diagram, sets the base switching frequency, f osc . an fset/sync resistor with 1% tolerance is recommended. a graph of switching frequency versus r fset resistor value is shown in the design and component selection section of this datasheet. transconductance error amplifier the transconductance error amplifier?s primary function is to regulate the converter?s output voltage. the error amplifier for one of the regulators is shown in figure 1. it is shown as a three- terminal input device with two positive and one negative input. the negative input is simply connected to the fbx pin and is used to sense the feedback voltage for regulation. the two positive inputs are used for soft start and regulation. the error ampli- fier performs an ?analog or? selection between its two positive inputs. the error amplifier regulates to either the soft start pin voltage minus 200mv or the a8651?s internal reference, which- ever is lower. to stabilize the regulator, a series rc compensation network (r z and c z ) must be connected from the error amplifier output (compx pin) to gnd as shown in the typical applications diagram. in some applications, an additional, low value capacitor (c p ) may be connected in parallel with the r z -c z compensation network to reduce the loop gain at higher frequencies. however if the c p capacitor is too large, the phase margin of the converter may be reduced. if the regulator is disabled or a fault occurs, the correspond- ing compx pin is immediately pulled to gnd via approxi- mately 1.5 k and pwm switching is inhibited. during startup (v ssx < 500 mv) the transconductance of the error amplifier is reduced to approximatel y one-third of the normal operating level to minimize transients when the system is requesting on-times less than or equal to the minimum controllable on-time. slope compensation the a8651 incorporates internal slope compensation to allow pwm duty cycles above 50% for a wide range of input/output voltages, switching frequencies, and inductor values. as shown in the detailed functional block diagram, the slope compensation signal is added to the sum of the current sense and pwm ramp figure 1. the a8651 error amplifier (for one regulator) + - + error amplifier compx ssx fbx v ref 800 m v 200 m v
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 14 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com offset (v pwmoffset ). the amount of slope compensation is scaled directly with the switching frequency. en x , vin x , and sleep mode the a8651 provides two independent inputs, vin1 and vin2, to sequence the output voltages after the a8651 is powered up. however, vin1 is the primary supply input. vin1 must be greater than v instart or the a8651 will not come out of sleep mode. vin2 can start or stop regulator 2 but cannot wake up the a8651. if the voltage at en1 or en2 is driven below v enil (800 mv) for more than t den(sd) (approximately 5 s) the regulator stops switching. in sleep mode (en1< v envil ) for more than t den(sd) the control circuits are de-biased and draw less than 5 a from v in . how- ever, the total current drawn by the vin pin will be the sum of the current drawn by the control circuitry ( i qsleep ) plus any leakage due to the high-side mosfets ( i dss(hs) ). synchronization (fset/sync) by using a 22 pf capacitor (c sync ) to ac-couple an external clock to the fset/sync pin, as shown in figure 2, the switch- ing frequency of the a8651 can by increased from 1.2 f osc to 1.5 f osc . f osc is the base frequency determined by the r fset resistor. the schottky diode, d sync , is required to protect the fset/sync pin from negative voltage transients when synchro- nizing. power mosfets the a8651 regulators each include an 80 m , high-side p-chan- nel mosfet capable of delivering up to 4.1 a at a 5% duty cycle. the a8651 regulators also each include a 55 m , low-side n-channel mosfet to provide synchronous rectification. the low-side mosfet continues to conduct when the induc- tor current crosses zero to maintain constant conduction mode (ccm). this helps minimize emi/emc for noise sensitive appli- cations by eliminating the sw high-frequency ringing associated with discontinuous conduction mode (dcm). when the a8651 is disabled, via the enx input or a fault condi- tion, the a8651 output stage is tri-stated by turning off both the high-side and low-side mosfets. pulse width modulation (pwm) a high-speed pwm comparator, capable of pulse widths less than 105 ns, is included in each a8651 regulator. the inverting input of the comparator is connected to the output of the error ampli- fier. the non-inverting input is connected to the sum of the cur- rent sense signal, the slope compensation, and the pwm ramp offset (v pwmoffset ). at the beginning of each pwm cycle, the clk signal sets the pwm flip-flop and the upper mosfet is turned on. when the summation of the dc offset, the current sense signal, and the slope compensation rises above the error amplifier voltage, the comparator resets the pwm flip-flop and the high-side mosfet is turned off. if the output voltage of the error amplifier drops below the pwm ramp offset (v pwmoffset ) then a zero percent pwm duty cycle (pulse skipping) operation is achieved. current sense amplifier a high-bandwidth current sense amplifier monitors the current in the high-side mosfets. the pwm comparator, the pulse- by-pulse current limiter, and the hiccup mode up/down counter require the current signal. soft start (startup) and inrush current control inrush currents to the converter are controlled by the soft start function of the a8651. when the a8651 is enabled and all faults are cleared, the soft start (ssx) pins source approximately 20 a (i sssu ) and the voltage on the soft start capacitors (c ssx ) ramp upward from 0 v. when the voltage on a soft start pin exceeds the soft start offset voltage (v ssoffs , typically 200 mv mea- sured at the ssx pin) the output of the error amplifier is released and shortly thereafter the high-side and low-side mosfets figure 2. fset/sync ac-coupling and negative voltage protection circuit 22 pf c sync bat54 d sync sod323 r fset fset/sync syncin
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 15 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com begin switching. as shown in figure 3, there is a short delay (t ss(delay) ) between when the enable (enx) pin transitions high and when the soft start voltage reaches 200 mv to initiate pwm switching. when the a8651 begins pwm switching, the error amplifier regulates the voltage at the fbx pin to the soft start (ssx) pin voltage minus the soft start offset voltage (v ssoffs ). when pwm switching starts, the voltage at the ssx pin rises from 200 mv to 1000 mv, a difference of 800 mv, the voltage at the fbx pin rises from 0 v to 800 mv, and the regulator output voltage rises from 0 v to the target setpoint determined by the feedback resistor divider (rfb1-rfb2 or rfb3-rfb4). when the voltage at the soft start pin reaches approximately 1000 mv the error amplifier begin regulating using the a8651 internal reference, 800 mv. the voltage at the soft start pin con- tinues to rise to approximately v in . the soft start functionality is shown in figure 3. if the a8651 is disabled or a fault occurs, the internal fault latch is set and the soft start (ssx) pin is pulled to ground via approximately 2 k . the a8651 clears the internal fault latch when the voltage at the ssx pin decays to approximately 100 mv (v ssreset ). if the a8651 enters hiccup mode, the capacitor (c ssx ) on the soft start pin is discharged by a 10 a current sink (i sshic ). therefore, the soft start pin capacitor value (c ssx ) controls the time between soft start attempts. hiccup mode operation is discussed in more detail in the output short circuit (hiccup mode) protection section of this datasheet. when fbx > 400 mv the pwm switching frequency is f sw . if fbx < 300 mv the pwm switching frequency is reduced to f sw / 2 to provide the low duty cycles and accurate, stable control required during initial startup (when v out 0 v). also, if fbx < 400 mv and compx = v eavo(max) , it can be assumed the regu- lator output is shorted to ground. in this case the pwm switching frequency is further reduced to only f sw / 4 to allow more off-time between pwm pulses. this is done to prevent stair-casing of the output inductor current, which could result in damage to the inductor or the a8651. this is especially important when the input voltage is relatively high and the output of the regulator is either shorted or soft starting a relatively high output capacitance. pre-biased startup if the output capacitors are pre-biased to some voltage, the a8651 modifies the normal startup routine to prevent discharging the output capacitors. normally, the compx pin becomes active and pwm switching starts when the voltage at the soft start (ssx) pin reaches 200 mv. with pre-bias at the output, the pre-bias volt- age is sensed at the fbx pin. the a8651 does not start switching until the voltage at the soft-start pin increases to approximately v fbx + 200 mv. at this soft start pin voltage, the error amplifier output is released, the voltage at the compx pin rises, pwm switching starts, and v out ramps upward, starting from the pre-bias level. figure 4 shows startup when the output voltage is pre-biased to 0.9 v. figure 3. startup to v outx = 1.2 v, 2.0 a, with c ss = 22 nf figure 4. startup to v outx = 1.2 v, 2.0 a, with v out pre-biased to 0.6 v 1 . 2 v 1.2 v 1 0 0 0 m v 1000 mv s w i t c h i n g s t a r t s w h e n switching starts when v v c o m p comp > 3 5 0 m v > 350 mv c o m p p i n r e l e a s e d a t comp pin released at v v s s ss = v = v f b fb + 2 0 0 m v +200 mv v v o u t out r i s e s f r o m 0 . 6 v rises from 0.6 v 2 0 0 m v 200 mv v v o u t out v v c o m p comp v v e n en v v s s ss 1 . 2 v 1.2 v 1 0 0 0 m v 1000 mv s w i t c h i n g s t a r t s w h e n switching starts when v v c o m p comp > 3 5 0 m v > 350 mv 2 0 0 m v 200 mv v v o u t out t t s s ( d e l a y ) ss(delay) t t s s ss v v c o m p comp v v s s ss v v e n en
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 16 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com active low power-on reset (nporx) the nporx pins are open drain outputs, so an external pull-up resistor must be connected to each. an internal comparator moni- tors the voltage at the fbx pin and controls the open drain device at the nporx pins. nporx is pulled high by the external resis- tor approximately 7.5 ms after v outx is within regulation. the nporx output is pulled low if: ? v fbx(rising) < 92% of the reference voltage, or ? v fbx(rising) > 115% of the reference voltage, or ? en is low, or ? v in uvlo occurs, or ? thermal shutdown (tsd) occurs. if the a8651 is running and vinx transitions low, then nporx transitions low and remains low only as long as the internal circuitry is able to enhance the open-drain output device. when v in fully collapses, the nporx pin returns to the high impedance state. the npor comparator incorporates hysteresis to prevent chattering due to voltage ripple at the fbx pin. protection features undervoltage lockout (uvlo) an undervoltage lockout (uvlo) comparator monitors the volt- age at the vin pin and keeps the regulator disabled if the voltage is below the lockout threshold (v instart ). the uvlo com- parator incorporates enough hysteresis (v uvlo(hys) ) to prevent on-off cycling of the regulator due to ir drops in the vin path during heavy loading or during startup. thermal shutdown (tsd) the a8651 protects itself from overheating with an internal ther- mal monitoring circuit. if the junction temperature exceeds the upper thermal shutdown threshold (t sd(th) , nominally 170c), the voltages at the soft start (ssx) and compx pins is pulled to gnd and both the high-side and low-side mosfets are turned off. the a8651 stops pwm switching, but it does not enter the shutdown or sleep mode supply current levels. the a8651 auto- matically restarts when the junction temperature decreases more than the thermal shutdown hysteresis (t sd(hys) , 20c (typ) ). overvoltage protection (ovp) the a8651 uses the fbx pins to provide a basic level of overvolt- age protection. an overvoltage condition could occur if the load decreases very quickly or the compx pin or the regulator output are pulled high by some external voltage. when an overvoltage condition is detected, (1) nporx is pulled low, and (2) pwm switching stops (the swx node becomes high impedance). the compx and ssx pin voltages are not affected by ovp. if the regulator output decreases back to the normal operating range, nporx transitions high and pwm switching resumes. pulse-by-pulse overcurrent protection (ocp) the a8651 monitors the current in the high-side p-channel mosfet and if the current exceeds the pulse-by-pulse current overcurrent threshold (i lim ), then the high-side mosfet is turned off. normal pwm operation resumes on the next clock pulse from the oscillator. the a8651 includes leading edge blank- ing to prevent false triggering of the pulse-by-pulse current limit when the high-side mosfet is turned on. pulse-by-pulse current limiting is always active. a key feature of the a8651 is the ability to adjust the peak switch current limit. this can be useful when the full current capability of the regulator is not required for a given application. a smaller current limit may allow the use of power components with lower current ratings, thus saving space and reducing cost. a single resistor between the iset pin and ground controls the current limit. resistor values should be set in the range between 30.9 k (for the lowest current limit setting) and 41.2 k (for the highest current limit setting). the maximum switch current is affected by slope compensation via the duty cycle. the a8651 is conservatively rated to deliver 2.0 adc for most applications. however, the exact current the a8651 supports is heavily dependent on duty cycle, ambient temperature, thermal resistance of the pcb, airflow, component selection, and nearby heat sources. the a8651 is designed to deliver more current at lower duty cycles and slightly less current at higher duty cycles. for exam- ple, the pulse-by-pulse current limit at 20% duty cycle is typically 3.85 a, but at 80% duty cycle the pulse limit is typically 3.10 a.
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 17 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 5b. current limit versus duty cycle, with r set = 30.9 k 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 2 . 2 2 . 4 2 . 6 2 . 8 3 . 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 1 0 0 i l i m ( a ) d u t y c yc l e ( % ) min., f sw = 2.00 mhz typ., f sw = 2.00 mhz max., f sw = 2.00 mhz min., f sw = 350 khz typ., f sw = 350 khz max., f sw = 350 khz use table 1a and figure 5a, and table 1b and figure 5b to deter- mine the real current limit given the duty cycle required for each application. take care to do a careful thermal solution or thermal shutdown can occur. output short circuit (hiccup mode) protection hiccup mode protects the a8651 when the load is either too high or when the output of the converter is shorted to ground. when the voltage at the fbx pin is below the hiccup enable threshold (v hicen , 700 mv (typ)), hiccup mode protection is enabled. when the voltage at the fbx pin is above the hiccup disable threshold (v hicdis , 740 mv (typ)) hiccup mode protection is disabled. hiccup mode overcurrent protection monitors the number of overcurrent events using an up/down counter. an overcurrent pulse increments the counter by 1 and a pwm cycle without an overcurrent pulse decrements the counter by 1. if more than 7 consecutive overcurrents are detected then the hiccup latch is set and pwm switching is stopped. the hiccup signal causes the compx pin to be pulled low with a relatively low resistance 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5 101520253035404550556065707580859095100 i lim (a) duty cycle (%) min., f sw = 2.00 mhz typ., f sw = 2.00 mhz max., f sw = 2.00 mhz min., f sw = 350 khz typ., f sw = 350 khz max., f sw = 350 khz table 1a. pulse-by-pulse current limit versus duty cycle r set = 41.2 k , f sw = 2 mhz duty cycle (%) pulse-by-pulse current limit (a) min. typ. max. 5 3.42 4.04 4.65 20 3.17 3.86 4.51 40 2.83 3.61 4.31 60 ? 3.37 4.12 80 ? 3.12 3.92 90 ? 3.00 3.83 table 1b. pulse-by-pulse current limit versus duty cycle r set = 30.9 k , f sw = 2 mhz duty cycle (%) pulse-by-pulse current limit (a) min. typ. max. 5 1.85 2.37 2.87 20 1.69 2.27 2.77 40 1.49 2.13 2.64 60 1.28 2.00 2.52 80 ? 1.86 2.39 90 ? 1.80 2.32 figure 5a. current limit versus duty cycle, with r set = 41.2 k
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 18 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com s h o r t r e m o v e d short removed 4 . 1 a 4.1 a 2 0 0 m v 200 mv 1 0 0 m v 100 mv v v o u t out v v c o m p comp v v s s ss i i l l figure 6. hiccup mode operation and recovery (1.5 k ). hiccup mode also enables a current sink connected to the soft start (ssx) pin (i sshic ,10 a), so when hiccup initially occurs, the voltage at the soft start pin ramps downward. hiccup mode operation is shown in figure 6. when the voltage at the soft start pin decays to a low level (v ssreset , 100 mv (typ) ), the hiccup latch is cleared and the 10 a soft start pin current sink is turned off. the soft start pin resumes charging the soft start capacitor with 20 a, and the voltage at the soft start pin ramps upward. when the voltage at the soft start pin exceeds the soft start offset voltage (v ssoffs , 200 mv (typ)) the low resistance pull-down at the compx pin is turned off. the error amplifier forces the voltage at the compx pin to ramp up quickly, and pwm switch- ing begins. if the short circuit at the converter output remains, another hiccup cycle occurs. hiccup cycles repeat until the short circuit is removed or the converter is disabled. if the short circuit is removed the a8651 soft starts normally and the output voltage ramps to the operating level, as shown in figure 6.
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 19 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 2. summary of a8651 fault modes and operation fault mode v ss v comp high-side switch low-side switch npor reset condition output hard short to ground (v out and v fb = 0 v) hiccup after v comp 1.25 v and 7 oc faults clamped to 1.25 v for i lim , then pulled low during hiccup controlled by v comp , f sw / 2 if 0 < v fb < 400 mv, f sw / 4 if comp 1.25 v and i lim active during t off , off during hiccup depends on v out automatic, remove the short output overcurrent and v fb < v hicdis hiccup after v comp 1.25 v and 7 oc faults clamped to 1.25 v for i lim , then pulled low during hiccup controlled by v comp , f sw / 2 if 0 < v fb < 400 mv, f sw / 4 if v comp 1.25 v and i lim active during t off , off during hiccup depends on v out automatic, decrease the load current sw hard short to ground ramps to v in , hiccup may occur when the short is removed clamped to 1.25 v, pulled low if hiccup occurs controlled by v comp , turn off if v sw 0 v and blanking time expires, f sw / 4 active during t off , off if hiccup occurs when the short is removed depends on v out automatic, remove the short sw soft short to ground hiccup after v comp 1.25 v and 7 oc faults clamped to 1.25 v for i lim , then pulled low during hiccup controlled by v comp , f sw / 2 if 0 < v fb < 400 mv, f sw / 4 if v comp 1.25 v and i lim active during t off , off during hiccup depends on v out automatic, remove the short fb pin open (v fb floats high due to negative bias current) not affected transitions low via loop response as v fb floats high off, f sw / 2 if 0 < v fb < 400 mv, f sw if 300 mv < v fb off, disabled if v comp < 200 mv pulled low whenv fb > 115% v ref automatic, connect the fb pin output overvoltage (v fb > 115% v ref ) not affected transitions low via loop response because v fb > v ref off, f sw / 2 if 0 < v fb < 400 mv, f sw if 300 mv < v fb off, disabled if v comp < 200 mv pulled low when v fb > 115% v ref automatic, v fb returns to the normal range output undervoltage not affected transitions high via loop response controlled by v comp , f sw / 2 if 0 < v fb < 400 mv, f sw if 300 mv < v fb active during t off pulled low when v fb < 92% v ref automatic, v fb returns to the normal range thermal shutdown (tsd) pulled low and latched until v ss < v ssreset pulled low and latched until v ss > v ss(release) off off pulled low automatic, after the junction cools down
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 20 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com this section shows how to design and select external component values. for simplicity, the naming convention used here refers only to regulator 1, but the same design methods can be used for regulator 2. setting the output voltage (v out1 , r fbx ) the output voltage of the a8651 is determined by connecting a resistor divider from the output node (v out1 ) to the fb1 pin as shown in figure 7. there are trade-offs when choosing the value of the feedback resistors. if the series combination (r fb1 +r fb2 ) is relatively low then the light load efficiency of the regulator is reduced. so, to maximize the efficiency it is best to choose high values of resistors. on the other hand, if the parallel combination (r fb1 // r fb2 ) is too high, then the regulator may be susceptible to noise coupling into the fb1 pin. in general, the feedback resistors must satisfy the ratio shown in equation 1 to produce an output voltage, v out1 : = ? 1 0.8 (v) v out1 r fb2 r fb1 (1) table 4 shows the most common output voltages and recom- mended feedback resistors, assuming less than 0.2% efficiency loss at a light load of 100 ma and a parallel combination of 4 k presented to the fb1 pin. for optimal system accuracy, it is rec- ommended that the feedback resistors have 1% tolerances. pwm switching frequency (r fset ) the pwm switching frequency is set by connecting a resistor from the fset/sync pin to ground. figure 8 is a graph showing the relationship between the typical switching frequency (y-axis) and the fset resistor (x-axis). design and component selection figure 7. connection for the feedback divider rfb1 rfb2 v out1 fb1 pin table 3. recommended feedback resistors v out1 (v) r fb1 (v out1 to fb1 pin) (k ) r fb2 (fb1 pin to gnd) (k ) 1.2 6.04 12.1 1.5 7.50 8.45 1.8 9.09 7.15 2.5 12.4 5.76 3.3 16.5 5.23 figure 8. pwm switching frequency versus r fset 2.500 2.250 2.000 1.750 1.500 1.250 1.000 0.750 0.500 0.250 0 5 152535455565758595 fset resistor, r fset (k ) swtiching frequency, f sw (mhz)
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 21 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com to set a specific switching frequency (f sw ), the r fset resistor can be calculated as follows: = ? 1.7 f sw 24900 r fset (2) where f sw is in khz and r fset is in k . when the pwm switching frequency is chosen, the designer should be aware of the minimum controllable on-time (t on(min) ) of the a8651. if the application system required on-time is less than the a8651 minimum controllable on-time, then switch node jitter occurs and the output voltage has increased ripple or oscil- lations. the pwm switching frequency should be calculated as follows: = t on(min) v in1(max) v out1 f swmax (3) where v out1 is the output voltage, t on(min) is the minimum controllable on-time of the a8651 (worst case is 105 ns), and v in1(max) is the maximum required operational input voltage to the a8651 (not the peak surge voltage). if the a8651 synchronization function is employed, then the base switching frequency should be chosen such that jitter does not result at the maximum synchronized switching frequency accord- ing to equation 3: 1.5 f sw < f swmax calculated by equation 3. output inductor (l o ) for a peak current mode regulator it is common knowledge that, without adequate slope compensation, the system becomes unstable when the duty cycle is near or above 50%. however, the slope compensation in the a8651 is a fixed value (s e ). therefore, it is important to calculate an inductor value such that the falling slope of the inductor current (s f ) works well with the a8651 slope compensation. equations 4a and 4b can be used to calculate a range of values for the output inductor based on the well known approach of provid- ing slope compensation that matches 50% to 100% of the down slope of the inductor current. l o1 2 s e v out1 v out1 s e (4a) where l o is in h and the slope compensation (s e ) is a function of switching frequency, as follows: s e = 1.175 f sw1 (4b) where s e is in a/ s and f sw is in mhz. another limitation is shown in equation 5. this is based on a formula to calculate the amount of slope compensation required to critically damp the double poles at half the pwm switching frequency (this approach includes the duty cycle (d), which should be calculated at the minimum input voltage to insure optimal stability): l o1 1 ? v in1(min) v out1 v out1 s e 0.18 (5) to avoid dropout (saturation of the buck regulator), v in1(min) must be approximately 0.75 to 1.0 v above v out1 when calculat- ing the inductor value with equation 5. if equations 4a or 5 yield an inductor value that is not a standard value then the next closest available value should be used. the final inductor value should allow for 10% to 20% of initial toler- ance and 10% to 20% of inductor saturation. the saturation current of the inductor should be higher than the peak current capability of the a8651. ideally, for output short circuit conditions, the inductor should not saturate given the high- est pulse-by-pulse current limit at minimum duty cycle (i lim(5%) ); 4.7 a. this may be too costly. at the very least, the inductor should not saturate given the peak operating current according to the following equation: = i peak 4.1 ? s e v out1 1.15 f sw v in1(max) (6) where v in1(max) is the maximum continuous input voltage, such as 5.5 v. starting with equation 6 and subtracting half of the inductor ripple current provides us with an interesting equation to predict the typical dc load capability of the regulator at a given duty cycle (d = v out1 / v in1 ): i out1(dc) 4.1 ? ? s e dv out1 (1 ? d ) 2 f sw l o1 f sw (7) after an inductor is chosen it should be tested during output short circuit conditions. the inductor current should be monitored
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 22 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com using a current probe. a good design should ensure the inductor or the regulator are not damaged when the output is shorted to ground at maximum input voltage and the highest expected ambi- ent temperature. output capacitors the output capacitors filter the output voltage to provide an acceptable level of ripple voltage and they store energy to help maintain voltage regulation during a load transient. the voltage rating of the output capacitors must support the output voltage with sufficient design margin. the output voltage ripple ( v out1 ) is a function of the output capacitors parameters: c out1 , esr cout1 , and esl cout1 : = ? v out1 ? i l1 esr cout1 ? i l1 esl cout1 v in1 ? v out1 l o1 8 f sw c out1 + + (8) the type of output capacitors determines which terms of equa- tion 8 are dominant. for ceramic output capacitors the esr cout1 and esl cout1 are virtually zero, so the output voltage ripple will be dominated by the third term of equation 8: ? v out1 ? i l1 8 f sw c out1 (9) to reduce the voltage ripple of a design using ceramic output capacitors simply: increase the total capacitance, reduce the inductor current ripple (that is, increase the inductor value), or increase the switching frequency. for electrolytic output capacitors the value of capacitance will be relatively high, so the third term in equation 8 will be very small and the output voltage ripple will be determined primarily by the first two terms of equation 8: = ? v out1 ? i l1 esr cout1 esl cout1 v in1 l o1 + (10) to reduce the voltage ripple of a design using electrolytic out- put capacitors simply: decrease the equivalent esr cout1 and esl cout1 by using a high(er) quality capacitor, or add more capacitors in parallel, or reduce the inductor current ripple (that is, increase the inductor value). the esr of some electrolytic capacitors can be quite high so allegro recommends choosing a quality capacitor for which the esr or the total impedance is clearly documented in the capaci- tor datasheet. also, the esr of electrolytic capacitors usually increases significantly at cold ambients, as much as 10 x, which increases the output voltage ripple and, in most cases, reduces the stability of the system. the transient response of the regulator depends on the quantity and type of output capacitors. in general, minimizing the esr of the output capacitance will result in a better transient response. the esr can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. at the instant of a fast load transient (di/dt), the output voltage changes by the amount: = ? v out1 ? i l1 esr cout1 esl cout1 di dt + (11) after the load transient occurs, the output voltage will deviate from its nominal value for a short time. the length of this time depends on the system bandwidth, the output inductor value, and output capacitance. eventually, the error amplifier brings the output voltage back to its nominal value. the speed at which the error amplifier brings the output voltage back to the setpoint depends mainly on the closed-loop band- width of the system. a higher bandwidth usually results in a shorter time to return to the nominal voltage. however, a higher bandwidth system may be more difficult to obtain acceptable gain and phase margins. selection of the compensation components (r z , c z , and c p ) are discussed in more detail in the compensa- tion components section of this datasheet. input capacitors three factors should be considered when choosing the input capacitors. first, the capacitors must be chosen to support the maximum expected input surge voltage with adequate design margin. second, the capacitor rms current rating must be higher than the expected rms input current to the regulator. third, the capacitors must have enough capacitance and a low enough esr to limit the input voltage dv/dt to something much less than the hysteresis of the uvlo circuitry (nominally 200 mv for the a8651) at maximum loading and minimum input voltage.
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 23 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the input capacitor(s) must limit the voltage deviations at the vin1 pin to something significantly less than the device uvlo hysteresis during maximum load and minimum input voltage. the following equation allows us to calculate the minimum input capacitance: c in1 i out1 ? v in1(min) f sw 0.85 d (1 ? d ) (12) where v in1(min) is chosen to be much less than the hysteresis of the v in1 uvlo comparator ( v in1(min) 100 mv is recom- mended), and f sw is the nominal pwm frequency. the d (1?d) term in equation 12 has an absolute maximum value of 0.25 at 50% duty cycle. so, for example, a very con- servative design based on i out1 = 2.0 a, f sw = 85% of 2 mhz, d (1?d) = 0.25, and v in1 = 100 mv yields: = c in 1.7 (mhz) 100 (mv) 2.9 f 2.0 (a) 0.25 the input capacitors must deliver an rms current (i rms ) accord- ing to the following formula: = i rms i out1 d ( 1 ? d ) (13) where the duty cycle (d) is defined as: d = v out1 / v in1 (14) figure 9 shows the normalized input capacitor rms current versus duty cycle. to use this graph, simply find the operational duty cycle (d) on the x-axis and determine the input/output current multiplier on the y-axis. for example, at a 20% duty cycle, the input/output current multiplier is 0.40. therefore, if the regula- tor is delivering 2.0 a of steady-state load current, the input capacitor(s) must support 0.40 2.0 a or 0.8 arms. a good design should consider the dc-bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. this effect is very pronounced with the y5v and z5u temperature characteristic devices (as much as 90% reduction), so these types should be avoided. the x5r and x7r type capacitors should be the primary choices due to their stability versus both dc bias and temperature. for all ceramic capacitors, the dc-bias effect is even more pro- nounced on smaller sizes of device case, so a good design uses the largest affordable case size (such as 1206 or 1210). also, it is advisable to select input capacitors with plenty of design margin in the voltage rating to accommodate the worst case transient input voltage. soft start and hiccup mode timing (c ss1 ) the soft start time of the a8651 is determined by the value of the capacitance at the soft start pin, c ss1 . when the a8651 is enabled the voltage at the soft start pin (ss1) starts from 0 v and is charged by the soft start current, i sssu1 . however, pwm switch- ing does not begin instantly because the voltage at the soft start pin must rise above 200 mv. the soft start delay (t ss(delay) ) can be calculated using the following equation: = t ss(delay) c ss1 i sssu 200 (mv) (15) if the a8651 is starting into a very heavy load a very fast soft start time may cause the regulator to exceed the cycle-by-cycle overcurrent threshold. this occurs because the total of the full load current, the inductor ripple current, and the additional cur- rent required to charge the output capacitors: i cout1 = c out1 v out1 / t ss (16) is higher than the cycle-by-cycle current threshold, as shown in figure 9. normalized input capacitor ripple versus duty cycle 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0 102030405060708090100 duty cycle, d (%) i rms / i out1
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 24 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 10. this phenomena is more pronounced when using high value electrolytic type output capacitors. to avoid prematurely triggering hiccup mode the soft start capacitor, c ss1 , should be calculated according to: c ss1 c out1 v out1 i sssu 0.8 (v) i cout1 (17) where v out1 is the output voltage, c out1 is the output capaci- tance, i cout1 is the amount of current allowed to charge the output capacitance during soft start (recommend 0.1 a < i cout1 < 0.3 a). higher values of i cout1 result in faster soft start times. however, lower values of i cout1 ensure that hiccup mode is not inappropriately triggered. allegro recommends starting the design with an i cout1 of 0.1 a and increasing it only if the soft start time is too slow. if a non-standard capacitor value for c ss1 is calcu- lated, the next larger value should be used. the output voltage ramp time, t ss , can be calculated by using either of the following methods: = = t ss t ss c out1 c ss1 i sssu v out1 0.8 (v) or i cout1 (18) (19) when the a8651 is in hiccup mode, the soft start capacitor is used as a timing capacitor and sets the hiccup period. the soft start pin charges the soft start capacitor with i sssu during a startup attempt, and discharges the same capacitor with i sshic between startup attempts. because the ratio i sssu / i sshic is approximately 2:1, the time between hiccups is about two times as long as the startup time. therefore, the effective duty-cycle ofthe a8651 is very low and the junction temperature is kept low. compensation components (rz, cz, cp) to compensate the system, it is important to understand where the buck power stage, load resistance, and output capacitance form their poles and zeros in frequency. also, it is important to understand that the (type ii) compensated error amplifier introduces a zero and two more poles, and where these should be placed to maximize system stability, provide a high bandwidth, and optimize the transient response. first, consider the power stage of the a8651, the output capaci- tors, and the load resistance. this circuitry is commonly referred as the control-to-output transfer function. the low frequency gain of this circuitry depends on the comp1 to sw1 current gain ( g mpower ), and the value of the load resistor (r l1 ). the dc gain (g co(0hz) ) of the control-to-output is: g co(0hz) = g mpower r l1 (20) the control-to-output transfer function has a pole (f p1 ), formed by the output capacitance (c out1 ) and load resistance (r l1 ), located at: = f p1 c out1 r l1 2 1 (21) the control-to-output transfer function also has a zero (f z1 ) formed by the output capacitance (c out1 ) and its associated esr: = f z1 c out1 esr cout1 2 1 (22) for a design with very low-esr type output capacitors (such as ceramic capacitors), the esr zero, f z1 , is usually at a very high frequency so it can be ignored. on the other hand, if the esr zero falls below or near the 0 db crossover frequency of the system (as happens with electrolytic output capacitors), then it should be cancelled by the pole formed by the c p capacitor and the r z resistor (discussed and identified later as f p3 ). figure 10. output current (i cout1 ) during startup output capacitor current, i cout1 } i lim i load1 t ss
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 25 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a bode plot of the control-to-output transfer function for the schematic shown in figure 15, with v out1 = 1.2 v, i out1 = 1.5 a, and r l1 = 0.8 , is shown in figure 11. the pole at f p1 can easily be seen at 8.8 khz while the esr zero, f z1 , occurs at a very high frequency, 4 mhz (this is typical for a design using ceramic out- put capacitors). note, there is more than 90 of total phase shift because of the double-pole at half the switching frequency. next, consider the feedback resistor divider, (r fb1 and r fb2 ), the error amplifier (gm), and its compensation network r z -c z -c p . it greatly simplifies the transfer function derivation if r o >> r z , and c z >> c p . in most cases, r o > 2 m , 1 k < r z <100 k , 220 pf < c z < 47 nf, and c p < 50 pf, so the following equations are very accurate. the low frequency gain of the control section (g c(0hz) ) is formed by the feedback resistor divider and the error amplifier. it can be calculated as: = g c(0hz) r fb2 r o r fb1 +r fb2 g m = v fb r o v out g m = v fb v out a vol (23) where v out is the output voltage, v fb is the reference voltage (0.8 v), g m is the error amplifier transconductance (750 a/v ), and r o is the error amplifier output impedance (a vol /g m ). the transfer function of the type-ii compensated error amplifier has a (very) low frequency pole (f p2 ) dominated by the output error amplifier output impedance (r o ) and the c z compensation capacitor: = f p2 c z r o 2 1 (24) the transfer function of the type-ii compensated error amplifier also has frequency zero (f z2 ) dominated by the r z resistor and the c z capacitor: = f z2 c z r z 2 1 (25) lastly, the transfer function of the type-ii compensated error amplifier has a (very) high frequency pole (f p3 ) dominated by the r z resistor and the c p capacitor: = f p3 c p r z 2 1 (26) a bode plot of the error amplifier and its compensation network is shown in figure 12, where f p2 , f p3 , and f z2 are indicated on the gain plot. notice that the zero (f z2 at 16 khz) has been placed so that it is just above the pole at f p1 previously shown at 8.8 khz in the control-to-output bode plot (figure 11). placing f z2 just above f p1 results in excellent phase margin, but relatively slow transient recovery time, as we will see later. finally, consider the combined bode plot of both the control-to- output and the compensated error amplifier (figure 13). careful examination of this plot shows that the magnitude and phase of the entire system (red curve) are simply the sum of the error amplifier response (blue curve) and the control to output response (green curve). as shown in figure 13, the bandwidth of this sys- figure 11. control-to-output bode plot g co(0hz) = 12 db f p1 = 8.8 khz f z1 = 4 mhz 0 -180 -90 180 90 -80 0 -40 40 gain (db) phase () frequency (hz) 10 100 10 3 1010 3 10010 3 10 6 1.0 6 double pole at 1 mhz figure 12. type-ii compensated error amplifier bode plot g co(0hz) = 58 db f p2 = 45 hz f p2 z 1.1 mhz f z2 = 16 khz 90 0 -45 180 135 -40 40 0 80 g a i n (db) ph ase () frequency (hz) 10 100 10 3 1010 3 10010 3 10 6 1.0 6
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 26 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com tem (f c ) is 72 khz, the phase margin is 73 degrees, and the gain margin is 27 db. a generalized tuning procedure this section presents a methodology to systematically apply design considerations provided above. 1. choose the system bandwidth (f c ). this is the frequency at which the magnitude of the gain crosses 0 db. recommended values for f c , based on the pwm switching frequency, are in the range f sw / 20 < f c < f sw / 7.5. a higher value of f c generally provides a better transient response, while a lower value of f c generally makes it easier to obtain higher gain and phase margins. 2. calculate the r z resistor value. this sets the system bandwidth (f c ): = r z f c g mpower g m c out1 v out1 v fb1 2 (27) 3. determine the frequency of the pole (f p1 ). this pole is formed by c out and r l . use equation 21 (repeated here): = f p1 c out1 r l1 2 1 4. calculate a range of values for the c z capacitor. use the fol- lowing: << c z f c r z 2 4 f p1 r z 2 1.5 1 (28) to maximize system stability (that is, to have the greatest gain margin), use a higher value of c z . to optimize transient recovery time, although at the expense of some phase margin, use a lower value of c z . 5. calculate the frequency of the esr zero (f z1 ) formed by the output capacitor(s) by using equation 22 (repeated here): = f z1 c out1 esr cout1 2 1 if f z1 is at least 1 decade higher than the target crossover fre- quency (f c ) then f z1 can be ignored. this is usually the case for a design using ceramic output capacitors. use equation 26 to calculate the value of c p by setting f p3 to either 5 f c or f sw / 2, whichever is higher. alternatively, if f z1 is near or below the target crossover fre- quency (f c ), then use equation 26 to calculate the value of c p by setting f p3 equal to f z1 . this is usually the case for a design using high esr electrolytic output capacitors. figure 13. bode plot of the complete system (red curve) figure 14. transient recovery comparison for f z2 at 16 khz/69 and 50 khz/51 f c 72 khz gm = 27 db pm = 73 deg 0 -180 -90 180 90 -100 0 100 g a i n (db) ph ase () frequency (hz) 10 100 10 3 1010 3 10010 3 10 6 1.0 6 (v) (s) 240 250 260 270 280 290 300 310 320 330 1.840 1.820 1.800 1.780 1.760 1.740 1.725
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 27 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 15: typical application circuit for v in = 5 v at t a = 125c: vout 3.3 v/1.5 a and 1.2 v /1.5 a at 2 mhz c sync and d sync are only required if synchronizing to an external clock cin2 0.1uf 0805 cin3 10nf 0603 u1 a8651 ss1 19 en1 3 fset/sync 5 vin1 20 gnd 16 npor1 15 fb1 18 comp1 17 pgnd1 2 sw1 1 vin2 11 pgnd2 9 en2 8 ss2 12 comp2 13 sw2 10 fb2 14 npor2 6 iset1 4 iset2 7 co2 0.1uf 0805 co3 10nf 0603 vin csy nc 22pf 3.3v / 1.5a rfb2 5.23k rfb1 16.5k css1 22nf cin1 3.3uf 1206 rset1 34.8k en1 npor1 rz1 4.99k cp1 68pf cz1 1.8nf lo1 3.3uh 1 2 rpu1 10k co1 10uf 1206 3.3v syncin co9 10nf 0603 dsy nc bat54 sod323 cin5 0.1uf 0805 cin6 10nf 0603 css2 22nf cin4 3.3uf 1206 rset2 34.8k en2 rz2 5.62k cp2 68pf cz2 1.8nf rfset 11.3k co6 10uf 1206 co7 10uf 1206 co8 0.1uf 0805 1.2v / 1.5a rfb4 12.1k rfb3 6.04k npor2 lo2 1.5uh 1 2 rpu2 10k 3.3v co5 10uf 1206
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 28 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com power dissipation and thermal calculations the power dissipated in the a8651 is the sum of the power dis- sipated from the vin supply current (p in ) and the power dis- sipated by the two regulators. the regulator power dissipation is composed of: the power dissipated due to the switching of the high-side power mosfet (p sw(hs) ), the power dissipated due to the rms current being conducted by the high-side and low-side mosfets (p cond(hs) and p cond(ls) ), and the power dissipated by the low-side body diode (p no ) during the non-overlap time. the power dissipated from the vin supply current can be calcu- lated using the following equation: p in = v in1 i q + ( v in1 + v in2 ) ( q g(hs) + q g(ls) ) f sw (29) where v inx are the input voltages, i q is the input quiescent current drawn by the device (nominally 2 ma), q g(hs) and q g(ls) are the internal high- and low-side mosfet gate charges (approximately 3.3 nc and 1.4 nc, respectively), and f sw is the pwm switching frequency. note: the calculation after this point refers only to regulator 1. the power dissipated by the internal high-side mosfet during pwm switching can be calculated using the following equation: = p sw v in i out f sw ( t r + t f ) 2 (30) where v in is the input voltage, i out is the output current, f sw is the pwm switching frequency, and t r and t f are the rise and fall times measured at the sw node. the exact rise and fall times at the sw node depend on the external components and pcb layout so each design should be measured at full load. approximate values for both t r and t f range from 10 to 15 ns. the fall time is usually about 50% faster than the rise time. the conduction losses dissipated by the high-side mosfet while it is conducting can be calculated using the following equa- tion: = p cond(hs) i rms(fet) r ds(on)hs v out v in + 12 2 ? i l 2 i out 2 = r ds(on)hs (31) where i out is the regulator output current, i l is the peak-to-peak inductor ripple current, and r ds(on)1 is the on-resistance of the high-side mosfet. the conduction losses dissipated by the low-side mosfet can be calculated as: = p cond2 i rms(fet) r ds(on)2 v out v in + 12 2 ? i l 2 i out 2 = r ds(on)2 1 ? (32) where i out is the regulator output current, i l is the peak-to-peak inductor ripple current, and r ds(on)1 is the on-resistance of the high-side mosfet. the r ds(on) of the mosfets has some initial tolerance plus an increase from self-heating and elevated ambient temperatures. a conservative design should accommodate an r ds(on) with at least a 15% initial tolerance plus 0.39%/c increase due to temperature. the power dissipated by the low-side mosfets body diode dur- ing the non-overlap time can be calculated as: p no = v sd i out 2 t no f sw (33) where the deadtime is the same for the rising and falling edges of sw, v sd is the source-to-drain voltage of the low-side mosfet (typically 0.60 v), and t no is the non-overlap time (typically 15 ns),
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 29 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com finally, the total power dissipated by the device (p total ) is the sum of the previous equations: p total = p in + p regulator1 + p regulator2 (35) where p regulator1 = p sw + p cond(hs) + p cond(ls) + p no (36) the average junction temperature can be calculated with the fol- lowing equation: t j = p total r ja + t a (37) where p total is the total power dissipated as described in equation 35, r ja is the junction-to-ambient thermal resistance (48c/w on a 4-layer pcb), and t a is the ambient temperature. the maximum junction temperature is dependent on how effi- ciently heat can be transferred from the pcb to ambient air. it is critical that the thermal pad on the bottom of the ic should be connected to a at least one ground plane using multiple vias. as with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. there are trade-offs among: ambient operating temperature, input voltage, output voltage, output current, switching frequency, pcb thermal resistance, airflow, and other nearby heat sources. even a small amount of airflow will reduce the junction tempera- ture considerably.
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 30 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pcb component placement and routing a good pcb layout is critical if the a8651 is to provide clean, stable output voltages. follow these guidelines to insure a good pcb layout. figure 16 shows a typical buck converter schematic with the critical power paths/loops. figure 17 shows an example pcb component placement and routing with the same critical power paths/loops from the schematic. 1. place the ceramic input capacitors as close as possible to the vinx pins and ground the capacitors at the pgndx pins. the ceramic input capacitors and the a8651 must be on the same layer. connect the input capacitors, the vinx pins, and the pgndx pins with a wide trace. this critical loop is shown as a red trace in figures 16 and 17. 2. place the output inductor (l ox ) as close as possible to the swx pins. the output inductor and the a8651 must be on the same layer. connect the swx pins to the output inductor with a relatively wide trace or polygon. for emi/emc reasons, its best to minimize the area of this trace/polygon. this critical trace is shown as a green trace in figure 16. also, keep low level analog signals (like fb and comp) away from the sw metal. 3. place the output capacitors relatively close to the output induc- tor and the a8651. ideally, the output capacitors, output inductor and the a8651 should be on the same layer. connect the output inductor and the output capacitors with a fairly wide trace. the output capacitors must use a ground plane to make a very low inductance connection back to the pgnd pin. these critical con- nections are shown in blue in figures 16 and 17. 4. place the feedback resistor dividers (r fb1 -r fb2 ) very close to the fb pin. orient r fb2 such that its ground is as close as pos- sible to the a8651. 5. place the compensation components (r z , c z , and c p ) as close as possible to the comp pin. orient cz and cp such that their ground connections are as close as possible to the a8651. 6. place and ground the fset resistor as close as possible to the fset pin. 7. the output voltage sense trace (from v out to r fb1 ) should be connected as close as possible to the load to obtain the best load regulation. 8. the thermal pad under the ic should be connected a ground plane (preferably on the bottom layer) with as many vias as pos- sible. allegro recommends vias with approximately a 10-15 mil hole and a 5-7 mil ring. 9. place the soft start capacitor (css) as close as possible to the ss pin. place a via to the gnd plane as close as possible to this component. 10. when connecting the input and output ceramic capacitors to a power or ground plane, use multiple vias and place the vias as close as possible to the component?s pads. do not use thermal reliefs (spokes) around the pads for the input and output ceramic capacitors. 11. emi/emc issues are always a concern. allegro recommends having locations for an rc snubber from sw to ground. the snubber components can be placed on the back of the pcb and populated only if necessary. the resister should be 0805 or 1206 size. 12. allegro strongly recommends the use of current steering (a cut in the ground plane) to prevent current from sw1 from disturbing sw2 and vice versa. notice the horizontal cut in the ground plane as shown in figure 17.
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 31 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 16. typical synchronous buck converter with critical paths/loops shown figure 17: example pcb component placement and routing ss fset comp sw vin pgnd fb lo cin cout load single point ground could be the thermal/ground pad under the ic a8651 sw1 gnd css rfset rz cp cz rfb2 rfb1 notice the cut in the gnd plane
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 32 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 16. current derating curve versus output voltages, switching frequency, and ambient temperature 0 0.5 1 1.5 2 2.5 75 80 85 90 95 100 105 110 115 120 125 current ra ? ng (a) ambient temperature (c) 3.3vo 1.5vo 0 0.5 1 1.5 2 2.5 75 80 85 90 95 100 105 110 115 120 125 current ra ? ng (a) ambient temperature (c) 3.3vo 1.5vo 0 0.5 1 1.5 2 2.5 75 80 85 90 95 100 105 110 115 120 125 current ra ? ng (a) ambient temperature (c) 3.3vo 1.5vo 0 0.5 1 1.5 2 2.5 75 80 85 90 95 100 105 110 115 120 125 current ra ? ng (a) ambient temperature (c) 3.3vo 1.5vo v in = 5v, f sw v z h k 0 0 4 = in = 5v, f sw = 2 mhz v in = 5v, f sw v z h k 0 0 4 = in = 5v, f sw = 2 mhz
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 33 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 20-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 20x 0.65 bsc 0.25 bsc 2 1 20 6.500.10 4.400.10 3.00 3.00 4.20 4.20 6.400.20 gauge plane seating plane a terminal #1 mark area for reference only; not for tooling use (reference mo-153 act) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b 0.45 1.70 20 2 1 pcb layout reference view b 6.10 0.65 c exposed thermal pad (bottom surface); dimensions may vary with device reference land pattern layout (reference ipc7351 sop65p640x110-21m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) c
low input voltage, adjustable frequency dual synchronous 2 a / 2 a buck regulator with synchronization, 2x en, and 2x npor a8651 34 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2013-2014, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegro?s product can reasonably be expected to cause bodily harm. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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