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the ilc6383 series of step-up dc-dc converters operate from 1-cell to 3-cell input. they are direct replacement for ilc6382, in applications where sync pin is not used. the pfm or pwm operating mode is user selectable through sel pin connected to ground or left open, respectively .the choice should be dependent upon the current to be deliv- ered to the load : pfm is recommended for input voltage higher than 1.5v and loads below 100ma ,while pwm is recommended for more than 50ma load current in shut- down mode, the device allows true load disconnect from battery input. designed for wireless communications appli- cations, the oscillator frequency is set at 300khz with no harmonics at sub 20khz audio band or at 455khz if band. internal synchronous rectification and externally selectable pfm/pwm mode of operation allows the selection of the best efficiency at light or full load. the ilc6383 is capable of delivering 75ma at 3.3v output from a single cell input. the ilc6383-xx offers 3.3v or 5v fixed output voltage while the ilc6383-adj allows adjustable output voltage to 6v maximum. output voltage accuracy is 2% over speci- fied temperature range. additional features include power good output (pok) and an internal low battery detector with 100ms transient rejec- tion delay. the device will reject low battery input transients under 100ms in duration. the ilc6383 series is available in a space saving eight lead micro sop (msop-8) package. ilc6383 1-cell to 3-cell boost with true load disconnect, 3.3v, 5v or adjustable output www.fairchildsemi.com rev. 1.2 september 2001 1 ! 0.9v to 6v input voltage ! guaranteed start up in pwm at 0.9v input ! synchronous rectification requires no external diode ! true load disconnect from battery input in shutdown ! up to 75ma at 3.3v and 40ma at 5v from 1v input ! up to 375ma at 3.3v and 160ma at 5v from 3v input ! peak efficiency > 90% ! 1 a battery input current in shutdown (with v out = 0v) ! internal oscillator frequency : 300khz to 15% ! ilc6383 : fixed 3.3v or 5v output ! ilc6383-adj : adjustable output to 6v maximum ! low battery detector with 100ms transient rejection delay ! powergood output flag when v out is in regulation ! cellular phones, pagers ! palmtops, pdas and portable electronics ! high efficiency 1v step up converters 47 f on off v in 1 to 3-cell r5 r6 15 h l c out r1 r2 ilc6383-adj msop-8 l x v in lbi/sd sel gnd lbo v fb v out v out v out = 1.25 (1+r1/r2) 1 2 3 4 8 7 6 5 c in + + 47 f ilc6383-xx 1 3 2 4 8 6 7 5 l x v in lbi/sd sel gnd lbo pok v out on off v in 1 to 3-cell r5 r6 15 h msop-8 l v out 47f c out low battery detector output power good output c in + + pwm pfm pwm pfm 47 f general description features applications typical circuit figure 1: ilc6383cir-xx figure 2: ilc6383cir-adj final
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 2 pin number pin name pin description 1 l x inductor input. inductor l connected between this pin and the battery 2 v in connect directly to battery 3 lbi/sd low battery detect input and shutdown. low battery detect threshold is set with this pin using a potential divider. if this pin is pulled to logic low then the device will shut down. 4 sel a low logic level signal applied to this pin selects pfm operation mode. if the pin is left open or high logic level is applied, pwm mode is selected. 5 pok (ilc 6383cir - xx) this open drain output pin will go high when output voltage is within regulation, 0.92*v out (nom) < v out < 0.98*v out (nom) v fb (ilc6383cir - adj) this pin sets the adjustable output voltage via an external resistor divider network. the formula for choosing the resistors is shown in the ?applications information? sec tion. 6 lbo this open drain output will go low if the battery voltage is below the low battery threshold set at pin 3 7 gnd connect this pin to the battery and system ground 8 v ou t this is the regulated output voltage ordering information* (t a = -40c to + 85c) ilc6383cir-33 3.3v output, msop-8 package ILC6383CIR-50 5v output, msop-8 package ilc6383cir-adj adjustable output, msop-8 package msop (top view) ilc6383cir-xx sel lb/sd v in l x 1 2 3 4 5 6 7 8 v out gnd lbo pok sel lb/sd v in l x 1 2 3 4 5 6 7 8 v out gnd lbo v fb msop (top view) ilc6383cir-adj pin-package configurations pin functions ilc6382 parameter symbol ratings units voltage on v out pin v out -0.3 to 7 v voltage on lbi, sync, lbo, pok, v fb , l x and v in pins - -0.3 to 7 v peak switch current on l x pin il x 1 a current on lbo pin i sink(lbo) 5 ma continuous total power dissipation at 85 c p d 315 mw short circuit current i sc internally protected (1 sec duration) a operating ambient temperature t a -40 to 85 c maximum junction temperature t j (max) 150 c storage temperature t stg -40 to 125 c lead temperature (soldering 10 sec) 300 c package thermal resistance ja 206 c/w
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 3 parameter symbol conditions min typ max units output voltage v out(nom) 3.234 3.201 3.300 3.366 3.399 v output current i out v in = 0.9v, v out = v out(nom) 4% v in = 1.2v, v out = v out(nom) 4% v in = 2.4v, v out = v out(nom) 4% v in = 3.0v, v out = v o ut(nom) 4% 50 75 200 375 ma load regulation ? v out v out v in = 1.2v, 0ma < i out < 50ma 1.5 % no load battery input current i gnd v in = 1.2v, i out = 0ma 250 a efficiency v in = 1.2v, i out = 3ma, v in = 2.0v 90 % unless otherwise specified all limits are at v in = v lbi = 2.4v, i out = 50ma and t a = 25c. test circuit figure 1. boldface type indicates limits that apply over the full operating temperature range. note 2. absolute maximum ratings (note 1) electrical characteristics ilc6383cir-33 in pwm mode (sel open) electrical characteristics ilc6383cir-33 in pfm mode (sel in low state) parameter symbol conditions min typ max units output voltage v out 3.168 3.135 3.3 3.432 3.465 v output current i out v in = 2.0v, v out = v out(nom) 4% 100 ma load regulation ? v out v out 1ma < i out < 20ma 1 % no load battery input current i in(no load) i out = 0ma 250 a efficiency i out = 20ma, v in = 2.0v 88 % unless otherwise specified all limits are at v in = v lbi = 2.4v, i out = 1ma t a = 25c. test circuit figure 1. boldface type indicates limits that apply over the full operating temperature range. note 2.
parameter symbol conditions min typ max units lbo output voltage low v lbo(low) i sink = 2ma, open drain output, v lbi = 1v 0.4 v lbo output leakage current i lbo(hi) v lbo = 5v 1 2 a shutdown input voltage low v sd(low) 0.4 v shutdown input voltage high v sd(hi) 1 6 v sel input voltage high v sel(hi) 1.5 v sel input voltage low v sel(low) 0.4 v pok output voltage low v pok(low) i sink = 2ma, open drain output 0.4 v pok output voltage high v pok(hi) 6 v pok output leakage current i l(pok) force 6v at pin 5 2 a pok threshold v th(pok) 0.92x v out 0.95x v o ut 0.98xv o ut v pok hysteresis v hyst 50 mv feedback voltage (ilc6383cir-adj only) v fb 1.225 1.212 1.250 1.275 1.288 v output voltage adjustment range (ilc6383cir-adj only) v out(adj) min v out(adj) max v in = 0.9v, i out = 50ma v in = 3v, i out = 50ma 2.5v 6 v minimum startup voltage v in(start) i out = 10ma, pwm mode 0.9 1 v input voltage range v in v out = v out(nominal) 4% i out = 10ma (note 3) 0.9 1 v out(nominal) + +0.5v v battery input current in load disconnect mode i in(sd) v lbi/sd < 0.4v, v out = 0v (short circuit) 1 10 a switch on resistance r ds(on) n-channel mosfet p-channel mosfet 400 750 m ? oscillator frequency f osc 255 300 345 khz lbi input threshold v ref 1.175 1.150 1.250 1.325 1.350 input leakage current i leak pins lb/sd,sel and vfb, ( note 4) 200 na lbi hold time t hold (lbi) (note 5) 100 120 ms 1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 4 unless otherwise specified all limits are at v in = v lbi = 2.4v and t a = 25c. test circuits figure 1 and figure 2 for ilc6383cir-xx and ilc6383cir-adj respectively. boldface type indicates limits that apply over the full operating temperature range. note 2. general electrical characteristics for all voltage versions.
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 5 note 1 . absolute maximum ratings indicate limits which, when exceeded, may result in damage to the component. electrical specifications do not apply when operating the device outside its rated operating conditions. note 2 . specified min/max limits are production tested or guaranteed through correlation based on statistical control methods. measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing. note 3. v out (nom) is the nominal output voltage at i out = 50ma in pwm mode. note 4 . guaranteed by design. note 5 . in order to get a valid low-battery-output (lbo) signal, the input voltage must be lower than the low-battery-input (lbi) threshold for a duration greater than the low battery hold time (t hold(lbi) ). this feature eliminates false triggering due to voltage transients at the battery terminal.
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 6 the ilc6383 performs boost dc-dc conversion by control- ling the switch element as shown in the simplified circuit in figure 3 below. when the switch is closed, current is built up through the inductor. when the switch opens, this current has to go somewhere and is forced through the diode to the output. as this on and off switching continues, the output capacitor voltage builds up due to the charge it is storing from the inductor current. in this way, the output voltage gets boost- ed relative to the input. in general, the switching characteristic is determined by the output voltage desired and the current required by the load. specifically the energy transfer is determined by the power stored in the coil during each switching cycle. p l = ?(t on , v in ) synchronous rectification the ilc6383 also uses a technique called "synchronous rectification" which removes the need for the external diode used in other circuits. the diode is replaced with a second switch or in the case of the ilc6383, an fet as shown in figure 4 below. the two switches now open and close in opposition to each other, directing the flow of current to either charge the inductor or to feed the load. the ilc6383 monitors the volt- age on the output capacitor to determine how much and how often to drive the switches. pwm mode operation the ilc6383 uses a pwm or pulse width modulation tech- nique. the switches are constantly driven at typically 300khz. the control circuitry varies the power being deliv- ered to the load by varying the on-time, or duty cycle, of the switch sw1 (see fig. 5). since more on-time translates to higher current build-up in the inductor, the maximum duty cycle of the switch determines the maximum load current that the device can support. the minimum value of the duty cycle determines the minimum load current that can main- tain the output voltage within specified values. there are two key advantages of the pwm type controllers. first, because the controller automatically varies the duty cycle of the switch's on-time in response to changing load conditions, the pwm controller will always have an opti- mized waveform for a steady-state load. this translates to very good efficiency at high currents and minimal ripple on the output. ripple is due to the output cap constantly accepting and storing the charge received from the induc- tor, and delivering charge as required by the load. the "pumping" action of the switch produces a sawtooth-shaped voltage as seen by the output. the other key advantage of the pwm type controllers is that the radiated noise due to the switching transients will always occur at the (fixed) switching frequency. many appli- cations do not care much about switching noise, but certain types of applications, especially communication equipment, need to minimize the high frequency interference within their system as much as possible. using a boost converter requires a certain amount of higher frequency noise to be generated; using a pwm converter makes that noise high- ly predictable thus easier to filter out. pfm mode operation for low loads the ilc6383 can be switched to pfm, or pulse frequency modulation, technique at low currents. this technique conserves power loss by only switching the output if the current drain requires it. as shown in the figure 5, the waveform actually skips pulses depending on the power needed by the output. this technique is also called "pulse skipping" because of this characteristic. in the ilc6383, the switchover from pwm to pfm mode is determined by the user to improve efficiency and conserve power. v out pok lbo lb/sd sel gnd l x v in ilc6383 pwm/pfm controller shutdown control v ref delay + + - - sw1 sw2 ilc6382 fig. 4 ilc6382 fig. 5 figure 3: basic boost circuit figure 4: simplified ilc6382 block diagram applications information
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 7 the dual pwm/pfm mode architecture was designed specifically for applications such as wireless communica- tions, which need the spectral predictability of a pwm-type dc-dc converter, yet also need the highest efficiencies possible, especially in standby mode. other considerations the other limitation of pwm techniques is that, while the fundamental switching frequency is easier to filter out since it's constant, the higher order harmonics of pwm will be present and may have to be filtered out, as well. any filter- ing requirements, though, will vary by application and by actual system design and layout, so generalizations in this area are difficult, at best. however, pwm control for boost dc-dc conversion is widely used, especially in audio-noise sensitive applica- tions or applications requiring strict filtering of the high fre- quency components. low battery detector the ilc6383's low battery detector is a based on a cmos comparator. the negative input of the comparator is tied to an internal 1.25v (nominal) reference, v ref . the positive input is the lbi/sd pin. it uses a simple potential divider arrangement with two resistors to set the lbi threshold as shown in figure 6. the input bias current of the lbi pin is only 200na. this means that the resistor values r1 and r2 can be set quite high. the formula for setting the lbi thresh- old is: vlbi = vref x (1+r5/r6) since the lbi input current is negligible (<200na), this equation is derived by applying voltage divider formula across r6. a typical value for r6 is 100k ? . r5 = 100k ? x [(v lbi /v ref ) -1], where v ref =1.25v (nom.) the lbi detector has a built in delay of 120ms. in order to get a valid low-battery-output (lbo) signal, the input volt- age must be lower than the low-battery-input (lbi) thresh- old for a duration greater than the low battery hold time (t hold(lbi) ) of 120msec. this feature eliminates false trigger- ing due to voltage transients at the battery terminal caused by high frequency switching currents. the output of the low battery detector is an open drain capable of sinking 2ma. a 10k ? pull-up resistor is recom- mended on this output. for vlbi < 1.25v the low battery detector can also be configured for voltages <1.25v by bootstrapping the lbi input from v out . the cir- cuitry for this is shown in figure 7. v set v out switch waveform r6 r5 lbi/sd 3 2 v in ilc6383 shutdown delay 100ms 1.25v internal reference gnd 7 lbo 3.3v r pu 6 + - ilc6382 fig. 6 figure 5: pfm waveform figure 6: low battery detector
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 8 the following equation is used when v in is lower than 1.25v: r1 = r2 x [(v ref - v in ) / (v out - v ref )], where v ref = 1.25v (nom.) this equation can also be derived using voltage divider for- mula across r2. a typical value for r2 is 100k ? . shut down the lbi pin is shared with the shutdown pin. a low voltage (<0.4v) will put the ilc6383 into a power down state. the simplest way to implement this is with an fet across r6 as shown in figure 8. note that when the device is not in pwm mode or is in shutdown the low battery detector does not operate. when the ilc6383 is shut down, the synchronous rectifier disconnects the output from the input. this ensures that there is only leakage (i in < 1a typical) from the input to the output so that the battery is not drained when the ilc6383 is shut down. power good output (pok) the pok output of the ilc6383 indicates when v out is within the regulation tolerance of the set output voltage. pok output is an open drain device output capable of sink- ing 2ma. it will remain pulled low until the output voltage has risen to typically 95% of the specified v out. note that a pull-up resistor must be connected from the pok output (pin 5 of ilc6383cir-xx) to either ilc6383's output or to some other system voltage source. adjustable output voltage selection the ilc6383-adj allows the output voltage to be set using a potential divider. the formula for setting the adjustable output voltage is; v out = v fb x (1+r1/r2) where v fb is the threshold set which is 1.25v nominal. negative voltage output it is possible to generate a negative output voltage as a sec- ondary supply using the ilc6383. this negative voltage may be useful in some applications where a negative bias voltage at low current is required. v out 8 r2 3 lbi/sd v in r1 ilc6383 + - 1.25v internal reference gnd 7 on/off r5 r6 lbi/sd 3 ilc6383 2 v in 7 gnd 47 f on off v in 1 to 3-cell r5 r6 15 h l 47f c out r1 r2 ilc6383-adj msop-8 l x v in lbi/sd sel gnd lbo v fb v out v out v out = 1.25 (1+r1/r2) 1 2 3 4 8 7 6 5 c in + pwm pfm 1 2 l l x v in v in ilc6383 0.01f 0.01f -v 1a schottky diodes figure 7: v lbi < 1.25v figure 8: shut down control figure 9: adjustable voltage configuration figure 10: negative output voltage
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 9 inductors the ilc6383 is designed to work with a 15h inductor in most applications. there are several vendors who supply standard surface mount inductors to this value. suggested suppliers are shown in table 1. higher values of inductance will improve efficiency, but will reduce peak inductor cur- rent and consequently ripple and noise, but will also limit output current. capacitors input capacitor the input capacitor is necessary to minimize the peak cur- rent drawn from the battery. typically a 10f tantalum capacitor is recommended. low equivalent series resist- ance (esr) capacitors will help to minimize battery voltage ripple. output capacitor low esr capacitors should be used at the output of the ilc6383 to minimize output ripple. the high switching speeds and fast changes in the output capacitor current, mean that the equivalent series impedance of the capacitor can contribute greatly to the output ripple. in order to mini- mize these effects choose an output capacitor with less than 10nh of equivalent series inductance (esl) and less than 100m ? of equivalent series resistance (esr). typically these characteristics are met with ceramic capac- itors, but may also be met with certain types of tantalum capacitors. suitable vendors are shown in table 2. layout and grounding considerations high frequency switching and large peak currents means pcb design for dc-dc converters requires careful consid- eration. a general rule is to place the dc-dc converter cir- cuitry well away from any sensitive rf or analog compo- nents. the layout of the dc-dc converters and its exter- nal components are also based on some simple rules to minimize emi and output voltage ripple. layout 1 . place all power components, ilc6383, inductor, input capacitor and output capacitor as close together as possible. 2. keep the output capacitor as close to the ilc6383 as possible with very short traces to the v out and gnd pins. typically it should be within 0.25 inches or 6mm. 3. keep the traces for the power components wide, typi- cally >50mil or 1.25mm. 4 . place the external networks for lbi and vfb close to the ilc6383, but away from the power components as far as possible. grounding 1 . use a star grounding system with separate traces for the power ground and the low power signals such as lbi/sd and vfb. the star should radiate from where the power supply enters the pcb. 2 . on multilayer boards use component side copper for grounding around the ilc6383 and connect back to a quiet ground plane using vias. vendor part no contact coilcraft do3308p-153 d03316p-153 d01608c-153 (847) 639 6400 murata lqh4n150k lqh3c150k (814) 237 1431 sumida cdr74b-150mc cd43-150 cd54-150 (847) 956 0666 tdk nlc453232t-150k (847) 390 4373 description vendor contact t495 series tantalum kemet (864) 963 6300 595d series tantalum sprague (603) 224 1961 taj, tps series tantalum avx (803) 946 0690 tdk (847) 390 4373 avx (803) 946 0690 y5v ceramic murata www.murata.com 47f v in 15 h c out 47f r1 r2 ilc6383 l x v in lbi/sd sel gnd lbo v fb v out v out 1 2 3 4 8 7 6 5 c in + r3 load on/off local "quiet" ground power ground l1 pwm pfm recommended application circuit schematic for ilc6383cir-adj external component selection
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 10 label part number manufacturer description u1 ilc6383cir - xx impala linear step - up dc - dc converter c grm43 - 2x5r476k6.3 murata 47 f, ceramic capacitor l1 lqs66ca50m04 murata 15 h, 1.3a r1 and r3 - dale, panasonic 10k, 1/10w, smt r4 - dale, panasonic 1m ? , 1/10w, smt label part number manufacturer description u1 ilc6383cir - adj impala linear step - up dc - dc converter c grm43 - 2x5r476k6.3 murata 47 f, ceramic capacitor l1 lqs66c150m04 murata 15 h, 1.3a r1 and r2 - dale, panasonic user determined values r3 - dale, panas onic 10k ? , 1/10w, smt r4 - dale, panasonic 1m ? , 1/10w, smt evaluation board parts list for printed circuit board shown above 47f v in 15 h 47f ilc6383xx l x v in lbi sel gnd lbo pok/vfb v out v out 1 2 3 4 8 7 6 5 c2 r3 on l1 c1 lbo pok/vfb 10k r1 10k off u2 pwm pfm sel gnd r4 1m ? u1 47f v in 15 h 47f r2 ilc6383adj l x v in lbi sel gnd lbo pok/vfb v out v out 1 2 3 4 8 7 6 5 c2 r3 on l1 c1 lbo vfb r1 10k off u2 pwm pfm sel gnd r4 1m ? u1 note: r1 and r2 are user determined values to set v out = vfb(1+r1/r2)
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 11 90 85 80 75 10 20 30 40 50 60 70 80 90100 i out (ma) eff i ci e nc y ( %) v out =3.3v v in =1.2v v in =2.4v v in =0.9v 3.26 3.34 3.32 3.24 0.9 1.4 1.9 2.4 2.9 v in (v) v out (v) 3.30 3.28 3.26 i out =70ma v out =3.3v (nominal) efficiency line regulation 3.35 0 20406080100 i out (ma) v out (v) v in =2.4v 3.33 3.31 3.29 3.27 3.25 v in =0.9v v in =1.2v load regulation v out =3.3v (nominal) 3.40 -40 -30 -20 -10 0 90 temperature (c) 3.35 3.30 3.25 3.20 3.10 v out vs temperature 3.15 20 10 30 40 50 60 70 80 i out =75ma v in =1.5v v in =1.2v v in =0.9v 1s/div ? l x pin 2v/div 0v load switching waveforms (pwm mode) 0v 0ma v out 10mv/div inductor current ac c o u pl e d 200ma/div v out =3.3v i out =75ma 10s/div? l x pin 2v /di v 0v load switching waveforms (pfm mode) 0ma 0v v ou t 10mv/div inductor current ac c o up l ed 200ma/div v out =3.3v i out =12ma v in =1.2v v out (v) v in =1.2v unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h. i out = 12ma typical performance characteristics ilc6383cir-33 (v out = 3.3 v) efficiency (pwm mode) 0.6 0.7 0.8 0.9 1 30 50 100 150 200 250 300 350 400 v in = 2v v in = 1.5v v in = 2.5v efficiency load current (ma) 0.9 0.85 0.8 0.75 0.7 0.65 1 5 10 15 20 25 30 load current (ma) efficiency efficiency (pfm mode) v in = 2.5v v in = 2v v in = 1.5v 400 350 300 250 200 150 100 50 load regulation (pwm mode) output voltage (v) load current (ma) v in = 2.5v v in = 2v v in = 1.5v 3.42 3.4 3.38 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 3.2 3.18 3.2 3.22 3.24 3.26 3.28 3.3 3.32 3.34 3.36 1 5 10 15 20 25 load regulation (pfm mode) load current (ma) output voltage (v) v in = 3v v in = 2v v in = 1.5v
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 12 typical performance characteristics ilc6383cir-33 (v out = 3.3v) unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h. v out = 3.3v v in = 1.2v i out = 10ma v in = 1.2v i out = 40ma v out = 3.3v i out = 0ma 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 110 203040 50 start-up input voltage vs output current in pfm load current (ma) start-up input voltage (v) start-up (pwm mode) (pfm mode)
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 13 typical performance characteristics ilc6383cir-33 (v out = 3.3v) unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h. 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 50 100 150 200 start-up input voltage vs output current (pwm mode) load current (ma) start-up voltage (v) (pwm mode) (pwm mode)
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 14 typical performance characteristics ilc6383cir-33 (v out = 3.3v) unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h. v out = 3.3v v in = 1.2v i out = 66ma 3.40 3.35 3.30 3.25 3.20 3.15 3.10 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 i out = 50ma v in = 1.5v v in = 2.5v v in = 2v pwm mode v out vs temperature temperature (c) v out (v) 3.34 1.5 2 2.5 3 line regulation (pfm mode) v out (v) v in (v) i out = 50ma 3.33 3.32 3.31 3.3 3.29 3.28 3.27 3.26 3.25 3.24 3.33 3.32 3.31 3.3 3.29 3.28 3.27 3.26 3.25 3.24 3.23 1.5 2 2.5 3 line regulation (pwm mode) v out (v) v in (v) i out = 100ma
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 15 typical performance characteristics ILC6383CIR-50 (v out = 5.0v) unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h. v in = 3.0v v in = 2.4v
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 16 typical performance characteristics ILC6383CIR-50 (v out = 5.0v) unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h. v out = 5.0v v in = 1.2v
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 17 typical performance characteristics ILC6383CIR-50 (v out = 5.0v) unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h. v out = 5.0v v in = 2.4v v out = 5.0v v in = 1.2v i out = 67ma c out = 10f fundamental: 352khz/2.5mv rms first harmonic: 704khz/1.5mv rms
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output rev. 1.2 september 2001 18 spectral noise plot 1.75 1.40 1.05 0.70 100 0.35 0 v out (mvr ms) v out =5.0v v in =1.2v i out =67ma c out =2x 10f fundamental: 352khz/1.3mvrms first harmonic: 704khz/0.49mvrms freq (hz) ? 1k 10k 100k 1m start-up input voltage vs. output current i out (ma) input voltage (v) 1.1 1 0.8 0.7 0.6 0.5 0.9 1.4 1.3 1.2 20 100 60 120 0 1.5 v out = 5v 40 80 typical performance characteristics ILC6383CIR-50 (v out = 5.0v) unless otherwise specified: t a = 25c, c in = 47f, c out = 47f, l = 15h.
1-cell to 3-cell boost with true load disconnect, 3.3v, 5v, or adjustable output 19 0.118 0.004 0.118 0.004 .020 typ. 0.013 typ. 0.0256 bsc 0.000-0.005 rad. typ. 0.040 0.004 seating plane 3 typ. 12 typ 0.116 12 typ 0.118 0.006 rad. typ. 0.037 0.0215 package dimensions msop-8 all dimensions in inches life support policy fairchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corpora- tion. as used herein: disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/28/00 0.0m 001 stock#dsxxxxxxxx '2001 f airchild semiconductor corporation

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