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| 1 features ? 3.0v to 5.5v operating range advanced low-voltage, zero-power, electrically erasable programmable logic device edge-sensing ?zero? power low-voltage equivalent of atf22v10cz ?zero? standby power (25 a maximum) (input transition detection) ideal for battery powered systems cmos- and ttl-compatible inputs and outputs latch feature hold inputs to previous logic states advanced ee technology ? reprogrammable ? 100% tested high-reliability cmos process ? 20-year data retention ? 100 erase/write cycles ? 2,000v esd protection ? 200 ma latch-up immunity commercial and industrial temperature ranges dual inline and surface mount standard pinouts inputs are 5v tolerant block diagram high- performance ee pld atf22lv10cz ATF22LV10CQZ rev. 0779j?11/00 pin configurations all pinouts top view pin name function clk clock in logic inputs i/o bi-directional buffers gnd ground vcc (3 to 5.5v) supply tssop note: tssop is the smallest package of spld offering. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk/in in in in in in in in in in in gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o in dip/soic 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk/in in in in in in in in in in in gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o in plcc note: for plcc, pins 1, 8, 15, and 22 can be left unconnected. for superior performance, connect vcc to pin 1 and gnd to pins 8, 15, and 22. 5 6 7 8 9 10 11 25 24 23 22 21 20 19 in in in gnd* in in in i/o i/o i/o gnd* i/o i/o i/o 4 3 2 1 28 27 26 12 13 14 15 16 17 18 in in gnd gnd* in i/o i/o in in clk/in vcc* vcc i/o i/o
atf22lv10c(q)z 2 description the atf22lv10cz/cqz is a high-performance cmos (electrically erasable) programmable logic device (pld) that utilizes atmel ? s proven electrically erasable flash memory technology and provides 25 ns speed with standby current of 25 a maximum. all speed ranges are specified over the 3.0v to 5.5v range for industrial and commercial temperature ranges. the atf22lv10cz/cqz provides a low-voltage and edge- sensing ? zero ? power cmos pld solution with ? zero ? standby power (5 a typical). the atf22lv10cz/cqz powers down automatically to the zero power mode through atmel ? s patented input transition detection (itd) circuitry when the device is idle. the atf22lv10cz/cqz is capable of operating at supply voltages down to 3.0v. pin ? keeper ? circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. the ? cqz ? combines this low high-frequency i cc of the ? q ? design with the ? z ? feature. the atf22lv10cz/cqz macrocell incorporates a variable product term architecture. each output is allocated from 8 to 16 product terms which allows highly complex logic func- tions to be realized. two additional product terms are included to provide synchronous reset and asynchronous reset. these additional product terms are common to all 10 registers and are automatically cleared upon power-up. register preload simplifies testing. a security fuse prevents unauthorized copying of programmed fuse patterns. absolute maximum ratings* temperature under bias .................................. -40 c to +85 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming .....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) dc and ac operating conditions commercial industrial operating temperature (ambient) 0 c - 70 c-40 c - 85 c v cc power supply 3.0v - 5.5v 3.0v - 5.5v atf22lv10c(q)z 3 functional logic diagram description the functional logic diagram describes the atf22lv10cz/cqz architecture. the atf22lv10cz/cqz has 12 inputs and 10 i/o macro- cells. each macrocell can be configured into one of four output configurations: active high/low or registered/combi- natorial. the universal architecture of the atf22lv10cz/cqz can be programmed to emulate most 24-pin pal devices. unused product terms are automatically disabled by the compiler to decrease power consumption. a security fuse, when programmed, protects the contents of the atf22lv10cz/cqz. eight bytes (64 fuses) of user signa- ture are accessible to the user for purposes such as storing project name, part number, revision or date. the user signature is accessible regardless of the state of the security fuse. notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. for dc characterization, the test condition of v cc = max corresponds to 3.6v. dc characteristics symbol parameter condition (2) min typ max units i il input or i/o low leakage current 0 v in v il (max) -10.0 a i ih input or i/o high leakage current (v cc - 0.2)v v in v cc 10.0 a i cc clocked power supply current v cc = max outputs open, f = 15 mhz cz-25 com. 50.0 85.0 ma cz-25 ind. 55.0 90.0 ma cqz-25 com. 18.0 50.0 ma cqz-25 ind. 19.0 60.0 ma i sb power supply current, standby v cc = max v in = max outputs open cz-25 com. 3.0 25.0 a cz-25 ind. 4.0 50.0 a cqz-25 com. 3.0 25.0 a cqz-25 ind. 4.0 50.0 a i os (1) output short circuit current v out = 0.5v -130.0 ma v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc + 0.75 v v ol output low voltage v in = v ih or v il v cc = min, i ol = 16 ma com. 0.5 v ind. v oh output high voltage v in = v ih or v il v ccio = min, i oh = -2.0 ma 2.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v atf22lv10c(q)z 4 ac waveforms note: 1. see ordering information for valid part numbers. inputs, i/o reg. feedback synch. preset cp asynch. reset registered outputs combinatorial outputs valid valid valid valid valid valid output disabled output disabled ts th tw tw tp tar taw tap tco tpd ter tea tea ter ac characteristics (1) symbol parameter -25 -30 units min max min max t pd input or feedback to non-registered output 3.0 25.0 10.0 30.0 ns t cf clock to feedback 13.0 10.0 15.0 ns t co clock to output 2.0 15.0 4.0 20.0 ns t s input or feedback setup time 15.0 18.0 ns t h input hold time 0 0 ns t p clock period 25.0 30.0 ns t w clock width 12.5 15.0 ns f max external feedback 1/(t s + t co ) internal feedback 1/(t s + t cf ) no feedback 1/(t p ) 33.3 35.7 40.0 25.0 30.0 33.3 mhz mhz mhz t ea input to output enable 3.0 25.0 10.0 30.0 ns t er input to output disable 3.0 25.0 10.0 30.0 ns t ap input or i/o to asynchronous reset of register 3.0 25.0 10.0 3.0 ns t sp setup time, synchronous preset 15.0 20.0 ns t aw asynchronous reset width 25.0 30.0 ns t ar asynchronous reset recovery time 25.0 30.0 ns t spr synchronous preset to clock recovery time 15.0 20.0 ns atf22lv10c(q)z 5 input test waveforms and measurement levels output test loads note: similar competitors devices are specified with slightly different loads. these load differences may affect output signals ? delay and slew rate. atmel devices are tested with sufficient margins to meet compatible device specifi- cation conditions. notes: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. power-up reset the registers in the atf22lv10cz/cqz are designed to reset during power-up. at a point delayed slightly from v cc crossing v rst , all registers will be reset to the low state. the output state will depend on the polarity of the buffer. this feature is critical for state machine initialization. however, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic and start below 0.7v. 2. the clock must remain stable during t pr . 3. after t pr , all input and feedback setup times must be met before driving the clock pin high. preload of register outputs the atf22lv10cz/cqz ? s registers are provided with cir- cuitry to allow loading of each register with either a high or a low. this feature will simplify testing since any state can be forced into the registers to control test sequencing. a jedec file with preload is generated when a source file with vectors is compiled. once downloaded, the jedec file preload sequence will be done automatically by most of the approved programmers after the programming. electronic signature word there are 64 bits of programmable memory that are always available to the user, even if the device is secured. these bits can be used for user-specific data. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf22lv10cz/cqz fuse patterns. once pro- grammed, fuse verify and preload are inhibited. however, the 64-bit user signature remains accessible. the security fuse should be programmed last, as its effect is immediate. programming/erasing programming/erasing is performed using standard pld programmers. see cmos pld programming hardware & software support for information on software/ programming. pin capacitance f = 1 mhz, t = 25 c (1) typ max units conditions c in 58 pf v in = 0v c i/o 68 pf v out = 0v parameter description typ max units t pr power-up reset time 600 1000 ns v rst power-up reset voltage 2.3 2.7 v atf22lv10c(q)z 6 input and i/o pin keepers all atf22lv10cz/cqz family members have internal input and i/o pin-keeper circuits. therefore, whenever inputs or i/os are not being driven externally, they will maintain their last driven state. this ensures that all logic array inputs and device outputs are at known states. these are relatively weak active circuits that can be easily overridden by ttl- compatible drivers (see input and i/o diagrams below). input diagram i/o diagram 100k v cc esd protection circuit input 100k v cc v cc data oe i/o input atf22lv10c(q)z 7 functional logic diagram atf22lv10cz/cqz atf22lv10c(q)z 8 atf22lv10cz/cqz standby current vs. supply voltage (t a = 25c) 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 3.00 3.30 3.60 v cc (v) i cc (a) atf22lv10cz supply current vs. input frequency (v cc = 3.3v, t a = 25c) 0.000 10.000 20.000 30.000 40.000 50.000 60.000 0 0.5 2.5 5 7.5 10 25 37.5 50 frequency (mhz) i cc (ma) atf22lv10cz/cqz source current vs. supply voltage (v oh = 2.4v) -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 3.0 3.2 3.3 3.5 3.6 supply voltage (v) ioh (ma) atf22lv10cz/cqz output sink current vs. supply voltage (v ol = 0.5v) 32.0 33.0 34.0 35.0 36.0 37.0 38.0 39.0 40.0 3.03.23.33.53.6 supply voltage (v) i ol (ma) normalized i cc vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized i cc ATF22LV10CQZ supply current vs. input frequency (v cc = 3.3v, t a = 25c) 0.000 5.000 10.000 15.000 20.000 25.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) atf22lv10c/cz output source current vs. output voltage (v cc = 3.3v, t a = 25c) -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.02.22.42.62.83.03.23.3 voh (v) ioh (ma) atf22lv10cz/cqz output sink current vs. output voltage (v cc = 3.3v, t a = 25c) 0.0 20.0 40.0 60.0 80.0 100.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.30 vol (v) iol (ma) atf22lv10c(q)z 9 atf22lv10cz/cqz input clamp current vs. input voltage (v cc = 3.3v, t a = 25 c) -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input curren t (ma) normalized t pd vs. v cc 0.8 0.9 1.0 1.1 1.2 3.0 3.2 3.3 3.5 3.6 supply voltage (v) normalized t pd normalized t co vs. v cc 0.8 0.9 1.0 1.1 1.2 3.03.23.33.53.6 supply voltage (v) normalized t co normalized t su vs. v cc 0.8 0.9 1.0 1.1 1.2 3.03.23.33.53.6 supply voltage (v) normalized t su atf22lv10cz/cqz input current vs. input voltage (v cc = 3.3v, t a = 25 c) -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 input voltage (v) input curren t (a) normalized t pd vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd normalized t co vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co atf22lv10c(q)z 10 22lv10cz/cqz delta t pd vs. output loading -5.0 0.0 5.0 10.0 15.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 output loading (pf) delta t pd (ns) delta t pd vs. # of output switching -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) 22lv10cz/cqz delta t co vs. output loading -5.0 0.0 5.0 10.0 15.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 output loading (pf) delta t co (ns) delta t co vs. # of output switching -0.3 -0.2 -0.2 -0.1 -0.1 0.0 1.02.03.04.05.06.07.08.09.010.0 number of outputs switching delta t co (ns) atf22lv10c(q)z 11 using ? c ? product for industrial to use commercial product for industrial temperature ranges, simply de-rate i cc by 15% on the ? c ? device. no speed de-rating is necessary. ordering information t pd (ns) t s (ns) t co (ns) ordering code package operation range 25 15 15 atf22lv10cz-25jc atf22lv10cz-25pc atf22lv10cz-25sc atf22lv10cz-25xc 28j 24p3 24s 24x commercial (0 c to 70 c) atf22lv10cz-25ji atf22lv10cz-25pi atf22lv10cz-25si atf22lv10cz-25xi 28j 24p3 24s 24x industrial (-40 c to +85 c) ATF22LV10CQZ-30jc ATF22LV10CQZ-30pc ATF22LV10CQZ-30sc ATF22LV10CQZ-30xc 28j 24p3 24s 24x commercial (0 c to 70 c) ATF22LV10CQZ-30ji ATF22LV10CQZ-30pi ATF22LV10CQZ-30si ATF22LV10CQZ-30xi 28j 24p3 24s 24x industrial (-40 c to +85 c) package type 28j 28-lead, plastic j-leaded chip carrier (plcc) 24p3 24-pin, 0.300" wide, plastic dual inline package (pdip) 24s 24-lead, 0.300" wide, plastic gull wing small outline (soic) 24x 24-lead, 4.4 mm wide, plastic thin shrink small outline (tssop) atf22lv10c(q)z 12 packaging information .045(1.14) x 45 pin no. 1 identify .032(.813) .026(.660) .050(1.27) typ .300(7.62) ref sq .045(1.14) x 30 - 45 .022(.559) x 45 max (3x) .012(.305) .008(.203) .021(.533) .013(.330) .430(10.9) .390(9.91) sq .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .456(11.6) .450(11.4) .495(12.6) .485(12.3) sq sq 1.27(32.3) 1.25(31.7) pin 1 .266(6.76) .250(6.35) .090(2.29) max .005(.127) min .070(1.78) .020(.508) .023(.584) .014(.356) .065(1.65) .040(1.02) .325(8.26) .300(7.62) 0 15 ref .400(10.2) max .012(.305) .008(.203) .110(2.79) .090(2.29) .151(3.84) .125(3.18) seating plane .200(5.06) max 1.100(27.94) ref .020(.508) .013(.330) .299(7.60) .291(7.39) .420(10.7) .393(9.98) .105(2.67) .092(2.34) .050(1.27) bsc .616(15.6) .598(15.2) .012(.305) .003(.076) .013(.330) .009(.229) .050(1.27) .015(.381) 8 0 ref pin 1 id *controlling dimension: millimeters 28j, 28-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ab 24p3, 24-pin, 0.300" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-001 af 24s, 24-lead, 0.300" wide, plastic gull wing small outline (soic) dimensions in inches and (millimeters) 24x, 24-lead, 4.4 mm wide, plastic thin shrink small outline (tssop) dimensions in millimeters and (inches)* ? atmel corporation 2000. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard war- ranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectu al prop- erty of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex france tel (33) 4-4253-6000 fax (33) 4-4253-6001 atmel smart card ics scottish enterprise technology park east kilbride, scotland g75 0qr tel (44) 1355-803-000 fax (44) 1355-242-743 atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex france tel (33) 4-7658-3000 fax (33) 4-7658-3480 fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. 0779j ? 11/00/xm marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. terms and product names in this document may be trademarks of others. |
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