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ordering number : en * 5083 40695th (ot) no. 5083-1/31 overview the lc321667bj series is a cmos dynamic ram operating on a single 5 v power source and having a 65536 words 16 bits configuration. equipped with large capacity capabilities, high speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. address input utilizes a multiplexed address bus which permits it to be enclosed in a compact plastic package of 40-pin soj. refresh rates are within 4 ms with 256 row address (a0 to a7) selection and support row address strobe (ras)-only refresh, column address strobe (cas)-before-ras refresh and hidden refresh settings. there are functions such as extended data out (edo) page mode, read-modify-write and byte write. features 65536 words 16 bits configuration. single 5 v 10% power supply. all input and output (i/o) ttl compatible. supports edo page mode, read-modify-write and byte write. supports output buffer control using early write and output enable (oe) control. 4 ms refresh using 256 refresh cycles. supports ras-only refresh, cas-before-ras refresh and hidden refresh. packages soj 40-pin plastic package (400 mil): lc321667bj sop 40-pin plastic package (525 mil): lc321667bm tsop 44-pin plastic package (400 mil): lc321667bt ras access time/column address access time/cas access time/cycle time/power dissipation. package dimensions unit: mm 3200-soj40 ii preliminary sanyo: soj40 ii [lc321667bj] lc321667bj, bm, bt-70/80 sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 1 meg (65536 words 16 bits) dram edo page mode byte write cmos lsi any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. parameter lc321667bj, bm, bt-70 lc321667bj, bm, bt-80 ras access time 70 ns 80 ns column address access time 40 ns 45 ns cas access time 25 ns 25 ns cycle time 125 ns 135 ns power consumption (max) during operation 688 mw 633 mw during standby 5.5 mw (cmos level)/11 mw (ttl level)
pin assignments no. 5083- 2 /31 lc321667bj, bm, bt-70/80 p ac ka g e dimensions unit: mm 3195-sop40 sanyo: sop40 [lc321667bm] p ac ka g e dimensions unit: mm 3207-tsop44 ii sanyo: tsop44 ii [lc321667bt]
block diagram specifications absolute maximum ratings note: 1. stresses greater than the above listed maximum values may result in damage to the device. dc recommended operating ranges at ta = 0 to +70 c note: 2. all voltages are referenced to v ss . a bypass capacitor of about 0.1 f should be connected between v cc and v ss of the device. * 1: ?.0 v when pulse width is less than 20 ns. no. 5083- 3 /31 lc321667bj, bm, bt-70/80 parameter symbol ratings unit note maximum supply voltage v cc max ?.0 to +7.0 v 1 input voltage v in ?.0 to +7.0 v 1 output voltage v out ?.0 to +7.0 v 1 operating temperature range topr 0 to +70 c 1 storage temperature range tstg ?5 to +150 c 1 allowable power dissipation lc321667bj, bm-70/80 pd max 800 mw 1 lc321667bt-70/80 700 output short-circuit current i out 50 ma 1 parameter symbol min typ max unit note power supply voltage v cc 4.5 5.0 5.5 v 2 input high level voltage v ih 2.4 6.5 v 2 input low level voltage v il ?.0 * 1 +0.8 v 2 (a0 to a7, ras, cas, uw, lw, oe) input low level voltage (i/o1 to i/o16) v il ?.5 * 1 +0.8 v 2
dc electrical characteristics at ta = 0 to +70 c, v cc = 5 v 10% note: 3. all current values are measured at minimum cycle rate. since current flows immoderately, if cycle time is longer than shown her e, current value becomes smaller. 4. i cc1 and i cc4 are dependent on output loads. maximum values for i cc1 and i cc4 represent values with output open. 5. address change is less than or equal to one time during ras = v il . concerning i cc4 , it is less than or equal to one time during 1 cycle (t pc ). ac electrical characteristics at ta = 0 to +70 c, v cc = 5 v 10% (note 6, 7 and 8) no. 5083- 4 /31 lc321667bj, bm, bt-70/80 parameter symbol conditions lc321667 lc321667 unit note bj, bm, bt-70 bj, bm, bt-80 min max min max operating current i cc1 ras, cas, address cycling: t rc = t rc min 125 115 ma 3, 4, 5 (average current during operation) standby current i cc2 ras = cas = v ih 2 2 ma ras-only refresh current i cc3 ras cycling, cas = v ih : t rc = t rc min 125 115 ma 3, 5 edo page mode current i cc4 ras = v il , cas, address cycling: t pc = t pc min 110 100 ma 3, 4, 5 standby current i cc5 ras = cas = v cc ?0.2 v 1 1 ma cas-before-ras refresh current i cc6 ras, cas cycling: t rc = t rc min 125 115 ma 3 input leakage current i il 0 v v in 6.5 v, pins other than test pin = 0 v ?0 +10 ?0 +10 a output leakage current i ol d out disable, 0 v v out 5.5 v ?0 +10 ?0 +10 a output high level voltage v oh i out = ?.5 ma 2.4 2.4 v output low level voltage v ol i out = 2.1 ma 0.4 0.4 v lc321667bj, bm, bt-70 lc321667bj, bm, bt-80 parameter symbol min max min max unit note random read or write cycle time t rc 125 135 ns read-write/read-modify-write cycle time t rwc 170 180 ns edo page mode cycle time t pc 35 40 ns edo page mode read-write/read-modify-write cycle time t prwc 85 90 ns ras access time t rac 70 80 ns 9, 14, 15 cas access time t cac 25 25 ns 9, 14 column address access time t aa 40 45 ns 9, 15 cas precharge access time t cpa 45 50 ns 9 output low-impedance time from cas low t clz 0 0 ns 9 output buffer turn-off delay time from ras or cas t off 0 20 0 20 ns 10, 17 rise and fall time t t 2.5 50 2.5 50 ns ras precharge time t rp 45 45 ns ras pulse width t ras 70 10000 80 10000 ns ras pulse width for edo page mode cycle only t rasp 70 100000 80 100000 ns ras hold time t rsh 20 25 ns cas hold time t csh 60 70 ns cas pulse width t cas 20 10000 25 10000 ns ras to cas delay time t rcd 20 45 20 55 ns 14 ras to column address delay time t rad 15 30 15 35 ns 15 cas to ras precharge time t crp 10 10 ns cas precharge time t cp 10 10 ns row address setup time t asr 0 0 ns row address hold time t rah 10 10 ns column address setup time t asc 0 0 ns column address hold time t cah 15 15 ns column address hold time referenced to ras t ar 50 55 ns column address to ras lead time t ral 25 30 ns read command setup time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 11 read command hold time referenced to ras t rrh 0 0 ns 11 write command hold time t wch 15 15 ns write command hold time referenced to ras t wcr 50 55 ns write command pulse width t wp 15 15 ns continued on next page.
continued from preceding page. input/output capacitance at ta = 25 c, f = 1 mhz, v cc = 5 v 10% note: 6. an initial pause of 200 s is required after power-up followed by eight ras-only refresh cycles before proper device operation is achieved. in case of using refresh counter, a minimum of eight cas-before-ras refresh cycles instead of eight ras-only refresh cycles are require d. 7. measured at t t = 2.5 ns. 8. when measuring input signal timing, v ih (min) and v il (max) are used for reference points. in addition, rise and fall time are defined between v ih and v il . 9. measured using an equivalent of 50 pf and one standard ttl loads. 10. t off (max) and t oez (max) are defined as the time until output voltage can no longer be measured when output switches to a high impedance condition. 11. operation is guaranteed if either t rrh or t rch is satisfied. 12. these parameters are measured from the falling edge of cas for an early-write cycle, and from the falling edge of uw and lw for a read- write/read-modify-write cycle. 13. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters for memory in that they specify the operating mode. if t wcs 3 t wcs (min), the cycle switches to an early-write cycle and output pins switch to high impedance throughout the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min) for fast page mode cycle only, the cycle switches to a read-write/read-modify-write cycle and data output equal information in the selected cells. if neither of the above timings are satisfied, output pins are in an undefined state. 14. t rcd (max) is not a restrictive operating parameter but instead represents the point at which the access time t rac (max) is guaranteed. if t rcd 3 t rcd (max), access time is determined according to t cac . 15. t rad (max) is not a restrictive operating parameter but instead represents the point at which the access time t rac (max) is guaranteed. if t rad 3 t rad (max), access time is determined according to t aa . 16. operation is guaranteed if either t dzc or t dzo is satisfied. 17. t off is referenced from the rising edge of ras or cas, whichever occurs last. no. 5083- 5 /31 lc321667bj, bm, bt-70/80 parameter symbol min max unit note input capacitance (a0 to a7, ras, cas, uw, lw, oe) c in 7 pf input/output capacitance (i/o1 to i/o16) c i/o 7 pf lc321667bj, bm, bt-70 lc321667bj, bm, bt-80 parameter symbol min max min max unit note write command to ras lead time t rwl 20 20 ns write command to cas lead time t cwl 20 20 ns data input setup time t ds 0 0 ns 12 data input hold time t dh 15 15 ns 12 data input hold time referenced to ras t dhr 50 55 ns refresh time t ref 4 4 ms write command setup time t wcs 0 0 ns 13 cas to uw or lw delay time t cwd 45 45 ns 13 ras to uw or lw delay time t rwd 90 100 ns 13 column address to uw or lw delay time t awd 60 65 ns 13 cas precharge uw or lw delay time for 70 edo page mode cycle only t cpwd 65 70 ns 13 cas setup time for cas-before-ras t csr 10 10 ns cas hold time for cas-before-ras t chr 10 10 ns ras precharge cas active time t rpc 10 10 ns cas precharge time for cas-before-ras counter test t cpt 40 40 ns ras hold time referenced to oe t roh 15 15 ns oe access time t oea 25 25 ns 9 oe delay time t oed 15 15 ns oe output buffer turn-off delay time t oez 0 15 0 15 ns 10 oe command hold time t oeh 20 20 ns oe setup time to cas high t och 5 5 ns 16 oe hold time from cas high t cho 10 10 ns 16 oe command pulse width t oep 10 10 ns data output hold time t doh 5 5 ns we output buffer turn-off delay time t wez 0 15 0 15 ns data input to cas delay time t dzc 0 0 ns 16 data input to oe delay time t dzo 0 0 ns 16 masked write setup time t mcs 0 0 ns masked write hold time referenced to ras t mrh 0 0 ns masked write hold time referenced to cas t mch 0 0 ns
timing chart read cycle no. 5083- 6 /31 lc321667bj, bm, bt-70/80
early write cycle no. 5083- 7 /31 lc321667bj, bm, bt-70/80
upper byte early write cycle no. 5083- 8 /31 lc321667bj, bm, bt-70/80
lower byte early write cycle no. 5083- 9 /31 lc321667bj, bm, bt-70/80
write cycle (oe control) no. 5083- 10 /31 lc321667bj, bm, bt-70/80
upper byte write cycle (oe control) no. 5083- 11 /31 lc321667bj, bm, bt-70/80
lower byte write cycle (oe control) no. 5083- 12 /31 lc321667bj, bm, bt-70/80
read-modify write cycle no. 5083- 13 /31 lc321667bj, bm, bt-70/80
read-modify upper byte write cycle no. 5083- 14 /31 lc321667bj, bm, bt-70/80
read-modify lower byte write cycle no. 5083- 15 /31 lc321667bj, bm, bt-70/80
edo page mode read cycle no. 5083- 16 /31 lc321667bj, bm, bt-70/80
edo page mode early write cycle no. 5083- 17 /31 lc321667bj, bm, bt-70/80
edo page mode upper byte early write cycle no. 5083- 18 /31 lc321667bj, bm, bt-70/80
edo page mode lower byte early write cycle no. 5083- 19 /31 lc321667bj, bm, bt-70/80
edo page mode read-modify-write cycle no. 5083- 20 /31 lc321667bj, bm, bt-70/80
edo page mode read-modify upper byte write cycle no. 5083- 21 /31 lc321667bj, bm, bt-70/80
edo page mode read-modify lower byte write cycle no. 5083- 22 /31 lc321667bj, bm, bt-70/80
edo page mode read early write cycle no. 5083- 23 /31 lc321667bj, bm, bt-70/80
edo page mode read upper byte early write cycle no. 5083- 24 /31 lc321667bj, bm, bt-70/80
edo page mode read lower byte early write cycle no. 5083- 25 /31 lc321667bj, bm, bt-70/80
hidden refresh cycle no. 5083- 26 /31 lc321667bj, bm, bt-70/80
ras-only refresh cycle cas-before-ras refresh cycle no. 5083- 27 /31 lc321667bj, bm, bt-70/80
cas-before-ras refresh counter test cycle (read) no. 5083- 28 /31 lc321667bj, bm, bt-70/80
cas-before-ras refresh counter test cycle (write) no. 5083- 29 /31 lc321667bj, bm, bt-70/80
cas-before-ras refresh counter test cycle (read-modify-write) no. 5083- 30 /31 lc321667bj, bm, bt-70/80
no. 5083- 31 /31 lc321667bj, bm, bt-70/80 this catalog provides information as of august, 1998. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any and all sanyo products described or contained herein fall under strategic products (including services) controlled under the foreign exchange and foreign trade control law of japan, such products must not be exported without obtaining export license from the ministry of international trade and industry in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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