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10-bit 2.2 gsps adc evaluation board - AT84AS008-EB ............... ................ ................. ................ ................. ............. user guide

AT84AS008-EB - evaluation board user guide i 0906c?bdc?10/07 table of contents section 1 overview ............. ................ .............. ............... .............. .............. ......... 1-1 1.1 description ................................................................................................1-1 1.2 AT84AS008-EB evaluation board ............................................................1-2 1.3 board mechanical characteristics.............................................................1-3 1.4 analog input, clock input and de-embedding fixture accesses ..............1-4 1.5 digital outputs accesses ..........................................................................1-4 1.6 power supplies and ground accesses.....................................................1-4 1.7 adc function setting accesses ...............................................................1-4 section 2 layout information .............. .............. ............... .............. .............. ......... 2-1 2.1 board ........................................................................................................2-1 2.2 ac inputs/digital outputs..........................................................................2-1 2.3 dc function settings ................................................................................2-1 2.4 power supplies .........................................................................................2-2 section 3 operating procedures and characteristics .................. ................ ............... .............. .............. ......... 3-1 3.1 introduction ...............................................................................................3-1 3.2 operating procedure (ecl mode) ............................................................3-1 3.3 use with dmux evaluation board ............................................................3-2 3.4 electrical characteristics...........................................................................3-3 3.5 operating characteristics..........................................................................3-4 section 4 application information ....... .............. ............... .............. .............. ......... 4-1 4.1 introduction ...............................................................................................4-1 4.2 analog inputs ............................................................................................4-1 4.3 clock inputs ..............................................................................................4-1 4.4 setting the digital output data format .....................................................4-1 4.5 adc gain adjust .......................................................................................4-2 4.6 sma connectors and microstrip lines de-embedding fixture .................4-2 4.7 die junction temperature monitoring .......................................................4-3 4.8 decimation function .................................................................................4-5 4.9 pattern generator enable .........................................................................4-5 4.10 data ready output signal reset ..............................................................4-6 4.11 sampling delay adjusting .........................................................................4-6 4.12 test bench description .............................................................................4-7
table of contents ii AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 section 5 package description.... ................. ................ ................. .............. ......... 5-1 5.1 at84as008 pinout ...................................................................................5-1 5.2 thermal characteristics ............................................................................5-3 5.2.1 thermal resistance from junction to ambient: rthja ........................5-3 5.2.2 thermal resistance from junction to case: rthjc .............................5-3 5.2.3 heat sink ............................................................................................5-4 5.3 ordering information .................................................................................5-5 section 6 schematics ................ ................ ................. ................ ................. ......... 6-1 6.1 AT84AS008-EB electrical schematic .......................................................6-1
AT84AS008-EB - evaluation board user guide 1-1 0906c?bdc?10/07 e2v semiconductors sas 2007 section 1 overview 1.1 description the AT84AS008-EB evaluation board is a prototype board which has been designed to facilitate the evaluation and characterization of the at84as008 devi ce (in cbga152) up to its 3.3 ghz full power bandwidth at up to 2.2 gsps in the extended temperature range. the high speed of the at84as008 requires that careful attention be paid to the circuit design and layout so as to achieve the optimal performance. this six metal layer board with an internal ground plane offers functions that enable a quick and simple evaluation of the at84as008 adc?s performances over the temperature range. the at84as008 evaluation board (eb) is very straightforward as it only implements the at84as008 adc device, sma connectors for input/output accesses and a 2.54 mm pitch connector compatible with high-speed acquisition system high-frequency probes. the board has been designed for full compatibil ity with e2v?s dmux evaluation boards (at84cs001-eb). please refer to user gui de reference 0904 and datasheet reference 0809 for more information. the board also implements a de -embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines. it comprises two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in the high frequency domain and extended temperature range. the board?s dimensions are 120 mm 150 mm. the board set comes fully assembled and tested, with the at84as008 installed and fea - tures a heatsink.
overview 1-2 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 1.2 AT84AS008-EB evaluation board figure 1-1. AT84AS008-EB block diagram clk clkb differential clock inputs z0 = 50 ? z0 = 50 ? clk clkb at84as008 vin vinb differential analog inputs z0 = 50 ? z0 = 50 ? vin vinb gain ga sda sda oa sdaen vee test vee b/bg pgeb dr/drb d0/d0b z0 = 50 ? z0 = 50 ? z0 = 50 ? z0 = 50 ? d7/d7b pc/pcb vcc drrb vcc = +5v gnd vplusd gnd = 0v vplusd = -0.8v (ecl) vplusd = 1.45v (lvds) vee dvee diode vee = -5v dvee = -5v or -2.2v j - diode v - diode drrb v-gnd i-gnd cal1 cal2 l = 50 mm typ lvin/vinb = lclk/clkb = 43 mm typ loutputs = 58 mm typ +5v vcc -5v vee gnd -5v or -2.2v dvee
overview AT84AS008-EB - evaluation board user guide 1-3 0906c?bdc?10/07 e2v semiconductors sas 2007 1.3 board mechanical characteristics the board?s layer number, thickness and functions are given in table 1-1, from top to bottom. the AT84AS008-EB is an eleven-layer pcb made of six copper layers and five dielec - tric layers. the six metal layers correspond respectively from top to bottom to the ac and dc signals? layer (layer 1), two ground layers (layers 3 and 5), and one supply layer (layer 7). considering the severe mechanical constraints due to the wide temperature range and the high frequency domain in which the board is to operate, it is necessary to use a ?sandwich? of two different dielectric ma terials, with specific characteristics: ? a low insertion loss ro4003 hydrocarbon/wovenglass dielectric layer 200 m thick, chosen for its low loss (-0.318 db/inch) and enhanced dielectric consistency in the high frequency domain. the ro4003 dielectric layer is dedicated to the routing of the 50 ? impedance signal traces (the ro4003 ty pical dielectric constant is 3.4 at 10 ghz). the ro4003 dielectric layer characteristics are very close to ptfe in terms of insertion loss characteristics ? a bt/epoxy dielectric layer 0.99 mm thick (total) sandwiched between the upper ground plane and the back-side supply layer table 1-1. board?s layer thickness profile layer characteristics layer 1 copper layer thickness of copper = 40 m ac signal traces = 50 ? microstrip lines dc signal traces (b/gb, gain, diode, oa, test, sda) layer 2 ro4003 dielectric layer (hydrocarbon/wovenglass) thickness of layer = 200 m dielectric constant = 3.4 at 10 ghz -0.044 db/inch insertion loss at 2.5 ghz -0.318 db/inch insertion loss at 18 ghz layer 3 copper layer thickness of copper = 39 m ground plane = reference plane 50 ? microstrip return layer 4 bt/epoxy dielectric layer thickness of layer = 330 m layer 5 copper layer thickness of copper = 35 m power and ground planes layer 6 bt/epoxy dielectric layer thickness of layer = 330 m layer 7 copper layer thickness of copper = 35 m power and ground planes (identical to layer 5) layer 8 bt/epoxy dielectric layer thickness of layer = 330 m layer 9 copper layer thickness of copper = 35 m ground planes (identical to layer 3) layer 10 bt/epoxy dielectric layer thickness of layer = 200 m layer 11 copper layer thickness of copper = 35 m power and ground planes
overview 1-4 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 the bt/epoxy layer has been chosen because of its enhanced mechanical characteris - tics for elevated temperature operation. the typical dielectric constant is 4.5 at 1 mhz. more specifically, the bt/e poxy dielectric layer offers enhanced characteristics com - pared to fr4 epoxy, namely: ? higher operating temperature values: 170 c (125 c for fr4) ? higher resistance to thermal shocks (-65 c up to 170 c) the total thickness of the board is 1.6 mm. the previously-described mechanical and frequency characteristics make the board part icularly suitable for device evaluation and characterization in the high frequency domain and in military temper ature ranges. 1.4 analog input, clock input and de-embedding fixture accesses the differential active inputs (analog, clock, de-embedding fixture) are provided by sma connectors. reference: vitelec 142-0701-851. connector mounting plates have been used to fasten the sma connectors. 1.5 digital outputs accesses access to the differential output data port is provided by a 2.54 mm pitch connector, compatible with the high-speed digital acquisi tion system. it provides access to the con - verter output data, as well as proper 50 ? differential termination. 1.6 power supplies and ground accesses the power supply accesses are provided by five 2 mm section banana jacks respec - tively for dv ee , v plusd and v cc . the power supply access is provided by one 4 mm section banana jack for v ee . the ground accesses are provided by four 2 mm and one 4 mm banana jacks. 1.7 adc function setting accesses for adc function setting accesses (b/gb, die junction temp., test), 2 mm section banana jacks are provided. three potentiometers are provided for adc gain, sampling delay and offset adjustments. one sub-screw is provided for asynchronous data ready reset. note: oa refers to sdaen test refers to pgeb pc/pcb refers to or/orb
AT84AS008-EB - evaluation board user guide 2-1 0906c?bdc?10/07 e2v semiconductors sas 2007 section 2 layout information 2.1 board the at84as008 requires appropriate board layout for optimum full-speed operation. the following explains the board layout recommendations and demonstrates how the evaluation board fulfills thes e implementation constraints. a single low impedance ground plane is recommended, since it allows the user to lay out signal traces and power planes wi thout interrupting the ground plane. a multi-layer board structure has therefore been retained for the AT84AS008-EB. six copper metal layers are used, dedicated to the signal traces, ground planes and power supplies respectively (from top to bottom). 2.2 ac inputs/digital outputs the board uses 50 ? impedance microstrip lines for the differential analog inputs, clock inputs, and differential digital outputs. the input signals and clock signals must be routed on one layer only, without use of any through-hole vias. the line lengths are matched to within 2 mm. the digital output lines are 50 ? differentially terminated. the output data trace lengths are matched to 1 mm to minimize the data output delay skew. for the AT84AS008-EB the propagation delay is approximately 6.1 ps/mm (155 ps/inch). the ro4003 typical dielectric constant is 3.4 at 10 ghz. for more information about different output termination options refer to the specification application note entitled ?input/output termination techniques? (reference 2169). 2.3 dc function settings the dc signal traces are low impedance. they have been routed with a 50 ? impedance near the device because of space restriction.
layout information 2-2 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 2.4 power supplies the bottom metal layers 5, 7 and 11 are dedicated to power supply traces (v ee , dv ee , v plusd and v cc ). the supply traces are approximately 6 mm wide in order to present low impedance, and are surrounded by a ground plane connected to the two inner ground planes. no difference in adc high-speed performance has been observed when connecting both negative supply planes together. obviou sly one single negative supply plane could be used for the circuit. each incoming power supply is bypassed by a 1 f tantalum capacitor in parallel with 1 nf chip capacitor. each power supply access is decoupled very close to the device by 10 nf and 100 pf surface-mount chip ca pacitors in parallel. note: the decoupling capacitors are superposed. in this configuration, the 100 pf capacitors must be mounted first.
AT84AS008-EB - evaluation board user guide 3-1 0906c?bdc?10/07 e2v semiconductors sas 2007 section 3 operating procedures and characteristics 3.1 introduction this section describes a typical single-ended configuration for the analog and clock inputs. the single-ended configuration is preferable, as it corresponds to the most straightfor - ward and quickest AT84AS008-EB board setti ng for evaluating the at84as008 at full speed in its given temperature range. the inverted analog input v inb and clock input clkb common mode level is ground (on- chip 50 ? -terminated). in this configuration, no balun transformer is needed to correctly convert the single-ended mixer output to balan ced differential signals for the analog inputs. in the same way, no balun is necessary to feed the at84as008 clock inputs with bal - anced signals. the rf sources should be directly connected to the in-phase analog and clock inputs of the converter. however, dynamic performanc es can be somewhat improved by entering either analog or clock inputs in differential mode. 3.2 operating procedure (ecl mode) 1. connect the power supplies and ground accesses (v cc = +5v, gnd = 0v, v plusd = 0v, v ee = -5v, dv ee = -5v or -2.2v) through the dedicated banana jacks. we recommend you turn the -5v power supply on first (followed by -2.2v if appli - cable, followed by 5v). 2. the board is set to default digital outputs in binary format. 3. connect the clk clock signal. the inverted phase clock input clkb may be 50 ? terminated. use a low phase noise rf source. the clock input level is typically 4 dbm and should not exceed +10 dbm into the 50 ? termination resistor (maxi - mum ratings for the clock input power level is 15 dbm). 4. connect the analog signal v in . the inverted phase clock input v inb may be 50 ? terminated. use a low phase noise rf source. the full-scale range is 0.5v peak- to-peak around 0v (250 mv) or -2 dbm into 50 ? . the input frequency can range from dc up to 1.8 ghz. at 3.3 ghz, the adc attenuates the input signal by -3 db.
operating procedures and characteristics 3-2 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 5. connect the high-speed data acquisition system probes to the output connector. the connector pitch (2.54 mm) is compatible with high-speed digital acquisition system probes. the digital data is on-board differentially terminated. however, the output data can be picked up either in single-ended or differential mode. 3.3 use with dmux evaluation board the at84cs001-eb dmux eval uation board has been designed for full compatibility with the AT84AS008-EB adc evaluation board. the demux input configuration has been optimized for connection with the at84as008 adc (cbga152 package). for correct operation, when using the dmux board with the adc board, do not forget to set clkintype to dr/2 mo de (jumper on-board). the power-up sequence should be: 1. supply the adc 2. supply the dmux 3. perform an asynchronous reset on the dmux board when this power-up sequence has been completed, synchronization between the dmux and adc boards can be achieved via the clkdactrl potentiometers on the dmux evaluation board. to correctly synchronize the two boards, we recommend that you run the adc at its full-speed (maximum sampling rate) and tune the dmux delay adjust control potentiometer to the left, noting the settings at which the boards are de- synchronized, and similarly tune the potentiome ter to the right to identify the point of loss of synchronization at the other extrem ity. the correct potentiometer setting should be half-way between these two settings and should be accurate for all sampling rates of the adc. when used with the at84cs001, then there are two solutions: ? v plusd = 1.45v and dv ee = -5v (or -2.2v, for power saving) ? v plusd = 2.5v and dv ee = -2.2v
operating procedures and characteristics AT84AS008-EB - evaluation board user guide 3-3 0906c?bdc?10/07 e2v semiconductors sas 2007 3.4 electrical characteristics note: absolute maximum ratings are limiting values (referenced to gnd = 0v), to be applied individually, while other parameters are within specified operating conditions. long exposure to maximum ratings may affect device reliability. the use of a thermal hea t sink is mandatory. table 3-1. absolute maximum ratings parameter symbol comments value unit positive supply voltage v cc gnd to 6.0 v digital negative supply voltage dv ee gnd to -5.5 or -2.2v v digital positive supply voltage v plusd gnd -1.1 to 2.5 v negative supply voltage v ee gnd to -5.5 v maximum difference between negative supply voltages dv ee to v ee 0.3 v maximum difference between v plusd and d vee v plusd - d vee 7 v analog input voltages v in or v inb -1.5 to +1.5 v maximum difference between v in and v inb v in - v inb -1.5 to +1.5 v clock input common mode voltage (v clk + v clkb )/2 -1.5 to +0.6 v maximum difference between v clk and v clkb v clk - v clkb -1 to +1 v static input voltage v d ga/sda -1 to +0.8 v digital input voltage v d sdaen, drrb, b/gb, pgeb -5 to +0.8 v digital output voltage v o v plusd -2.2 to v plusd +0.8 v maximum junction temperature t j +130 c storage temperature t stg -65 to +150 c lead temperature (soldering 10s) t leads +300 c
operating procedures and characteristics 3-4 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 3.5 operating characteristics the power supplies denoted by v cc , v ee , dv ee and v plusd are dedicated to the at84as008 adc. the power supplies denoted by v eet , v dd are dedicated to the optional mc100el16 asynchronous differential receivers. note: 1. if the adc is used with the at84cs001-eb dmux evaluation board, v plusd can be set to 2.5v so that the same supply can be used for v plusd (adc) and v plusd (dmux). in this case, dv ee must be set to -2.2v. 2. to save power, dv ee can be set to -2.2v. in this case, v plusd must be either 1.5v or 2.5v. table 3-2. electrical operating characteristics parameter symbol value unit min typ max positive supply voltage (dedicated to at84as008 adc only) v cc 4.75 5 5.25 v v plusd -0.9 1.375 ecl: -0.8 lvds: 1.45 2.5 (1) -0.7 1.525 v v eea -5.25 -5 -4.75 v dv ee -5.25 -2.3 -5 -2.2 (2) -4.75 -2.1 v positive supply current (dedicated to at84as008 adc only) i cc ? 75 100 ma i plusd ? 195 230 ma i ee ? 590 660 ma i eed ? 195 230 ma nominal power dissipation (ecl) pd ? 4.2 4.7 (t j = 125 c) w analog input impedance z in ? 50 ? ? full power analog input bandwidth (-3 db) ? ? 3.3 ? ghz analog input voltage range (differential mode) v in -125 ? 125 mv clock input impedance ? ? 50 ? ? clock input voltage compatibility (single-ended or differential) (see application notes) ? ecl levels or 0 dbm (typ) into 50 ? ? clock input power level into 50 ? termination resistor ? -4 0 4 dbm
AT84AS008-EB - evaluation board user guide 4-1 0906c?bdc?10/07 e2v semiconductors sas 2007 section 4 application information 4.1 introduction for this section, also refer to the product?s ?main features? in the datasheet of the at84as008 device (reference 5404a). more particularly, refer to sections related to sin - gle-ended and differential input configurations. 4.2 analog inputs the analog inputs can be entered in differential or single-ended mode without degrading the high-speed performance of the device. the board digitizes single-ended signals by sele cting either input and leaving the other input open, as the latter is on-board 50 ? terminated. the nominal in-phase inputs are v in (refer to section 3 ). 4.3 clock inputs the clock inputs can be entered in different ial or single-ended mode without degrading performance of the device for a clock frequency up to 500 mhz. at higher rates, we rec - ommend that you drive the clock inputs differentially. moreover, the typical in-phase clock input amplitude is 1v peak-to-peak, centered on 0v (ground), or -1.3v (ecl) in common mode. regarding the analog input, either clock input can be chosen (if the single-ended output mode is used), leaving the other input open, as both clock inputs are on-chip 50 ? termi - nated. the nominal in-phase clock input is clk (refer to section 3 ). 4.4 setting the digital output data format for this section, refer to the evaluation board electrical schematic and to the compo - nents placement document (respectively figure 6-2 on page 6-3 and figure 6-8 on page 6-5). please also refer to the at84as008 datasheet (reference 5404a) for more information on digital output coding. the at84as008 delivers data in natural binary c ode or in gray code. if the b/gb input is left floating or tied to gn d, the data format selected w ill be natural binary, whereas if this input is tied to v ee the data will follow the gray code. use the jumper designated b/gb to select the output data port format: ? if b/gb is left floating or tied to gnd, the data output format is true binary ? if b/gb is tied to v ee or driven with ecl low, the data outputs are in the gray format
application information 4-2 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 the v plusd positive supply voltage is used to adjust the output common mode level from -1.05v (v plusd = -0.8v for ecl output compatibility) to +1.35v (v plusd = 1.45v for lvds output compatibility). each output voltage varies between -0.9v and -1.2v (respectively +1.2v and +1.5v), leading to 0.3v = 660 mv in differential mode for v plusd = -0.8v (respectively 1.45v). 4.5 adc gain adjust the adc gain can be adjusted through pin r9 (pad input impedance is 1 m ? in parallel with 2 pf). a jumper denoted gain has been foreseen in order to provide access to the adc gain adjust pin. the gain potentiometer is dedicated to ad justing the adc gain from approximately 0.85 up to 1.15. the gain adjust transfer function is given below. figure 4-1. adc gain adjust 4.6 sma connectors and microstrip lines de- embedding fixture attenuation in microstrip lines can be found by calculating the difference in the log mag - nitudes of the s21 scattering parameters measured on two different lengths of meandering transmission lines. such a measurement also removes common losses such as those due to transitions and connectors. the s21 scattering parameter corresponds to the amount of power transmitted through a two-port network. the characteristic impedance of the micros trip meander lines must be close to 50 ? to minimize impedance mismatching with the 50 ? network analyzer test ports. impedance mismatching will ca use ripples in the s21 pa rameter accord ing to the degree of mismatch and the length of the line. 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 v ga gain adjust voltage (v) adc gain min typical
application information AT84AS008-EB - evaluation board user guide 4-3 0906c?bdc?10/07 e2v semiconductors sas 2007 4.7 die junction temperature monitoring figure 4-2 and figure 4-3 show the recommended implementation of the die junction temperature monitoring function. there are two possible configurations: 1. the adc decimation test mode is not authorized. due to the use of one internal diode-mounted transistor, you must implement 2 2 head-to-tail protection diodes to avoid potential reverse current flows that may damage the diode pin. note that e2v usually recommends the use of 2 3 head-to-tail protection diodes but in this particular case, it is necessary to have exactly two diodes in the a10 to ground con - duction flow. figure 4-2. recommended die junction temperature monitoring function implemen- tation, test mode not allowed 2. the adc decimation test mode is authorized if you still want to be able to sw itch from normal mode to test mode or to the die junction temperature monitori ng function, the protection diode co nfiguration will be slightly differ - ent and will take into account the fact that the test mode can be activated by applying v ee = -5v to the diode pin. this explains why seven protection diodes are needed in the reverse direction, as described in figure 4-3 . figure 4-3. recommended diode pin implementation providing for both die junction temperature monitoring function and test mode a10 gnd idiode ignd adc pin 1 ma vdiode vgnd v a10 gnd idiode ignd adc pin 1 ma vdiode vgnd v
application information 4-4 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 figure 4-4. diode pin implementation in test mode the expected diode-mounted transistors v diode value (including chip parasitic resis - tance) compared to the junction temperature is given in figure 4-5 (i diode = 1 ma). figure 4-5. junction temperature versus diode voltage for i = 1 ma note: the operating die junction temperature must be kept below 125 c; this requires that an adequate cooling system be set up. a10 gnd adc pin vee = -5v 740 750 760 770 780 790 800 810 820 830 840 850 860 870 880 890 900 910 920 930 940 950 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 diode voltage (mv) junction temperature ( 0 c)
application information AT84AS008-EB - evaluation board user guide 4-5 0906c?bdc?10/07 e2v semiconductors sas 2007 4.8 decimation function the decimation function can be used for initial stage debugging of the adc. this func - tion enables reduction of the adc output rate by 32, thus allowing for a quick debug phase of the adc at maximum speed rate. when active, this function outputs only 1 out of 32 bits of data, thus resulting in a data rate 32 times slower than the clock rate. 4.9 pattern generator enable the at84as008 is able to self-generate (with no analog input signal) a series of pat - terns. if the test input is left floating or tied to gnd, the at84as008 digitizes the analog input signal according to b/gb. if this input is driven with ecl low or tied to v ee , the at84as008 generates checker-board patterns. use the jumper named test to activate the pattern generator. 4.10 data ready output signal reset a sub-screw connector is provided fo r the drrb command. the data ready signal is reset on the fallin g edge of the drrb input command, on ecl logical low level (-1.8v). d rrb may also be tied to v ee = -5v for data ready output sig - nal master reset. as long as drrb remains at a logical low level, (or tied to v ee = -5v), the data ready output remains at logical zero and is independent of the external free running encoding clock. the data ready output signal (dr, drb) is re set to logical zero after trdr = 720 ps typically. trdr is measured between the -1.3v point of the falling edge of the drrb input com - mand and the zero crossing point of the differential data ready output signal (dr, drb). the data ready reset command may be a pulse of 1 ns minimum time width. the data ready output signal restarts on the drrb command?s rising edge, ecl logi - cal high level (-0.8v). drrb may also be grounded, or left floating, for normal free running of the data ready output signal. 4.11 sampling delay adjusting one delay adjust, controlled by the sda poten tiometer, is available in order to add a delay to the adc?s input clock. this allows you to tune the instant of internal sampling. to enable this delay adjustment there is an sdaen pin on the chip. in the current revi - sion, the sdaen function corresponds to the oa labels (oa jumper and oa potentiometer). the oa potentiometer has been re moved and short-circuited to v ee . use the jumper named oa to activate the sampling delay adjustment: ? if oa is left floating or tied to gnd, the sda is disabled ? if oa is tied to v ee , the sda is activated the sda input varies from -0.5 to 0.5v, de pending on the sda?s potentiometer position. the delay variation around its nominal value according to the sda voltage is more or less linear, as shown in figure 4-6 (simulation results).
application information 4-6 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 figure 4-6. sampling delay adjust note: the delay variation according to temperature is insignificant. 4.12 test bench description figure 4-7. differential analog and clock input configuration 400p 300p 200p 100p -500m -400m -300m -200m -100m 100m delay 200m 300m 400m 500m 0m delay in the variable delay cell at 60 c sda (v) rf generator rf generator -121 dbc/hz at 1 khz offset from fc 0 ? 180 hybrid 0 ? 180 hybrid bpf data acquisition system at84as008 adc -117 dbc/hz at 20 khz offset from fc pc gpib clkb clk dr 10 data tunable delay line vinb vin synchro 10 mhz
application information AT84AS008-EB - evaluation board user guide 4-7 0906c?bdc?10/07 e2v semiconductors sas 2007 figure 4-8. single-ended analog and clock input configuration bpf data acquisition system at84as008 adc pc gpib (50 ? ) clkb clk dr 10 data tunable delay line vinb (50 ? ) vin synchro 10 mhz rf generator rf generator
application information 4-8 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007
AT84AS008-EB - evaluation board user guide 5-1 0906c?bdc?10/07 section 5 package description 5.1 at84as008 pinout figure 5-1. at84as008 pinout of cbga152 package (bottom view) note: if required, four nc balls can be electrically connected to gnd to simplify pcb routing. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gnd gnd gnd vplusd vplusd vplusd dvee dvee gnd gnd dvee dvee dvee dvee vplusd gnd vplusd vplusd vplusd vplusd gnd vplusd vee vplusd gnd vee vee vee gnd pgeb vee vee vcc vee vcc vcc gnd vcc gnd gnd vcc gnd vcc gnd gnd gnd veeh vccth vccth gnd gnd vee gnd vee at84as008 cbga152 (cavity down) gnd gnd gnd veeh veeh vccth d9 gnd or d1 d2 dr d4 d5 gnd d3 d6 d7 d8 d9b gnd orb d1b d0 d0b d2b drb d4b d5b gnd d3b d6b d7b d8b vplusd vplusd vplusd vee vee gnd vee vee gnd gnd nc gnd dvee vplusd gnd vee ga vcc gnd vinb vin nc gnd dvee vplusd b/gb decb/ diode vee vcc sda gnd vee gnd vee gnd gnd vee vee vee gnd vee vee gnd gnd nc gnd gnd gnd nc gnd gnd clk clkb veeh veeh vccth vee gnd drrb sdaen gnd gnd gnd gnd ab cde f g h j k l mnp qr ab cde f g h j k l mnp qr
package description 5-2 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 table 5-1. AT84AS008-EB pin description symbol pin number function power supplies v cc k1, k2, j3, k3, b6, c6, a7, b7, c7, p8, q8, r8 +5v analog supply gnd b1, c1, d1, g1, m1, q1, b2, c2, d2, e2, f2, g2, n2, p2, q2, a3, b3 , d3, e3, f3, g3, n3, p4, q4, r4, a5, p5, q5 , p6, q6, p7, q7, r7, b9, b10, b11, r11, p12, a14, b14, c14, g14, k14, p14, q14, r14, b15, q15, b16, q16 analog ground v ee h1, j1, l1, h2, j2, l2, m2, c3, h3, l3, m3, p3, q3, r3, a4, b4, c4, b5 , c5, a8, b8, c8, c9, p9, q9, c10, q10, r10 -5v analog supply v plusd p10, c11, p11, q11, a12, b12, c12, q12, r12, d14, e14, f14, l14, m14, n14 digital positive supply dv ee a13, b13, c13, p13, q13, r13, h14, j14 -5v or -2.2v digital supply analog inputs v in r5 in-phase (+) analog input signal of the differential sample and hold preamplifier v inb r6 inverted phase (-) analog input signal of the differential sample and hold preamplifier clock inputs clk e1 in-phase (+) clock input clkb f1 inverted phase (-) clock input digital outputs d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 d16, e16, f16, g16, j16, k16, l16, m16, n16, p16 in-phase (+) digital outputs d0 is the lsb. d9 is the msb d0b, d1b, d2b, d3b, d4b, d5b, d6b, d7b, d8b, d9b d15, e15, f15, g15, j15, k15, l15, m15, n15, p15 inverted phase (-) digital outputs or c16 in-phase (+) out-of-range output orb c15 inverted phase (-) out-of-range output dr h16 in-phase (+) data ready signal output drb h15 inverted phase (-) data ready signal output additional functions b/gb a11 binary or gray select output format control - binary output format if b/gb is floating or connected to gnd - gray output format if b/gb is driven with ecl low level or b/gb is connected to v ee
package description AT84AS008-EB - evaluation board user guide 5-3 0906c?bdc?10/07 e2v semiconductors sas 2007 5.2 thermal characteristics 5.2.1 thermal resistance from junction to ambient: rthja table 5-2 lists the converter?s thermal performance parameters with no external heat sink added. diode a10 decimation function enable or die junction temperature monitoring: - decimation active when low (die junction temperature monitoring not possible) - normal mode when high or left floating - die junction temperature m onitoring when current is applied pgeb a9 active low pattern generator enable - digitized input delivered at outputs according to b/gb if pgeb is floating or connected to gnd - checkerboard pattern delivered at outputs if pgeb is driven with ecl low level or connected to v ee drrb n1 asynchronous data ready reset function ga r9 gain adjust sda a6 sampling delay adjust sdaen p1 sampling delay adjust enable: - inactive if floating or connected to gnd - active if ecl low or connected to v ee table 5-1. AT84AS008-EB pin description (continued) symbol pin number function table 5-2. thermal resistance air flow (m/s) estimated ja thermal resistance ( c/w) 0 45 figure 5-2. thermal resistance from junction to ambient: rthja 0.5 35.8 1 30.8 1.5 27.4 2 24.9 2.5 23 3 21.5 4 19.3 5 17.7 rthja ( c/w) air flow (m/s) 0 0 10 20 30 40 50 12 345
package description 5-4 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 5.2.2 thermal resistance from junction to case: rthjc the maximum thermal junction-to-case resistance is 4.0 c/watt. this value does not include thermal contact resistance between the package and exter - nal heat sink (glue, paste or thermal foil interface for example). as an example, we will use 2.0 c/w for a 50 m thickness of thermal grease. 5.2.3 heat sink we recommend that you use a 50 50 30 mm heat sink (respectively l l h) when in natural convection-cooling mode (with no air flow). a fan heat sink or direct conduction cooli ng is recommended, due to high power dissipa - tion (4.7w). a cooling method should be chosen that permits less than 4.0 c/w for the case-to- ambient thermal resistance (rthca). the thermal resistance of the board is a high value (within a range of 30 c/w); thus an external heat sink is mandatory. the heat sink must be fixed to the heat spre ader which is at -5v. the heat sink must therefore be electrically isolated usi ng adequate low rth electrical isolation. example: 4.0 c/w rthca (case-to-ambient) + 2.0 c/w thermal grease resistance + 4.0 c/w rthjc = 10.0 c/w total (rthja). the heat sink should be in contact with the package on the side opposite to the balls, in a 8.5 mm diameter circle as shown in figure 5-3 : figure 5-3. cbga152 board assembly the efficiency of the cooling system can be monitored using the temperature sensing diodes integrated in the device. 31 8.5 32.5 board 50.5 20.2 24.2 note: the measures are given in mm.
package description AT84AS008-EB - evaluation board user guide 5-5 0906c?bdc?10/07 e2v semiconductors sas 2007 5.3 ordering information table 5-3. ordering information part number package temperature range screening level comments at84xas008gl cbga 152 ambient prototype prototype version at84as008cgl cbga 152 ?c? grade: 0 c package description 5-6 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007
AT84AS008-EB - evaluation board user guide 6-1 0906c?bdc?10/07 e2v semiconductors sas 2007 section 6 schematics 6.1 AT84AS008-EB electrical schematic figure 6-2 to 6-8 depict the electrical schematic of the AT84AS008-EB. the pinout used for the evaluation board has been translated from e2v's pinout (refer to ?at84as008 pinout of cbga152 package (bottom view)? on page 5-1 ) to the jedec standard shown in figure 6-1. this explains the discrepancies between the pinout used on page 5-1 and the one given in the electrical schematic in figures 6-2 on page 6-2.
schematics 6-2 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 figure 6-1. at84as008 pinout in jedec standard a b c d e f g h j k l m n p q r a b c d e f g h j k l m n p q r gnd gnd gnd vplusd vplusd vplusd dvee dvee gnd gnd dvee dvee dvee dvee vplusd gnd vplusd vplusd vplusd vplusd gnd vplusd vee vplusd gnd vee vee vee gnd pgeb vee vee vcc vee vcc vcc gnd vcc gnd gnd vcc gnd vcc gnd gnd gnd veeh vccth vccth gnd gnd vee gnd vee at84as008 cbga152 (cavity down) gnd gnd gnd veeh veeh vccth d9 gnd or d1 d2 dr d4 d5 gnd d3 d6 d7 d8 d9b gnd orb d1b d0 d0b d2b drb d4b d5b gnd d3b d6b d7b d8b vplusd vplusd vplusd vee vee gnd vee vee gnd gnd nc gnd dvee vplusd gnd vee ga vcc gnd vinb vin nc gnd dvee vplusd b/gb decb/ diode vee vcc sda gnd vee gnd vee gnd gnd vee vee vee gnd vee vee gnd gnd nc gnd gnd gnd nc gnd gnd clk clkb veeh veeh vccth vee gnd drrb sdaen gnd gnd gnd gnd 1 2 3 4 5 6 7 8 9 10111213141516 12345678910111213141516
schematics AT84AS008-EB - evaluation board user guide 6-3 0906c?bdc?10/07 e2v semiconductors sas 2007 figure 6-2. AT84AS008-EB electrical schematic 50 ohms impedance lines same line length 50 ohms impedance lines nc nc nc nc nc nc nc nc gain sda oa clk clkb vi n vinb clk clkb vin vinb b/gb test b/gb test diode diode drrb drrb gain gai n sda oa oa sda pcb pc d0b d1b d1 d2 b d2 d3 b d3 dr b dr d4 d5 b d5 d6b d6 d7 b d7 d8b d8 d9b d9 d0 d4b buf_pcb buf_pc buf_d0b buf_d0 buf_d1b buf_d1 buf_d2b buf_d2 buf_d3b buf_d3 buf_dr b buf_dr buf_d4b buf_d4 buf_d5b buf_d5 buf_d6b buf_d6 buf_d7b buf_d7 buf_d8b buf_d8 buf_d9b buf_d9 vplusd vcc dvee vee vplusd vee vcc dvee vee vee vcc vee vcc vee vee vcc xj 9 c4b 10nf c127 10nf b3 1 xj8 c6 10nf j1 jumper 1 2 3 1 2 3 j8 jumper 1 2 3 1 2 3 c12 10nf c1 100pf c56 100pf c10 10nf c13 10nf b17 1 c20a 10nf ptoa 1 ptb/gb 1 ptsd a 1 s5 vinb 1 2 1 2 r53 3k9 1% c18 10nf r52 0r 5% c125 10nf c3 100pf xj10 cavalier c22a 10nf p2 1k 25 turns j10 jumper 1 2 3 1 2 3 c5 100pf c30b 10nf c55 10nf c20b 10nf st13 1 2 s1 conn smc fc / drrb 1 2 3 4 5 1 2 34 5 c9 100pf c28 10nf c11 100pf j2 jumper 1 2 3 1 2 3 c30a 10nf c128 100pf c17 100pf c32b 10nf p3 1k 25 turns b1 1 c19 100pf c22b 10nf d1 zener 1 2 r50 3k9 1% p ttest 1 c21 100pf c32a 10nf b6 1 r49 3k9 1% c27 100pf c36b 10nf xs4 sma c29 100pf ptgain 1 c42a 10nf s2 clock 1 2 1 2 v1 ts83102g0 a2 a3 a4 a12 a7 a15 b1 b2 b3 b4 b5 b6 b7 b13 b14 b15 b16 c1 c2 c4 c5 c6 c7 c13 d14 d15 d16 e1 e14 e15 f14 f15 g14 g15 g16 j2 k2 l2 l16 m13 p1 p2 p3 p7 p10 p14 p15 p16 q1 q2 q15 q16 r2 r15 a8 a9 a11 b8 b9 b11 b12 c3 c8 c11 c12 c14 c15 c16 d1 d2 d3 e2 e3 h1 h2 h3 j3 j14 j15 k3 k15 k16 a10 b10 c9 c10 f2 f3 g1 g2 g3 h14 h15 h16 k14 l3 l14 l15 m1 m2 m3 m15 m16 p4 p5 p6 p11 p12 p13 n1 n2 n3 n14 n15 n16 p8 p9 q3 r3 q4 r4 q5 r5 q6 r6 q7 r7 q8 r8 q9 r9 q10 r10 q11 r11 q12 r12 q13 r13 q14 r14 a5 a6 a13 a14 e16 f16 f1 j1 j16 k1 l1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd vplusd dvee dvee dvee dvee dvee dvee dvee dvee pcb (orb) pc (or) d0b d0 d1b d1 d2b d2 d3b d3 drb dr d4b d4 d5b d5 d6b d6 d7b d7 d8b d8 d9 b d9 clk clkb drrb oa (sdaen) vin vinb sda test (pgeb) gain diode b/gb c31 100pf r54 3k9 1% c36a 10nf c35 100pf xj2 c38b 10nf r51 0r 5% s8 cal2 1 2 1 2 c37 100pf p1 1k 25 turns c26 100pf c40 10nf xs5 sma xs3 sma c39 100pf b5 1 c46 10nf c126 100pf c25 10nf c41 100pf c129 100nf c38a 10nf c14 100pf b2 1 c45 100pf c42b 10nf s4 vin 1 2 1 2 j7 con2x48 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 49 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 s3 clockb 1 2 1 2 xj 1 c2 10nf s7 cal1 1 2 1 2 xs2 sma b4 1 j9 jumper 1 2 3 1 2 3 c4a 10nf banana jacks
schematics 6-4 AT84AS008-EB - evaluation board user guide 0906c?bdc?10/07 e2v semiconductors sas 2007 figure 6-3. component side description figure 6-4. metal layer 2 and 4: ground planes figure 6-5. metal layer 3 and 3 bis: power supplies and ground planes figure 6-6. metal layer 5: solder side figure 6-7. AT84AS008-EB evaluation board: top view (signal side) with heatsink figure 6-8. AT84AS008-EB evaluation board: bottom view
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