spt7734 8-bit , 40 msps,175 mw a/d converter features ? monolithic 40 msps converter ? 175 mw power dissipation ? on-chip track-and-hold ? single +5 v power supply ? ttl/cmos outputs ? 5 pf input capacitance ? low cost ? tri-state output buffers ? high esd protection: 3,500 v minimum ? selectable +3 v or +5 v logic i/o applications ? all high-speed applications where low power dissipation is required ? video imaging ? medical imaging ? radar receivers ? ir imaging ? digital communications general description the spt7734 is a 8-bit monolithic, low cost, ultralow power analog-to-digital converter capable of minimum word rates of 40 msps. the on-chip track-and-hold function assures very good dynamic performance without the need for exter- nal components. the input drive requirements are mini- mized due to the spt7734's low input capacitance of only 5 pf. power dissipation is extremely low at only 175 mw typical at 40 msps with a power supply of +5.0 v. the digital outputs are +3 v or +5 v, and are user selectable. the spt7734 has incorporated proprietary circuit design and cmos process- ing technologies to achieve its advanced performance. in- puts and outputs are ttl/cmos compatible to interface with ttl/cmos logic systems. output data format is straight binary. the spt7734 is available in 28-lead soic and 32-lead small (7 mm square) tqfp packages over the commercial tem- perature range. . . . aaa aaa aaa aaa aaa aaa 9-bit sar da c adc section 1 t/h 9 aaa aaa aaa aaa aaa aaa 9-bit sar da c adc section 16 a uto- zero cmp a uto- zero cmp t/h 9 v ref 1:16 mux . . . 9 9 9 9 9-bit 16:1 mux/ error correction timing and control p1 p2 p15 p16 adc section 2 adc section 15 . . . ref erence ladder ref in enab le clk in data v ali d a in . . . d8 ov err ange d7 (msb) d6 d5 d4 d3 d2 d1 d (lsb) block diagram
2 1/27/98 spt7734 electrical specifications t a =t max to t max , av dd =dv dd =+5.0 v, v in =0 to 4 v, f s =40 msps, v rhs =4.0 v, v rls =0.0 v, unless otherwise specified. test test spt7734 parameters conditions level min typ max units resolution 8 bits dc accuracy integral nonlinearity iv 1.0 lsb differential nonlinearity iv 0.5 lsb no missing codes vi guaranteed analog input input voltage range vi v rls v rhs v input resistance iv 50 k w input capacitance v 5.0 pf input bandwidth (small signal) v 250 mhz offset v 2.0 lsb gain error v 2.0 lsb reference input resistance vi 300 500 600 w bandwidth v 100 150 mhz voltage range v rls iv 0 - 2.0 v v rhs iv 3.0 - av dd v v rhs - v rls v 1.0 4.0 5.0 v d (v rhf - v rhs )v90mv d (v rls - v rlf )v75mv reference settling time v rhs v15 clock cycles v rls v20 clock cycles conversion characteristics maximum conversion rate vi 40 mhz minimum conversion rate iv 2 mhz pipeline delay (latency) iv 12 clock cycles aperture delay time v 4.0 ns aperture jitter time v 30 ps(p-p) dynamic performance effective number of bits f in =3.58 mhz vi 7.3 7.8 bits f in =10.3 mhz vi 7.2 7.7 bits absolute maximum ratings (beyond which damage may occur) 1 25 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. supply voltages av dd ......................................................................... +6 v dv dd ........................................................................ +6 v input voltages analog input .................................. -0.5 v to av dd +0.5 v v ref ............................................................................ 0 to av dd clk input .................................................................. v dd av dd - dv dd ............................................................... 100 mv agnd - dgnd ................................................... 100 mv output digital outputs ....................................................... 10 ma temperature operating temperature ................................. 0 to +70 c junction temperature ......................................... +175 c lead temperature, (soldering 10 seconds) ........ +300 c storage temperature ................................ -65 to +150 c
3 1/27/98 spt7734 electrical specifications t a =t max to t max , av dd =dv dd =+5.0 v, v in =0 to 4 v, f s =40 msps, v rhs =4.0 v, v rls =0.0 v, unless otherwise specified. test test spt7734 parameters conditions level min typ max units dynamic performance signal-to-noise ratio (without harmonics) f in =3.58 mhz vi 46 49 db f in =10.3 mhz vi 45 48 db harmonic distortion 9 distortion bins from f in =3.58 mhz 1024 pt fft vi 53 57 db f in =10.3 mhz vi 53 56 db signal-to-noise and distortion (sinad) f in =3.58 mhz vi 46 49 db f in =10.3 mhz vi 45 48 db spurious free dynamic range f in =1.0 mhz v 63 db differential phase v 0.3 degree differential gain v 0.3 % intermodulation distortion tbd db inputs logic 1 voltage vi 2.0 v logic 0 voltage vi 0.8 v maximum input current low vi -10 +10 m a maximum input current high vi -10 +10 m a input capacitance v +5 pf digital outputs logic 1 voltage i oh = 0.5 ma vi 3.5 v logic 0 voltage i ol = 1.6 ma vi 0.4 v t rise 15 pf load v 10 ns t fall 15 pf load v 10 ns output enable to data output delay 20 pf load, t a = +25 c v 10 ns 50 pf load over temp. v 22 ns power supply requirements voltages ov dd iv 3.0 5.0 v dv dd iv 4.75 5.0 5.25 v av dd iv 4.75 5.0 5.25 v currents ai dd vi 17 22 ma di dd vi 18 23 ma power dissipation vi 175 225 mw test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi
4 1/27/98 spt7734 figure 1a: timing diagram 1 description parameters min typ max units conversion time t c t clk ns clock period t clk 25 ns clock high duty cycle t ch 40 50 60 % clock low duty cycle t cl 40 50 60 % clock to output delay (15 pf load) t od 17 ns clock to dav t s 10 ns table i - timing parameters figure 1b: timing diagram 2 analog in clock in 1 3 5 7 9 11 13 15 17 sampling clock (internal) a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a data output data valid valid invalid 13 245 t od t cl t ch t c t clk data data 1 data 2 data 3 clock in data output data valid t s t ch t cl t s
5 1/27/98 spt7734 typical interface circuit very few external components are required to achieve the stated device performance. figure 1 shows the typical inter- face requirements when using the spt7734 in normal circuit operation. the following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. figure 1 - typical interface circuit the high sample rate is achieved by using multiple sar adc sections in parallel, each of which samples the input signal in sequence. each adc uses 16 clock cycles to complete a conversion. the clock cycles are allocated as follows: table ii - clock cycles clock operation 1 reference zero sampling 2 auto-zero comparison 3 auto-calibrate comparison 4 input sample 5-15 9-bit sar conversion 16 data transfer the 16 phase clock, which is derived from the input clock, synchronizes these events. the timing signals for adjacent adc sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one adc section. after 16 clock periods, the timing cycle repeats. the latency from analog input sample to the corre- sponding digital output is 12 clock cycles. ? since only 16 comparators are used, a huge power savings is realized. ? the auto-zero operation is done using a closed loop system that uses multiple samples of the comparators response to a reference zero. ? the auto-calibrate operation, which calibrates the gain of the msb reference and the lsb reference, is also done with a closed loop system. multiple samples of the gain error are inte grated to produce a calibration voltage for each adc section. ? capacitive displacement currents, which can induce sam- pling error, are minimized since only one comparator samples the input during a clock cycle. ? the total input capacitance is very low since sections of the converter which are not sampling the signal are isolated from the input by transmission gates. voltage reference the spt7734 requires the use of a single external voltage reference for driving the high side of the reference ladder. it must be within the range of 3 v to 5 v. the lower side of the ladder is typically tied to agnd (0.0 v), but can be run up to 2.0 v with a second reference. the analog input voltage range will track the total voltage difference measured be- tween the ladder sense lines, v rhs and v rls . force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. by using the configuration shown in figure 2, offset and gain errors of less than 2 lsb can be obtained. power supplies and grounding voltages on the spt7734 be derived from a single analog supply as shown in figure 1. a separate digital supply should this power supply configuration to prevent a possible latch- up condition on power up. operating description the general architecture for the cmos adc is shown in the block diagram. the design contains 16 identical successive approximation adc sections, all operating in parallel, a 16- phase clock generator, an 9-bit 16:1 digital output multi- plexer, correction logic, and a voltage reference generator which provides common reference levels for each adc section. v rhf v rls v rlf v rhs v in clk v cal da v d8 d0 en av dd a gnd dgnd* dv dd ref in (+4 v) v in clk in enab le/t r i-state (enab le = activ e lo w) interf acing logics +d5 spt7734 dgnd + 10 f +5 v digital +5 v digital rt n +d5 fb3 no tes: 1) fb3 is to be located as closely to the de vice as possib le . 2) there should be no additional connections to the r ight of fb1 and fb2. 3) all capacitors are 0.1 f surf ace-mount unless otherwise specified. 4) fb1, fb2 and fb3 are 10 h inductors or f err ite beads . fb1 fb2 +a5 a gnd + 10 f +5 v analog +5 v analog rt n +a5 *t o reduce the possibility of latch-up , a v oid connecting the dgnd pins of the adc to the digital g round of the system. cadeka suggests that both the digital and the analog supply be used for all interface circuitry. cadeka suggests using
6 1/27/98 spt7734 figure 2 - ladder force/sense circuit agnd v rhf v rhs v rls v rlf v in 1 2 3 5 6 7 + - + - all capacitors are 0.01 f 4 n/c figure 3 - simplified reference ladder drive circuit without force/sense circuit r/2 r r r r r r r/2 r=30 w (typ) all capacitors are 0.01 f v rlf (agnd) 0.0 v v rls (0.075 v) v rhs (+3.91 v) 90 mv 75 mv +4.0 v external reference in cases where wider variations in offset and gain can be tolerated, v ref can be tied directly to v rhf and agnd can be tied directly to v rlf as shown in figure 3. decouple force and sense lines to agnd with a .01 m f capacitor (chip cap preferred) to minimize high-frequency noise injection. if this simplified configuration is used, the following considerations should be taken into account: the reference ladder circuit shown in figure 3 is a simplified representation of the actual reference ladder with force and sense taps shown. due to the actual internal structure of the ladder, the voltage drop from v rhf to v rhs is not equivalent to the voltage drop from v rlf to v rls . typically, the top side voltage drop for v rhf to v rhs will equal: v rhf - v rhs = 2.25 % of (v rhf - v rlf ) (typical), and the bottom side voltage drop for v rls to v rlf will equal: v rls - v rlf = 1.9 % of (v rhf - v rlf ) (typical). figure 3 shows an example of expected voltage drops for a specific case. vref of 4.0 v is applied to v rhf and v rlf is tied to agnd. a 90 mv drop is seen at v rhs (= 3.91 v) and a 75 mv increase is seen at v rls (= 0.075 v). analog input v in is the analog input. the input voltage range is from v rls to v rhs (typically 4.0 v) and will scale proportionally with respect to the voltage reference. (see voltage reference section.) the drive requirements for the analog inputs are very minimal when compared to most other converters due to the spt7734's extremely low input capacitance of only 5 pf and very high input resistance in excess of 50 k w . the analog input should be protected through a series resistor and diode clamping circuit as shown in figure 4. calibration the spt7734 uses an auto calibration scheme to en- sure 8-bit accuracy over time and temperature. gain and offset errors are continually adjusted to 8-bit accuracy during device operation. this process is completely transparent to the user. upon power-up, the spt7734 begins its calibration algo- rithm. in order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 8- bit lsb. since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. this results in a minimum calibration time upon power-up of 250 m sec (for a 40 mhz clock). once calibrated, the spt7734 remains calibrated over time and temperature. since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the spt7734 to remain in calibration. input protection all i/o pads are protected with an on-chip protection circuit shown in figure 5. this circuit provides esd robustness to 3.5 kv and prevents latch-up under severe discharge condi- tions without degrading analog transition times.
7 1/27/98 spt7734 clock input the spt7734 is driven from a single-ended ttl-input clock. because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. digital outputs the digital outputs (d0-d8) are driven by a separate supply (ov dd ) ranging from +3 v to +5 v. this feature makes it possible to drive the spt7734's ttl/cmos-compatible out- puts with the user's logic system supply. the format of the output data (d0-d7) is straight binary. (see table iii.) the outputs are latched on the rising edge of clk. these outputs can be switched into a tri-state mode by bringing en high. table iii - output data information analog input overrange output code d8 d7-d0 +f.s. + 1/2 lsb 1 1111 1111 +f.s. -1/2 lsb o 1111 111? +1/2 f.s. o ???? ???? +1/2 lsb o oooo ooo? 0.0 v o oooo oooo (? indicates the flickering bit between logic 0 and 1). do not connect pins (dnc) there are two pins designated as do not connect (dnc). these pins must be left floating for proper operation of the device. overrange output the overrange output (d8) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 lsb. when this condition occurs, d8 will switch to logic 1. all other data outputs (d0 to d7) will remain at logic 1 as long as d8 remains at logic 1. this feature makes it possible to include the spt7734 into higher resolution systems. figure 4 - recommended input protection circuit 47 w d1 d2 adc buffer av dd +v -v d1 = d2 = hewlett packard hp5712 or equivalent figure 5 - on-chip protection circuit v dd analog pad 120 w 120 w
8 1/27/98 spt7734 package outlines 1 28 a b cd e f g i h h inches millimeters symbol min max min max a 0.696 0.712 17.68 18.08 b 0.004 0.012 0.10 0.30 c .050 typ 0.00 1.27 d 0.014 0.019 0.36 0.48 e 0.009 0.012 0.23 0.30 f 0.080 0.100 2.03 2.54 g 0.016 0.050 0.41 1.27 h 0.394 0.419 10.01 10.64 i 0.291 0.299 7.39 7.59 28-lead soic 32-lead tqfp a b c d e f g h i j k l inches millimeters symbol min max min max a 0.347 0.355 8.90 9.10 b 0.269 0.277 6.90 7.10 c 0.347 0.355 8.90 9.10 d 0.269 0.277 6.90 7.10 e 0.027 0.035 0.68 0.89 f 0.012 0.018 0.30 0.45 g 0.053 0.057 1.35 1.45 h 0.002 0.006 0.05 0.15 i 0.039 typ 1.00 typ j 0.004 0.008 0.09 0.20 k0 7 0 7 l 0.018 0.029 0.45 0.75
9 1/27/98 spt7734 pin assignments pin functions name function agnd analog ground v rhf reference high force v rhs reference high sense v rls reference low sense v rlf reference low force v cal calibration reference v in analog input av dd analog v dd dv dd digital v dd dgnd digital ground clk input clock f clk =fs (ttl) en output enable d0-7 tri-state data output, (d?=lsb) d8 tri-state output overrange dav data valid output ov dd digital output supply ognd digital output ground dnc do not connect part number temperature range package type spt7734scs 0 to +70 c 28l soic SPT7734SCT 0 to +70 c 32l tqfp ordering information a gnd v rhf v rhs n/c v rls v rlf v in a gnd v cal av dd dv dd dgnd clk da v 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ognd d3 dnc d1 d0 dnc d2 ov dd d4 d5 d6 d7 d8 en soic 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 1 1 10 9 25 26 27 28 29 30 31 32 d5 d4 d3 ov dd ognd d2 d1 d0 d6 d7 d8 a gnd a gnd v rhf v rhs v rls dnc dnc da v clk dgnd dgnd dv dd en v rlf v in a gnd a gnd v cal av d d av d d dv dd tqfp
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