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1 ? fn6820.0 isl54221 high-speed usb 2.0 (480mbps) multiplexer the intersil isl54221 is a single supply dual 2:1 multiplexer that can operate from a single 2. 7v to 5.5v supply. it contains two spdt (single pole/double throw) switches configured as a dpdt. the part was designed for switching or routing of usb high-speed signals and/or usb full-speed signals in portable battery powered products. the 6.7 switches can swing rail to rail and were specifically designed to pass usb full-speed data signals that range from 0v to 3.3v and usb high-speed data signals that range from 0v to 400mv. they have high bandwidth and low capacitance to pass usb high-speed data signals with minimal distortion. the part can be used in personal media players and other portable battery powered devices that need to route usb high-speed signals or full-speed signals to different transceiver sections of the device while connected to a single usb host (computer). the digital logic inputs are 1.8v logic compatible when operated with a 2.7v to 3.6v supply. the isl54221 has an output enable pin to open all the switches. it can be used to facilitate proper bus disconnect and connection when switching between the usb sources. the isl54221 is available in a tiny 10 ld 2.1mmx1.6mm tqfn package. it operates over a temperature range of -40 to +85c. features ? high-speed (480mbps) and full-speed (12mbps) signaling capability per usb 2.0 ? 1.8v logic compatible (2.7v to +3.6v supply) ? enable pin to open all switches ? power off protection ? d-/d+ pins overvoltage tolerant to 5.5v ? -3db frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 742mhz ? low on capacitance. . . . . . . . . . . . . . . . . . . . . . . . 7.4pf ? low on-resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 ? single supply operation (v dd ) . . . . . . . . . . . . 2.7v to 5.5v ? available in tqfn package ? pb-free (rohs compliant) ? compliant with usb 2.0 short circuit and overvoltage requirements without additional external components applications ? mp3 and other personal media players ? cellular/mobile phones ?pda?s ? digital cameras and camcorders ? usb switching application block diagram portable media device isl54221 usb transceiver high-speed usb connector d- d+ sel gnd hsd1- hsd1+ hsd2- hsd2+ v dd oe logic circuitry controller usb transceiver full-speed vbus d- d+ gnd or full-speed high_speed or data sheet december 16, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6820.0 december 16, 2008 pinout isl54221 10 ld 2.1 x 1.6 tqfn top view note: 1. switches shown for sel = logic ?1? and oe = logic ?0?. 1 3 4 oe hsd2+ hsd2- hsd1+ vdd 2 10 5 7 8 hsd1- d+ d- gnd 9 6 sel logic control truth table oe sel hsd1-, hsd1+ hsd2-, hsd2+ 0 0 on off 01 off on 1x off off logic ?0? when 0.5v, logic ?1? when 1.4v with a 2.7v to 3.6v supply. pin descriptions pin name description vdd power supply gnd ground connection sel select logic control input oe bus switch enable d+, d-, hsdx+, hsdx- usb data port ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL54221IRUZ-T* gl -40 to +85 10 ld 2.1x1.6mm tqfn (tape and reel) l10.2.1x1.6a *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materi als and nipdau plate - e4 termination finish, wh ich is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020. isl54221
3 fn6820.0 december 16, 2008 absolute maximum rati ngs thermal information vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5v input voltages hsd2x, hsd1x (note 2). . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v sel, oe (note 2) . . . . . . . . . . . . . . . . . . . . -0.3 to ((v dd ) + 0.3v) output voltages d+, d- (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v continuous current (hsd2x, hsd1x) . . . . . . . . . . . . . . . . . . 40ma peak current (hsd2x, hsd1x) (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . 100ma esd rating: human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kv thermal resistance (typical, note 3) ja (c/w) 10 ld tqfn package . . . . . . . . . . . . . . . . . . . . . . 155 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c v dd supply voltage range . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v logic control input voltage . . . . . . . . . . . . . . . . . . . . . . . 0v to v dd analog signal range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to v dd caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. signals on hsd1x, hsd2x, d+,d- exceeding gnd by specified amount are clamped. signals on oe and sel exceeding v dd or gnd by specified amount are clamped. limit current to maximum current ratings. 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications - 2.7v to 5.5v supply test conditions: v dd = +3.3v, gnd = 0v, v selh = 1.4v, v sell = 0.5v, v oe h = 1.4v, v oe l = 0.5v, (note 4), unless otherwise specified parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units analog switch characteristics analog signal range, v analog v dd = v dd , sel = 0v or v dd , oe = 0v full 0 - v dd v on-resistance, r on (high-speed) v dd = 2.7v, sel = 0.5v or 1.4v, oe = 0.5v, i dx = 40ma, v hsd1x or v hsd2 x = 0v to 400mv (see figure 3, note 9) 25 - 6.7 8 full - - 10 r on matching between channels, r on (high-speed) v dd = 2.7v, sel = 0.5v or 1.4v, oe = 0.5v, i dx = 40ma, v v hsd1x or v hsd2 x = voltage at max r on , (notes 8, 9) 25 - 0.117 0.45 full - - 0.55 r on flatness, r flat(on) (high-speed) v dd = 2.7v, sel = 0.5v or 1.4v, oe = 0.5v, i dx = 40ma, v hsd1x or v hsd2 x = 0v to 400mv, (notes 7, 9) 25 - 0.94 1.2 full - - 1.3 off leakage current, i hsd1x(off) v dd = 5.5v, sel = v dd and oe = 0v or oe = v dd , v dx = 0.3v, 3.3v, v hsd1x = 3.3v, 0.3v, v hsd2x = 0.3v, 3.3v 25 -15 0.31 15 na full -20 - 20 na on leakage current, i hsd1x(on) v dd = 5.5v, sel = oe = 0v, v dx = 0.3v, 3.3v, v hsd1x = 0.3v, 3.3v, v hsd2x = 3.3v, 0.3v 25 -20 2.2 20 na full -25 - 25 na off leakage current, i hsd2x(off) v dd = 5.5v, sel = oe = 0v or oe = v dd , v dx = 3.3v, 0.3v, v hsd2x = 0.3v, 3.3v, v hsd1x = 3.3v, 0.3v 25 -15 0.26 15 na full -20 - 20 na on leakage current, i hsd2x(on) v dd = 5.5v, sel = v dd , oe = 0v, v dx = 0.3v, 3.3v, v hsd2x = 0.3v, 3.3v, v hsd1x = 3.3v, 0.3v 25 -20 2.1 20 na full -25 - 25 na power off leakage current, i d+ , i d- v dd = 0v, v d+ = 0v to 5.25v, v d- = 0v to 5.25v, sel = oe = v dd 25 - 0.0047 0.025 a full - - 0.40 a dynamic characteristics turn-on time, t on v dd = 3.3v, r l = 50 , c l = 10pf (see figure 1) 25 - 35 - ns turn-off time, t off v dd = 3.3v, r l = 50 , c l = 10pf (see figure 1) 25 - 27 - ns break-before-make time delay, t d v dd = 3.3v, r l = 50 , c l = 10pf (see figure 2) 25 - 10 - ns isl54221
4 fn6820.0 december 16, 2008 skew, (t skewout - t skewin )v dd = 3.3v, sel = 0v or 3.3v, oe = 0v, r l = 45 , c l = 10pf, t r = t f = 720ps at 480mbps, (duty cycle = 50%) (see figure 6) 25 - 50 - ps rise/fall degradation (propagation delay), t pd v dd = 3.3v, sel = 0v or 3.3v, oe = 0v, r l = 45 , c l = 10pf ( see figure 6) 25 - 250 - ps crosstalk v dd = 3.3v, r l = 50 , f = 240mhz (see figure 5) 25 - -36 - db off-isolation v dd = 3.3v, oe = 3.3v, r l = 50 , f = 240mhz 25 - -32 - db -3db bandwidth signal = 0dbm, 0.2vdc offset, r l = 50 25 - 742 - mhz off capacitance, c hsxoff f = 1mhz, v dd = 3.3v, sel = 0v, oe = 3.3v, v hsd1x or v hsd2x = v dx = 0v (see figure 4) 25 - 2.8 - pf com on capacitance, c dx(on) f = 1mhz, v dd = 3.3v, sel = 0v or 3.3v, oe = 0v, v hsd1x or v hsd2x = v dx = 0v (see figure 4) 25 - 7.4 - pf power supply characteristics power supply range, v dd full 2.7 5.5 v positive supply current, i dd v dd = 5.5v, sel = 0v or v dd , oe = 0v or v dd 25 - 0.009 0.03 a full - - 1 a positive supply current, i dd v dd = 4.3v, sel = 2.6v, oe = 0v or 2.6v 25 - 0.159 0.6 a full - - 1.6 a positive supply current, i dd v dd = 3.6v, sel = 1.4v, oe = 0v or 1.4v 25 - 6.6 10 a full - - 12 a digital input characteristics input voltage low, v sell , v oe l v dd = 2.7v to 3.6v full - - 0.5 v input voltage high, v selh , v oe h v dd = 2.7v to 3.6v full 1.4 - - v input voltage low, v sell , v oe l v dd = 4.3v to 5.5v full - - 0.8 v input voltage high, v selh , v oe h v dd = 4.3v to 5.5v full 2.0 - - v input current, i sell , i oe l v dd = 5.5v, sel = 0v, oe = 0v full - 3.3 - na input current, i selh v dd = 5.5v, sel = 5.5v full - -3.6 - na input current, i oe h v dd = 5.5v, oe = 5.5v full - -8.2 - na notes: 4. v logic = input voltage to perform proper function. 5. the algebraic convention, whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 7. flatness is defined as the difference between maximum and minimum value of on-resis tance over the specified analog signal ran ge 8. r on matching between channels is calculated by s ubtracting the channel with the highest max r on value from the channel with lowest max r on value, between hsd2+ and hsd2- or between hsd1+ and hsd1-. 9. limits established by characteri zation and are not production tested. electrical specifications - 2.7v to 5.5v supply test conditions: v dd = +3.3v, gnd = 0v, v selh = 1.4v, v sell = 0.5v, v oe h = 1.4v, v oe l = 0.5v, (note 4), unless otherwise specified (continued) parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units isl54221
5 fn6820.0 december 16, 2008 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 2b. test circuit figure 2. break-before-make time figure 3. r on test circuit 50% t r < 20ns t f < 20ns t off 90% vdd 0v v input 0v t on logic input switch input switch output 90% v out v out v (input) r l r l r on + ----------------------- - = switch input vin v out r l c l dx hsdxx sel 50 10pf gnd v dd c oe v input 90% vdd 0v t d logic input switch output 0v v out vin sel dx r l c l v out 10pf 50 hsd2x v dd gnd v input c oe hsd1x v dd c ov or vdd hsdx dx sel gnd v hsdx v 1 r on = v 1 /40ma 40ma repeat test for all switches. oe isl54221
6 fn6820.0 december 16, 2008 figure 4. capacitance test circuit figure 5. crosstalk test circuit figure 6a. measurement poin ts figure 6b. test circuit figure 6. skew test test circuits and waveforms (continued) v dd c gnd hsdxx dx sel impedance analyzer 0v or repeat test for all switches. oe vdd analyzer v dd c hsd1x signal generator r l gnd sel dx 50 nc dx hsd2x signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. oe vin din+ din- out+ out- 50% 50% 90% 10% 10% 10% 10% 90% 90% 50% 90% 50% t ri t fi t ro t f0 t skew_i t skew_o out+ c l comd1 d2 gnd v dd c d1 comd2 c l out- din+ din- |tro - tri| delay due to switch for ri sing input and rising output signals. |tfo - tfi| delay due to switch for falling input and falling output signals |tskew_0| change in skew through the switch for output signals. |tskew_i| change in skew through the switch for input signals. 15.8 15.8 143 143 45 45 sel vin oe isl54221
7 fn6820.0 december 16, 2008 application block diagram detailed description the isl54221 device is a dual single pole/double throw (spdt) analog switch configur ed as a dpdt that operates from a single dc power supply in the range of 2.7v to 5.5v. it was designed to function as a dual 2-to-1 multiplexer to select between two usb high-speed differential data signals in portable battery powered products. it is offered in a small tqfn package for use in mp3 players, cameras, pdas, cellphones, and other personal media players. the device has an enable pin to open all switches. the part consists of four 6 high-speed (hsx) switches. these switches have high bandwidth and low capacitance to pass usb high-speed (480mbps) differential data signals with minimal edge and phase distortion. they can also swing from 0v to v dd to pass usb full-speed (12mbps) differential data signals with minimal distortion. the isl54221 was designed for mp3 players, cameras, cellphones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these usb sources to a single usb host (computer). a typical application block diagram of this functionality is shown on page 7. a detailed description of the hs switches is provided in the following section. high-speed (hsx) switches the hsx switches (hsd1-, hsd1+, hsd2-, hsd2+) are bi-directional switches that can pass rail-to-rail signals. when powered with a 3.3v suppl y, these switches have a nominal r on of 6 over the signal range of 0v to 400mv with a r on flatness of 0.94 . the r on matching between the hsd1 and hsd2 switches over this signal range is only 0.12 , ensuring minimal impact by the switches to usb high-speed signal transitions. as the signal level increases, the r on switch resistance increases . at signal level of 3.3v, the switch resistance is nominally 129 . see figures 7, 8, 9 and 10 in the ?typical performance curves? on page 9. the hsx switches were specifically designed to pass usb 2.0 high-speed (480mbps) differential signals in the range of 0v to 400mv. they have low capacitance and high bandwidth to pass the usb high-speed signals with minimum edge and phase distortion to meet usb 2.0 high-speed signal quality specif ications. see figure 11 in the ?typical performance curves? on page 10 for usb high-speed eye pattern taken with switch in the signal path. the hsx switches can also pass usb full-speed signals (12mbps) with minimal distortion and meet all the usb requirements for usb 2.0 full-speed signaling. see figure 12 in the ?typical performance cu rves? on page 11 for the usb full-speed eye pattern taken with switch in the signal path. the maximum normal operating signal range for the hsx switches is from 0v to v dd . the signal voltage should not be allow to exceed the v dd voltage rail or go below ground by more than 0.3v for normal operation. however in the event that the usb 5.25v v bus voltage gets shorted to one or both of the d-/d+ pins, the isl54221 has special fault protection circuitry to prevent damage to the isl54221 part. the fault circuitry allows the signal pins (d-, d+, hs1d-, hs1d+, hs2d-, hs2d+) to be driven up to 5.5v while the v dd supply voltage is in the range of 0v to 5.5v. in this condition the part draws < 500a of current and causes no stress to the ic. in addition when v dd is at 0v (ground) portable media device isl54221 usb transceiver high-speed usb connector d- d+ sel gnd hsd1- hsd1+ hsd2- hsd2+ v dd oe logic circuitry controller usb transceiver full-speed vbus d- d+ gnd or full-speed high_speed or isl54221
8 fn6820.0 december 16, 2008 all switches are off and the fault voltage is isolated from the other side of the switch. when v dd is in the range of 2.7v to 5.5v the fault volt age will pass through to the output of an active sw itch channel. the hs1 channel switches are active (turned on) whenever the sel voltage is logic?0?(low) and the oe voltage is logic?0?(low). the hs2 channel switches are active (turned on) whenever the sel voltage is logic ?1? (high) and the oe voltage is logic ?0? (low). isl54221 operation the following will discuss using the isl54221 the ?application block diagram? on page 7. power the power supply connected at the vdd pin provides the dc bias voltage required by the isl54221 part for proper operation. the isl54221 can be operated with a v dd voltage in the range of 2.7v to 5.5v. when used in a usb application, the v dd voltage should be kept in the range of 3.0v to 5.5v to ensure you get the proper signal levels for good signal quality. a 0.01f or 0.1f decoupling capacitor should be connected from the vdd pin to ground to filter out any power supply noise from entering the part. the capacitor should be located as close to the vdd pin as possible. in a typical application, v dd will be in the range of 2.8v to 4.3v and will be connected to the battery or ldo of the portable media device. logic control the state of the isl54221 device is determined by the voltage at the sel pin and the oe pin. sel is only active when the oe pin is logic ?0? (low). refer to ?truth table? on page 2. the isl54221 logic pins are designed to minimize current consumption when the logic cont rol voltage is lower than the v dd supply voltage. with v dd = 3.6v and logic pins at 1.4v the part typically draws only 6.6a. with v dd = 4.3v and logic pins at 2.6v the part typically draws only 0.2a. driving the logic pins to the v dd supply rail minimizes power consumption. the logic pins must be held high or low and must not float. logic control voltage levels with v dd supply voltage in the range of 2.7v to 3.6v the logic levels are: oe = logic ?0? (low) when v oe 0.5v oe = logic ?1? (high) when v oe 1.4v sel = logic ?0? (low) when v sel 0.5v sel = logic ?1? (high) when v sel 1.4v with v dd supply voltage in the range of 4.3v to 5.5v the logic levels are: oe = logic ?0? (low) when v oe 0.8v oe = logic ?1? (high) when v oe 2.0v sel = logic ?0? (low) when v sel 0.8v sel = logic ?1? (high) when v sel 2.0v hsd1 usb channel if the sel pin = logic ?0? and the oe pin = logic ?0?, high-speed channel 1 will be on. the hsd1- and hsd1+ switches are on and the hs d2- and hsd2+ switches are off (high impedance). when a computer or usb hub is plugged into the common usb connector and channel one is active, a link will be established between the usb 1 driver section of the media player and the computer. the device will be able to transmit and receive data from the computer at a data rate of 480mbps. hsd2 usb channel if the sel pin = logic ?1? and the oe pin = logic ?0?, high-speed channel 2 will be on. the hsd2- and hsd2+ switches are on and the hs d1- and hsd1+ switches are off (high impedance). when a usb cable from a computer or usb hub is connected at the common usb connector and the part has channel 2 active, a link will be established between the usb 2 driver section of the media player and the computer. the device will be able to transmit and receive data from the computer at a data rate of 480mbps. all switches off mode if the sel pin = logic ?0? or logic ?1? and the oe pin = logic ?1?, all of the switches will turn off (high impedance). the all off state can be used to switch between the two usb sections of the media play er. when disconnecting from one usb device to the other usb device, you can momentarily put the isl54221 swit ch in the ?all off? state in order to get the computer to disconnect from the one device so it can properly connect to the other usb device when that channel is turned on. usb 2.0 v bus short requirements the usb specification in sectio n 7.1.1 states a usb device must be able to withstand a v bus short to the d+ or d- signal lines when the device is either powered off or powered on for at least 24 hours. the isl54220 part has special fault protection circuitry to meet these short circuit requirements. the fault protection circuitry allows the signal pins (d-, d+, hs1d-, hs1d+, hs2d-, hs2d+) to be driven up to 5.5v while the v dd supply voltage is in the range of 0v to 5.5v. in this overvoltage condition the part draws < 500a of current and causes no stress/damage to the ic. isl54221
9 fn6820.0 december 16, 2008 in addition when v dd is at 0v (ground) all switches are off and the shorted v bus voltage is isolated from the other side of the switch. when v dd is in the range of 2.7v to 5.5v the shorted v bus voltage will pass through to the output of an active (turned on) switch channel but not through a turned off channel. any components connected on the active channel must be able to withsta nd the overvoltage condition. note: during the fault condition normal operation of the usb channel is not guaranteed until the fault condition is removed. typical performance curves t a = +25c, unless otherwise specified figure 7. on-resistance vs supply voltage vs switch voltage figure 8. on-resistance vs supply voltage vs switch voltage figure 9. on-resistance vs switch voltage figure 10. on-resistance vs switch voltage 4 5 6 7 8 0 0.050.100.150.200.250.300.350.40 r on ( ) v com (v) i com = 40ma v dd = 3.0v v dd = 3.3v v dd = 2.7v v dd = 3.6v v dd = 5.5v 0 50 100 150 200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 v dd = 3.3v v dd = 2.7v r on ( ) v com (v) i com = 1ma 3 4 5 6 7 8 9 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) i com = 40ma +25c +85c -40c v+ = 2.7v 2 3 4 5 6 7 8 00.10.20.30.4 r on ( ) v com (v) +25c +85c -40c i com = 40ma v+ = 3.3v isl54221
10 fn6820.0 december 16, 2008 figure 11. eye pattern: 480mbps with switches in the signal path typical performance curves t a = +25c, unless otherwise specified (continued) time scale (0.2ns/div) voltage scale (0.1v/div) v dd = 3.3v v dd = 3.3v isl54221
11 fn6820.0 december 16, 2008 figure 12. eye pattern: 12mbps with switches in the signal path figure 13. frequency response figure 14. off-isolation typical performance curves t a = +25c, unless otherwise specified (continued) time scale (10ns/div) voltage scale (0.5v/div) v dd = 3.3v -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 1m 10m 100m 1g v in = 0dbm, 0.2vdc bias r l = 50 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 frequency (hz) normalized gain (db) 0.01 0.1 1m 500m 10m 0.001 100m v in = 0dbm, 0.2vdc bias r l = 50 isl54221
12 fn6820.0 december 16, 2008 figure 15. crosstalk die characteristics substrate potential (powered up): gnd transistor count: 325 process: submicron cmos typical performance curves t a = +25c, unless otherwise specified (continued) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 frequency (hz) normalized gain (db) 0.01 0.1 1m 500m 10m 0.001 100m v in = 0dbm, 0.2vdc bias r l = 50 isl54221
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6820.0 december 16, 2008 isl54221 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x 2 0.10 m c a b 0.05 m c (nd-1) x e c 0.05 c a 0.10 c a1 seating plane e index area pin #1 id 3 5 (datum a) (datum b) n-1 1 n nx l nx b 2 1 n top view bottom view side view nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) l detail ?a? pin 1 id l 0.05 min 0.10 min 0.10 c 2x 4xk b l10.2.1x1.6a 10 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.05 2.10 2.15 - e 1.55 1.60 1.65 - e 0.50 bsc - k0.20 --- l 0.35 0.40 0.45 - n102 nd 4 3 ne 1 3 0- 12 4 rev. 3 6/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. same as jedec mo-255uabd except: no lead-pull-back, "a" min dimension = 0.45 not 0.50mm "l" max dimension = 0.45 not 0.42mm. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389. 2.00 0.80 1.75 0.25 0.50 0.275 2.50 land pattern 10

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Price & Availability of ISL54221IRUZ-T

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISL54221IRUZ-T 46P7981	Renesas Electronics Corporation	High Speed Usb 2.0 Multiplexer, 10Ld 2.1X1.6X.5Mm Utqfn/Tape & Reel Rohs Compliant: Yes \|Renesas ISL54221IRUZ-T	3000: USD0.65	0

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