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page 1 july 2005 FS8170 2.5 ghz low powe r phase-locked loop ic princeton technology corp. reserves the ri ght to change the product described in this datasheet. all information con- tained in this datasheet is subject to change without prior notice. pr inceton technology corp. assumes no responsibility for the use of any circuits shown in this datasheet. description the FS8170 ic is a serial data input, fully programmable ph ase-locked loop with a 2.5 ghz prescaler for use in the local oscillator subsystem of radio tr ansceivers. multi-modu- lus division ratios of 32/33 a nd 64/65 are selectable thru serial programming to enable pulse swallowing operation. when combined with an external vco, the FS8170 becomes the core of a very low power frequency synthesizer well-s uited for mobile communication applications, such as 2.4 ghz ism-band wireless data links and cellular gsm and pcs. the FS8170 is also pin compatible with fujitsu?s mb15e07sl ic. features ? maximum input frequency: 2.5 ghz ? supply voltage range from 2.4 v to 3.6 v ? low current consumption in lo cked state: 3.5 ma typ. (v cc = v p = 2.7 v, t a = +25 c) 4.0 ma typ. (v cc = v p = 3.0 v, t a = +25 c) 10 a max. in asynchronous power-down mode ? digitally-filtered lock detect output ? 18-bit programmable input frequency divide r using 32/33/64/65 multi-modulus prescaler with di vide ratio range from 992 to 65631 for 32/33 mode and from 4032 to 131135 for 64/65 mode ? 14-bit programmable reference freque ncy divider with divide ra tio range from 3 to 16383 ? programmable charge pump c urrent: 1.5 ma or 6 ma ? pin compatible with fujitsu mb15e07, mb15e07l, mb15e07sl ? 16 pin, plastic tssop (0.65 mm pitch) package and pin assignment 16 pin, plastic tssop (dimensions in mm) xin xout vp vcc do vss xfin fin r p fold zc en le data clk 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 himark FS8170
FS8170 page 2 july 2005 pin descriptions functional block diagram number name i/o description 1 xin i reference crystal oscillator or external clock input with internally biased amplifier 2 xout o reference crystal oscillator output 3 vp ? power supply voltage for the charge pump 4 vcc ? power supply voltage 5 do o single-ended charge pump output 6 vss ? ground 7 xfin i complementary input for prescaler (normally ac-bypasse d via a capacitor) 8 fin i vco frequency input with internally biased input amplifier 9 clk i shift register clock input 10 data i serial data input 11 le i load enable signal input 12 en i power-down control 13 zc i forced high-impedance control for the charge pump 14 fold o multiplexed cmos level output (see functional de scription section f or programming infor- mation) 15 p o phase comparator n-channel open drain output for an external charge pump 16 r o phase comparator cmos inverter output for an external charge pump pfd ld mux fin data clk le control logic shift register fold do lock detector en n-latch n-counter r-counter charge pump osc n-prescaler xout xin r-latch xfin r p zc
FS8170 page 3 july 2005 absolute maximum ratings v ss = 0 v recommended oper ating conditions v ss = 0 v parameter symbol rating unit supply voltage range v cc v ss ? 0.3 to v ss + 4.0 v v p v cc to 6.0 v input voltage range v fin v ss ? 0.5 to v dd + 0.5 v output voltage range v o v ss to v cc v v do v ss to v p v storage temperature range t stg ?55 to 125 c soldering temperature range t sld 260 c soldering time range t sld 4s esd rating (human body mode) 3500 ev parameter symbol va l u e unit min. typ. max. supply voltage range v cc 2.4 3.0 3.6 v v p vcc ? 5.5 v operating temperature t a ?40 25 80 c
FS8170 page 4 july 2005 electrical characteristics (v cc = v p = 3.0 v, v ss = 0 v, t a = ?40 to 85 c unless otherwise noted) parameter symbol condition va l u e unit min. typ. max. general power supply current consumption i cc,total fin = 2.5 ghz 4 ma standby current consumption i cc,standby zc = ?h? or open 10 a fin operating frequency f fin v fin = 0.3 v pk-pk sinusoid 50 2500 mhz xin operating frequency f xin 3 40 mhz input sensitivity p fin 50 ? measurement system -15 +2 dbm xin input voltage swing v xin 0.5 v cc v pk-pk charge pump rf charge pump output current ido source v do = v p /2, cs bit = ?h? -6 ma ido sink v do = v p /2, cs bit = ?h? 6ma ido source v do = v p /2, cs bit = ?l? -1.5 ma ido sink v do = v p /2, cs bit = ?l? 1.5 ma digital interface (data, clk, le, ps, zc) high-level input voltage v ih 0.8 v cc v low-level input voltage v il 0.2 v cc v high-level input current i ih v ih = v cc = 3.6v ?1 1 a low-level input current i il v il = 0 v, v cc = 3.6v ?1 1 a xin logic high input current i ih,xin v ih = v dd 100 a xin logic low input current i il,xin v il = 0 v ?100 a p logic low output voltage v ol open drain output 0.4 v p logic low output current i ol open drain output 1 ma r logic high output voltage v oh v cc = v p = 3.0 v, i oh = ?1 ma v cc ? 0.4 v r logic low output voltage v ol v cc = v p = 3.0 v, i ol = 1 ma 0.4 v r logic high output current i oh v cc = v p = 3.0 v ?1 ma r logic low output current i ol v cc = v p = 3.0 v 1ma
FS8170 page 5 july 2005 fold logic high output voltage v oh v cc = v p = 3.0 v, i oh = ?1 ma v cc ? 0.4 v fold logic low output voltage v ol v cc = v p = 3.0 v, i ol = 1 ma 0.4 v fold logic high output current v oh v cc = v p = 3.0 v ?1 ma fold logic low output current v ol v cc = v p = 3.0 v 1ma microwire timing data to clk setup time t su1 10 ns data to clk hold time t hold1 10 ns clk to le setup time t su2 20 ns clk to le hold time t hold2 30 ns le pulse width t ew 50 ns electrical characteristics (v cc = v p = 3.0 v, v ss = 0 v, t a = ?40 to 85 c unless otherwise noted) parameter symbol condition va l u e unit min. typ. max.
FS8170 page 6 july 2005 functional description programmable input frequency divider the vco output to the fin pin is divided by the programmable divi der and then inter- nally output to the phase/f requency detector (pfd) as f v . the programmable input fre- quency divider consists of a multi-m odulus (selectable 32/33 or 64/65 (m/m+1)) prescaler and a 18-bit n-counter , which is further comprised of a 7-bit swallow a-counter, and a 11-bit main b -counter. the total divide ratio, n , is related to values for m , a , and b through the relation with the minimum programmable divi sor for continuous c ounting is given by , and is for the 32/33 prescaler mode, and is for the 64/65 mode. hence, the valid total divide ratio range for the input divider is for the 32/33 mode and for the 64/65 mode. programmable reference frequency divider the crystal oscillator output is divided by the programmable reference divider and then internally output to the pfd as f r . the programmable refere nce frequency divider con- sists of a 14-bit reference r-c ounter. becasue of its specif ic design, the minimum accept- able divisor for r is 3, and hence the total divide ratio, r , ranges from 3 to 16383. shift register configuration the divide ratios for the input and reference dividers are i nput using a 19-bit serial inter- face consisting of separate clock (clk), data (data), and load enable (le) lines. the format of the serial data is shown in table 1. the data on the data line is written to the shift register on the rising edge of the clk signa l and is input with msb first, and the last bit is used as the latch select control bit. the data on the data line should be changed on the falling edge of clk, and le should be held low while data is being written to the shift register. data is transferred from the shift register to one of the frequency divider latches when le is set high. when the latch se lect control bit is set low, data is loaded to the 18-bit n -counter latch, and when the latch se lect control bit is set high, the 4 msbs are recognized as cs, lds, fc, sw, resp ectively, and the next 14 data bits are loaded to the 14-bit r -counter latch. the definition of the 4 msbs will be described in table 5 and 6. note that lds s hould be set low for normal operation. also, serial input data timing waveforms are shown in fig. 1. nm 1 + () am ba ? () + mba , + == ba . mm 1 ? () 32 32 1 ? () 992 = 64 64 1 ? () 4032 = n 992 to 65631 = n 4032 to 13113 5 =
FS8170 page 7 july 2005 fig. 1 ? serial data input waveforms t su1 t su2 t hold1 data clk le data clk le msb 1817161514131211109876543 19 21 control parameter min. typ. max. unit t su1 10 ? ? ns t su2 20 ? ? ns t hold1 10 ? ? ns bit cb control bit for selecting the 0:n or 1: r latch a1 to a7 control bits for setting the divide ratio of the programmable swallow counter (0 to 127) n1 to n11 control bits for setting the divide ratio of the programm able main counter (3 to 2047) r1 to r14 control bits for setting th e divide ratio of the programmab le reference counter (3 to 16383) sw control bit for setting the divide ra tio of the prescaler (32/33 or 64/65) fc control bit for setting the polarit y of the phase/fre quency detector lds control bit for selecting the output for the fold pin cs control bit for setting th e charge pump current level table 1: serial data input format 12345678910111213141516171819 c b a 1 a 2 a 3 a 4 a 5 a 6 a 7 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 s w f c l d s c s msb lsb
FS8170 page 8 july 2005 table 2: binary 7-bit data format for swallow counter divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 . ....... 127 1111111 table 3: binary 11-bit data format for main counter divide ratio (b) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 3 00000000011 4 00000000100 . ........... 2047 1 1111111111 table 4: binary 14-bit data format for reference counter divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 3 00000000000011 4 00000000000100 . .............. 16383 11111111111111 table 5: data format for 3 optional bits bit h l description sw 32/33 64/65 prescaler dual-modulus ratio setting cs + 6 ma + 1.5 ma charge pump current setting lds fo signal ld signal fold output select setting
FS8170 page 9 july 2005 phase/frequency detector (pfd) the pfd compares an internal i nput frequency divider output signal, f v , with an internal reference frequency di vider output signal, f r , and generates an error signal, do, which is proportional to the phase error between f v and f r . the do output is intended for use with a passive filter as shown in fig. 2 (a). the pol arity of do is selectab le by setting the bit fc to high or low. the setting should depend on the frequency-vol tage characteristic of exter- nal vco as depicted in fig. 2 (b). the input/output waveforms for the pfd are shown in fig. 3. fig. 2 ? low-pass filter and external vco frequency-voltage characteristic table 6: data format for fc bit (lds = high) fc = high fc = low do r pfolddo r pfold f r > f v hll fold = f r lh z a fold = f v f r < f v lhz hll f r = f v z l zz l z a. z denotes high impedance state do vco (a) passive low-pass filter (1) (2) f vco v do (b) vco frequency-voltage characteristic note: if vco has a positive tuning curve similiar to trace (1), set fc = ?h,? otherwise if the vco has a negative tuning curve similar to trace (2), set fc = ?l.?
FS8170 page 10 july 2005 fig. 3 ? phase comparator output waveforms charge pump (cp) the phase error signal, do, generated from the pfd will pump charge into an external loop filter, which then converts the charge to produce the vco?s tuning voltage. with a constant pumping rate, the shif t of the vco?s tuning voltage will be directly proportional to the phase error signal do. two pumping rates, 1.5 ma and 6 ma, are provided by the chip and are selectable through the bit cs as defined previously in table 5. also, the charge pump characteristics corresponding to both modes are shown in the typical char- acteristics section. the inte rnal charge pump may be turned off by the pin zc. when zc is set low, the internal charge pump will stay in its high-impedance state and will not pump any charge into the external lpf. in this case, the user is allowe d to utilize one?s own charge pump by two control pins p and r which are defined in table 6. p and r are the error signals directly prop ortional to the positive/negative phase error when fc = ?h.? when fc = ?l,? the relati on becomes negative/positive. table 7: setting for the pin zc zc do output h normal output l high impedance f r f v do ld [fc=?h?] do [fc=?l?] 1. pulses of finite width on do output are genera ted during locked state to prevent dead zone. 2. a ?locked? condition (ld is high) is indicated when the phase error is less than t1 or t2 at least for 3 consecutive comparison cycles, otherwise an ?u nlocked? condition (ld is low) is indicated. 3. the values of t 1 and t 2 depend on the xin input frequency: t 1 > 2/fosc (e.g. t 1 > 250 ns, if f xin = 8 mhz) t 2 > 2/fosc (e.g. t 2 > 250 ns, if f xin = 8 mhz) 4. ld becomes high during power-dow n mode (when en is set low).
FS8170 page 11 july 2005 multi-function lock detect output (fold) a digital lock detect function is included with the phase dete ctor through an internal digi- tal filter to produce a logic level output whic h is available on the fold output pin. the criterion of lock indication de pends on the period of the crysta l oscillator reference. the lock dectect output is high whenever the phase error between pha se detector inputs is less than 2 times of the crystal period for mo re than three consecutive comparison cycles, otherwise is low. note that ld become s high during the power saving mode. the ld output is depicted in fig. 3 as well. power-down control (en) by setting the pin en to low, the chip enters into power-down mode, reducing the cur- rent consumption. during the power-down m ode, the phase detector output, do, is set to its high impedance. normal operation mode resumes when en is switched to high. to prove a smooth start-up condition, an intermittent control circ uit is activated when the device returns to normal operation. due to the unknown relationship between f v and f r after returning from power-dow n, the pfd output is unpredicta ble and may give rise to a significant jump in the vco?s frequency which will result in an increased lock-up time. to prevent this, the FS8170 employs an intermit tent control circuit to limit the magnitude of the error signal generated by the phase detector when it returns to normal operation, thus ensuring a much quicker return to the fully phase-locked condition. table 8: setting for the pin en en status h normal operation mode l power-down mode
FS8170 page 12 july 2005 measurement circuit setup the circuit shown in fig. 4 is used for measuring th e input sensitivity of the fin input of the pll. fig. 4 ? fin input sensitivity test circuit 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 xin xout vp vcc do vss xfin fin p fold zc en le data clk r s.g. s.g. 1000pf 1000pf 50 ? 50 ? 1000pf 0.1 f from controller vcc to counter
FS8170 page 13 july 2005 typical characteristics fin input sensitivity fig. 5 ? input sensitivity vs. frequency 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 spec fin input sensitivity (prescaler: 64/65) sensitivity (dbm) fin (ghz) vcc=2.4v vcc=3.0v vcc=3.6v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 vcc=2.4v vcc=3.0v vcc=3.6v spec fin input sensitivity (prescaler: 32/33) sensitivity (dbm) fin (ghz)
FS8170 page 14 july 2005 xin input sensitivity fig. 6 ? xin input sensitivity vs. frequency 0 50 100 150 200 250 -35 -30 -25 -20 -15 -10 -5 0 5 10 spec xin input sensitivity sensitivity (dbm) xin (mhz) vcc=2.4v vcc=3.0v vcc=3.6v
FS8170 page 15 july 2005 charge pump characteristic fig. 7 ? charge pump current vs. v do 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -8 -6 -4 -2 0 2 4 6 8 sink state : f r >f v , fc negative source state : f r >f v , fc positive high current mode (ido=6ma) ido (ma) vdo (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 sink state : f r >f v , fc negative source state : f r >f v , fc positive low current mode (ido=1.5ma) ido (ma) vdo (v)
FS8170 page 16 july 2005 supply voltage dependence of charge pump current fig. 8 ? charge pump current vs. supply voltage at v do = v p /2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 sink current source current low current mode (1.5ma mode) v do = 1/2 v p i do (ma) v p (v) 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 high current mode (6.0ma mode) v do = 1/2 v p i do (ma) v p (v) sink current source current
FS8170 page 17 july 2005 appication circuit xtal xout vp vcc do vss xfin fin r p fold zc en le data clk m c u himark FS8170 1000pf 12k 33pf 33pf 1 f vcc vco lock detect vp vp 12k 10k 10k xin 1000pf 0.1 f

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