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10-bit 85msps 3-channel d/a converter description the CXD2309AQ is a 10-bit high-speed d/a converter for video band, featuring rgb 3-channel input/ output. this is ideal for use in high-definition tvs and high-resolution displays. features resolution 10-bit maximum conversion speed 85msps rgb 3-channel input/output differential linearity error 0.5lsb low power consumption 275mw (200 ? load for 2vp-p output) single +5v power supply low glitch 48-pin qfp package structure silicon gate cmos ic absolute maximum ratings (ta = 25?) supply voltage av dd , dv dd 7v input voltage (all pins) v in v dd + 0.5 to v ss ?0.5 v output current i out 0 to 15 ma storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v reference input voltage v ref 0.5 to 2.0 v clock pulse width t pw 1, t pw 0 5.2 (min.) ns operating temperature topr ?0 to +85 ? ?1 e00739a0z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2309AQ 48 pin qfp (plastic)
?2 CXD2309AQ 1 2 3 4 5 6 7 8 9 10 (lsb) r0 r1 r2 r3 r4 r5 r6 r7 r8 (msb) r9 rck 31 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 av ss ro decoder latches 4lsb's current cells 6lsb's current cells clock generator decoder (lsb) g0 g1 g2 g3 g4 g5 g6 g7 g8 (msb) g9 gck av ss go decoder latches 4lsb's current cells 6lsb's current cells clock generator decoder (lsb) b0 b1 b2 b3 b4 b5 b6 b7 b8 (msb) b9 bck dv dd vb dv ss av ss av dd av dd av dd vg vref iref bo decoder latches 4lsb's current cells 6lsb's current cells clock generator bias voltage generator decoder 11 12 13 14 15 16 17 18 19 20 32 21 22 23 24 25 26 27 28 29 30 33 current cells (for full scale) block diagram
3 CXD2309AQ pin configuration 25 26 27 28 29 30 31 32 33 34 35 35 36 36 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 47 48 48 1 1 2 3 4 5 6 7 8 9 10 11 12 (lsb) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 (msb) g0 (lsb) g1 iref vb dv ss bck gck rck b9 (msb) b8 b7 b6 b5 b4 g2 g3 g4 g5 g6 g7 g8 g9 (msb) b0 (lsb) b1 b2 b3 dv dd av ss bo av ss go av ss ro av dd av dd av dd vg vref to digital system analog system , to pin description and equivalent circuit pin no. symbol i/o equivalent circuit description 1 to 10 r0 to r9 11 to 20 g0 to g9 i o 21 to 30 b0 to b9 31 rclk 32 gclk 33 bclk 35 vb digital input. pin 1 r0 (lsb) to pin 10 r9 (msb) pin 11 g0 (lsb) to pin 20 g9 (msb) pin 21 b0 (lsb) to pin 30 b9 (msb) clock input. 34 dv ss digital ground. connect an approximately 0.1f capacitor. 1 33 to dv dd dv ss dv dd dv ss dv dd 35
4 CXD2309AQ pin no. symbol i/o equivalent circuit description 36 iref 37 vref 38 vg reference current output. connect an "r ir " resistor which are 16 times the output resistance "r out ". reference voltage input. sets an output full-scale value. connect an approximately 0.1f capacitor. 39 to 41 av dd analog power supply. av dd av ss av dd av dd av ss 36 av dd av ss 38 37 42 ro 44 go 46 bo current output. output can be obtained by connecting a resistor (200 ? typ.). 43, 45, 47 av ss analog ground. 48 dv dd o i o o digital power supply. av dd av ss av ss 42 44 46
5 CXD2309AQ full-scale voltage of channel ? 1 full-scale ratio = average of the full-scale voltage of the channels 1 100 [%] v a av dd , dv dd av ss , dv ss CXD2309AQ +5.25v electrical characteristics measurement circuit analog input resistance digital input current measurement circuit electrical characteristics (f clk = 85mhz, av dd = dv dd = 5v, r out = 200 ? , v ref = 2.0v, r ir = 3.3k ? , ta = 25 c) item symbol measurement conditions min. typ. max. unit resolution conversion speed integral non-linearity error differential non-linearity error precision guaranteed output voltage range output full-scale voltage output full-scale ratio ? 1 output full-scale current output offset voltage glitch energy crosstalk s/n ratio supply current analog input resistance input capacitance output capacitance digital input voltage digital input current setup time hold time propagation delay time rise time fall time n f clk e l e d v oc v fs f sr i fs v os ge ct snr i dd r in c i c o v ih v il i ih i il ts th t pd tr tf av dd = dv dd = 4.75 to 5.25v ta = 20 to +85 c endpoint when "0000000000" data input r out = 100 ? , 1vp-p output when 10mhz sin wave input when 1mhz sin wave input when 10mhz sin wave output vref av dd = dv dd = 4.75 to 5.25v ta = 20 to +75 c av dd = dv dd = 4.75 to 5.25v ta = 20 to +75 c 0 2.0 0.5 1.8 1.8 0 9.0 40 50 1 2.15 5 4 1 10 1.92 1.92 9.6 36 49 49 63 61 48 55 15 6 7 12 85 2.0 0.5 2.0 2.0 3 10 1 58 9 0.85 5 bit msps lsb lsb v v % ma mv pv s db db ma m ? pf pf v a ns ns ns ns ns f clk = 50mhz f clk = 85mhz f clk = 50mhz f clk = 85mhz f clk = 50mhz f clk = 85mhz
6 CXD2309AQ 31 32 33 35 36 37 38 42 43 44 45 46 47 0.1 r0 to r9 1 to 10 g0 to g9 11 to 20 b0 to b9 21 to 30 vb rck ro av ss go av ss bo av ss vg vref iref gck bck 10bit counter with latch clk 50mhz square wave dv ss 200 av ss 200 oscilloscope av ss 200 av ss 3.3k av ss av dd 0.1 2v conversion rate measurement circuit 31 32 33 35 36 37 38 42 43 44 45 46 47 0.1 dv dd r0 to r9 1 to 10 g0 to g9 11 to 20 b0 to b9 21 to 30 vb rck ro av ss go av ss bo av ss vg vref iref gck bck digital waveform generator clk 50mhz square wave dv ss 200 av ss 200 spectrum analyzer av ss 200 av ss 3.3k av ss av dd 0.1 2v crosstalk measurement circuit 31 32 33 35 36 37 38 42 43 44 45 46 47 0.1 r0 to r9 1 to 10 g0 to g9 11 to 20 b0 to b9 21 to 30 vb rck ro av ss go av ss bo av ss vg vref iref gck bck 10bit counter with latch delay controller delay controller clk 50mhz square wave dv ss 200 av ss 200 oscilloscope av ss 200 av ss 3.3k av ss av dd 0.1 2v setup time hold time glitch energy measurement circuit
7 CXD2309AQ 31 32 33 35 36 37 38 42 43 44 45 46 47 0.1 r0 to r9 1 to 10 g0 to g9 11 to 20 b0 to b9 21 to 30 vb rck ro av ss go av ss bo av ss vg vref iref gck bck controller clk 50mhz square wave dv ss 200 av ss 200 dvm av ss 200 av ss 3.3k av ss av dd 0.1 2v dc characteristics measurement circuit 31 32 33 35 36 37 38 42 43 44 45 46 47 0.1 all "1" all "1" r0 to r9 1 to 10 g0 to g9 11 to 20 b0 to b9 21 to 30 vb rck ro av ss go av ss bo av ss vg vref iref gck bck digital waveform generator clk 50mhz square wave dv ss 200 av ss 200 spectrum analyzer av ss 200 av ss 3.3k av ss av dd 0.1 2v snr measurement circuit 31 32 33 35 36 37 38 42 43 44 45 46 47 0.1 r0 to r9 1 to 10 g0 to g9 11 to 20 b0 to b9 21 to 30 vb rck ro av ss go av ss bo av ss vg vref iref gck bck 10bit counter with latch delay controller delay controller clk 50mhz square wave dv ss 200 av ss 200 oscilloscope av ss 200 av ss 3.3k av ss av dd 0.1 2v propagation delay time measurement circuit
8 CXD2309AQ description of operation timing chart tr t pd t pw1 t s th t pw0 tf t s th t s th 1.5v clk data d/a out 1.5v 100% 90% 50% 10% 0% i/o correspondence table (output full-scale voltage: 2.00v) msb lsb 1 1 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 input code output voltage 2.0v 1.0v 0v
9 CXD2309AQ notes on operation selecting the output resistance CXD2309AQ is a current output type d/a converter. the output voltage can be obtained by connecting the reslstor r out to the current output pins ro, go and bo. specifications: output full-scale voltage v fs = 18 to 2.0 [v] output full-scale current i fs = 9.0 to 10.0 [ma] calculate the output resistance from v fs = i fs r out . connect a resistance sixteen times the output resistance to the reference current output pin iref. in some cases, as this value may not exist, a similar value can be used instead. note that the v fs will be the following. v fs = v ref 16r out /r ir v ref is the voltage set at the reference voltage input pin vref, r out is the resistor to be connected to the current output pins ro, go, bo and r ir is the resistor to be connected to the iref. power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data setting time. set the best values according to the purpose of use. power supply, ground separate the power supply and ground of the analog and digital signals around the device to reduce noise effects. bypass the power supply pin to each ground with a 0.1f ceramics capacitor as near as possible to the pin for both the digital and analog signals. latch up analog and digital power supplies must be able to share the same power supply of the board. this is to prevent latch up caused by potential difference between the two pins when the power is turned on. see "latch up prevention" on page 11. iref the iref pin is very sensitive to improve the ac characteristics. pay attention for capacitance component not to attach to this pin because its output may become unstable. output full-scale voltage for the applications using the rgb signal, the color balance may be broken up when the ro, go and bo output full-scale voltages are used with not adjustment.
10 CXD2309AQ application circuit 25 26 27 28 29 30 31 32 33 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 c c msb lsb lsb msb msb lsb rch input gch input bch input clock input r2 r3 r4 r1 c av dd av ss dv dd dv ss c c r1 r1 when the power supply (av dd and dv dd ) is 5.0v. r1 = 200 ? r2 = 3.3k ? r3 = 3.0k ? r4 = 2.0k ? c = 1f application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
11 CXD2309AQ latch up prevention the CXD2309AQ is a cmos ic which requires latch up precausions. latch up is mainly generated by the lag in the voltage rising time of av dd (pin 39, 40 and 41) and dv dd (pin 48), when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources b. when analog and digital supplies are from a common source (i) (ii) 34 39 40 41 43 45 47 48 dv dd av dd av ss dv ss CXD2309AQ dv dd digital ic +5v +5v av ss av dd c c 34 39 40 41 43 45 47 48 dv dd av dd av ss dv ss CXD2309AQ dv dd digital ic +5v av ss c c 34 39 40 41 43 45 47 48 dv dd av dd av ss dv ss CXD2309AQ dv dd digital ic +5v av ss c c
12 CXD2309AQ 2. example when latch up easily occurs a. when analog and digital supplies are from different sources b. when analog and digital supplies are from common source (i) (ii) 34 39 40 41 43 45 47 48 dv dd av dd av ss dv ss CXD2309AQ dv dd c digital ic +5v +5v av ss av dd c 34 39 40 41 43 45 47 48 dv dd av dd av ss dv ss CXD2309AQ dv dd digital ic +5v av ss av dd c c 34 39 40 41 43 45 47 48 dv dd av dd av ss dv ss CXD2309AQ dv dd digital ic +5v av ss av dd c
13 CXD2309AQ example of representative characteristics 2.0 1.0 0 1.0 v ref reference voltage [v] fig. 1. reference voltage vs. output full-scale voltage v fs output full-scale voltage [v] 2.0 100 50 0 100 r out output resistance [ ? ] fig. 2. output resistance vs. glitch energy ge glitch energy [pv s] 200 1.95 1.90 0 25 0 25 50 ta ambient temperature [ c] fig. 3. ambient temperature vs. output full-scale voltage v fs output full-scale voltage [v] 75 70 1 fo output frequency [mhz] fig. 4. output frequency vs. supply current i dd supply current [ma] 60 40 2 5 10 20 30 40 42 50 sin wave output ? v = 0.02mv/ c standard measurement conditions av dd = dv dd = 5.0v v ref = 2.0v f clk = 85mhz r out = 200 ? r ir = 3.3k ? ta = 25 c
14 CXD2309AQ 60 i dd supply current [ma] f clk clock frequency [mhz] fig. 5. clock frequency vs. supply current 50 i dd f out = 1mhz sin wave i a [analog] i d [digital] 40 30 20 10 20 50 85 60 i dd supply current [ma] f clk clock frequency [mhz] fig. 6. clock frequency vs. supply current 50 i dd f out = 10mhz sin wave i a [analog] i d [digital] 40 30 20 10 20 50 85 70 ct cross talk [db] fo output frequency [mhz] fig. 7. output frequency vs. cross talk sin wave output 40 20 10 1 0 2 5 10 20 42 0 output level [dbm] fo output frequency [mhz] fig. 8. output frequency vs. output level (including primary hold characteristics sinx/x) 10 20 1 2 5 10 20 50 70 snr [db] fo output frequency [mhz] fig. 9. output frequency vs. snr 40 10 0.1 0 1 10 42 40 standard measurement conditions av dd = dv dd = 5.0v v ref = 2.0v f clk = 85mhz r out = 200 ? r ir = 3.3k ? ta = 25 c
15 CXD2309AQ sony corporation package outline unit: mm sony code eiaj code jedec code m package structure package material lead treatment lead material package mass epoxy resin palladium plating copper alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.24 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 ?0.05 + 0.1 qfp-48p-l04 qfp048-p-1212 0.7g 0.15

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