NJU3711A - 1 - ver.2003-11-18 8-bit serial to parallel converter general description the NJU3711A is an 8-bit serial to parallel converter especially applying to mpu outport expander. it can operate from 2.4v to 5.5v. the effective outport assignment of mpu is available as the connection between NJU3711A and mpu using only 4 lines. the serial data synchronizing with 5mhz or more clock can be input to the serial data input terminal and the data are output from parallel output buffer through serial in parallel out shift register and parallel data latches. the hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer (25ma) can drive led directly. features 8-bit serial in parallel out hysteresis input 0.5v typ at 5v operating voltage 2.4 to 5.5v maximum operating frequency 5mhz and more output current 25ma at 5v, 5ma at 3v c-mos technology package outline ssop14 block diagram package outline pin configuration p3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v dd p2 p1 clr stb clk data p4 p5 v ss p6 p7 p8 p1 shift register controller circuit latch circuit p2 p3 p7 p8 dat a cl k stb clr NJU3711Av NJU3711Av
NJU3711A - 2 - ver.2003-11-18 terminal description no. symbol i/o function 1 p3 o 2 p4 o 3 p5 o parallel conversion data output terminals 4 v ss - gnd 5 p6 o 6 p7 o 7 p8 o parallel conversion data output terminals 8 data i serial data input terminal 9 clk i clock signal input terminal 10 stb i strobe signal input terminal 11 clr i clear signal input terminal 12 p1 o 13 p2 o parallel conversion data output terminals 14 v dd - power supply terminal (2.4 to 5.5v)
nju3555 nju3555 NJU3711A - 3 - ver.2003-11-18 functional description (1) reset when the "l" level is input to the clr terminal, all latches are reset and all of parallel conversion output are "l" level. normally, the clr terminal should be "h" level. (2) data transmission in the stb terminal is "h" level and the clock signals are inputted to the clk terminal, the serial data into the data terminal are shifted in the shift register synchronizing at a rising edge of the clock signal. when the stb terminal is changed to "l" level, the data in the shift register are transferred to the latches. even if the stb terminal is "l" level, the input clock signal shifts the data in the shift register, therefore, the clock signal should be controlled for data order. furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure to protect the noise. clk stb clr operation x x l all of latches are reset (the data in the shift register is no change). all of parallel conversion outputs are "l". h h the serial data into the data terminal are inputted to the shift register. in this stage, the data in the latch is not changed. l h the data in the shift register is transferred to the latch. and the data in the latch is output from the parallel conversion output terminals. l h when the clock signal is inputted into the clk terminal in state of the stb="l" and clr="h", the data is shifted in the shift register and latched data is also changed in accordance with the shift register. note 1) x: don?t care
NJU3711A - 4 - ver.2003-11-18 timing chart cl k clr stb data p1 p2 p3 p4 p5 p6 p7 p8
nju3555 nju3555 NJU3711A - 5 - ver.2003-11-18 absolute maximum ratings (ta=25 c) parameter symbol ratings unit supply voltage range v dd -0.5 ~ +7.0 v input voltage range v i v ss -0.5 ~ v dd +0.5 v output voltage range v o v ss -0.5 ~ v dd +0.5 v output current i o 25 ma v o =7v, v i =0v 20 (max) output short current (p1~p8 terminals) (note 5) i osd v o =0v, v i =7v -20 (max) ma power dissipation p d 300 (ssop) mw operating temperature range topr -25 ~ +85 c storage temperature range tstg -65 ~+150 c note 2) all voltage are relative to v ss =0v reference. note 3) do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the ic. it is also recommended that the ic be used in the range specified in the dc electrical characteristics, or the electrical stress may cause malfunctions and impact on the reliability. note 4) to stabilize the ic operation, place decoupling capacitor between v dd and v ss . note 5) v dd =7v, v ss =0v, less than 1 second per pin. dc electrical characteristics (v dd =2.4~5.5v, v ss =0v, ta=25 c, unless otherwise noted) parameter symbol condition min typ max unit operating voltage v dd 2.4 - 5.5 v operating current i dds v ih =v dd , v il =v ss - - 0.1 ma high-level input voltage v ih 0.7v dd - v dd v low-level input voltage v il v ss - 0.3v dd v input leakage current i li v i =0 ~ v dd -10 - 10 a i oh =-25ma v dd -1.5 - v dd i oh =-15ma v dd -1.0 - v dd v dd =5v i oh =-10ma v dd -0.5 - v dd high-level output voltage (note 6) v ohd v dd =3v i oh =-5ma p1~p8 terminals v dd -0.5 - v dd v i ol =+25ma v ss - 1.5 i ol =+15ma v ss - 0.8 v dd =5v i ol =+10ma v ss - 0.4 low-level output voltage (note 6) v old v dd =3v i ol =+5ma p1~p8 terminals v ss - 0.5 v note 6) specified value represent output current per pin. when use, total current consideration and less than power dissipation in rati ng operation should be required.
NJU3711A - 6 - ver.2003-11-18 switching characteristics (v dd =2.4~5.5v, v ss =0v, ta=25 c, unless otherwise noted) parameter symbol condition min typ max unit set-up time t sd data-clk 20 - - ns hold time t hd clk-data 20 - - ns set-up time t sstb stb-clk 30 - - ns hold time t hstb clk-stb 30 - - ns t pd pck clk-p1~p8 - - 100 ns t pd pstb stb-p1~p8 - - 80 ns output delay time t pd pclr clr-p1~p8 - - 80 ns maximum operating frequency f max 5 - - mhz note 7) c out =50pf
nju3555 nju3555 NJU3711A - 7 - ver.2003-11-18 switching characteristics test waveform f max cl k t sstb t sd t hd t hstb dat a stb cl k p1~p8 stb t pd pck l h p1~p8 t pd pstb cl k stb h p1~p8 t pd pclr clr dat a
NJU3711A - 8 - ver.2003-11-18 application circuit [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. mpu NJU3711A data clk stb clr p1 p2 p3 p4 p5 p6 p7 p8
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