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tca62746afg/afng 2007-11-27 1 toshiba cmos integrated circuit silicon monolithic tca62746afg, tca62746afng 16-output constant curr ent led driver with out put open/short detection the tca62746 series are led driv ers with sink type constant circuit output, making them id eal for controlling led modules and displays. the current value of the 16-outp ut is configurable using one external resistor. in addition, these drivers are equipped with a function for detecting the output voltage when the output load leds open or short, and which then outputs the result as serial data. these drivers consist of a 16-con stant current output block, a 16-bit shift register, a 16-bit latch and a 16-bit and-gate. the tca62746 series compli es with rohs regulation. features ? 16-output built-in ? output open detection (ood) function : when in detection mode, outputs the detection results via sout. ? output short detection (osd) function : when in detection mode, outputs the detection results via sout. ? output current setting range : 2 to 50 ma 16-constant current output ? current accuracy (@ r ext = 1.56 k , v o = 1.0 v, v dd = 5.0 v) : between outputs: 1% (typ.) between devices: 3% (max) @i o =15ma ? control data format: serial-in, parallel-out ? i/o logic: ttl level (schmitt trigger input) ? data transfer frequency: f max = 25 mhz (max) ? power supply voltage: v dd = 4.5 to 5.5 v ? operation temperature range: t opr = ? 40 to 85c ? constant current output voltage: v o = 17v (max) ? output delay circuit built-in: internal data reset circuit for power-on resetting (por) ? backward compatible to tb62706b and tb62726a series drivers ? package: fg type: ssop24-p-300-1.00b fng type: ssop24-p-300-0.65a caution this device is sensitive to electr ostatic discharge. please handle with care. the terminals which are marg inal to electro static discharge are shown in the following table. (please refer to page 22 for details.) esd test mm model marginal terminals (mm model internal standard 200v) 5,6,7,8,9,10, 11,12,13,14, 15,16,19,20 * esd test hbm model internal standard (2000v) is ok tca62746afg tca62746afng weight ssop24-p-300-1.00b : 0.32 g (typ.) ssop24-p-300-0.65a : 0.14 g (typ.) for part availability and ordering info rmation please call to ll free: 800.984.5337 website: www.marktechopto.com | email: info@marktechopto.com optoelectronics marktech
tca62746afg/afng 2007-11-27 2 pin assignment (top view) as shown below, this series has the same pin assignments as the tb62706b and tb62726a series: note1: short circuiting an output pin to a power supply pin (v dd or v led* ), or short-circuiting the r ext pin to the gnd pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. please keep this in mind when determining the wiring layout for the power supply and gnd pins. *v led : led power supply gnd sin sck slat out0 out1 out2 out3 out4 out5 out6 out7 v dd r ext sout oe out15 out14 out13 out12 out11 out10 out8 out9
tca62746afg/afng 2007-11-27 3 block diagram out0 out1 3.0 v 0.3 v osd ood constant current outputs out0 out1 out15 ood out15 osd delay1 delay15 16-bit d-latch g q0 q1 q15 d0 d1 d15 r 16-bit shift register q15 q0 q1 q15 st d0 to d15 r d0 ood/osd controller oe st-out slat oe sin sck 16-bit mux s osd ood do 16 16 16 b.g por v dd gnd r ext sout osd ood
tca62746afg/afng 2007-11-27 4 truth table sck slat oe sin out0 out7 out15 *1 sout h l dn dn dn 7 dn 15 dn 15 l l dn 1 no change dn 14 h l dn 2 dn 2 dn 5 dn 13 dn 13 - *2 l dn 3 dn 2 dn 5 dn 13 dn 13 - *2 h dn 3 off dn 13 note1: when out0 to out15 output pins are set to "h" the respective output will be on and when set to "l" the respective output will be off. note2: ?-?is irrelevant to the truth table. timing chart note 1: the latch circuit is a leveled-latch circuit. please exercise precaution as it is not triggered-latch circuit. note 2: keep the slat pin is set to ?l? to enable the latch circuit to hold data. in addition, when the slat pin is set to ?h? the latch circuit does not hold data. the data will instead pass onto output. when the oe pin is set to ?l? the out0 to out15 output pins will go on and off in response to the data. in addition, when the oe pin is set to ?h? all the output pins will be forced off regardless of the data. sin slat sck out0 out1 sout oe out15 h l n 0 1 2 3 4 5 6 8 h l h l h l on off on off on off on off h l 7911 10 12 13 1514 2out
tca62746afg/afng 2007-11-27 5 pin functions pin no pin name i/o function 1 gnd ? the ground pin. 2 sin i the serial data input pin. 3 sck i the serial data transfer clock input pin. also used for ood/osd mode settings. 4 slat i the latch signal input pin. data is saved at l level. also used for ood/osd mode settings. 5 0out o a sink type constant current output pin. 6 1 out o a sink type constant current output pin. 7 2out o a sink type constant current output pin. 8 3 out o a sink type constant current output pin. 9 4out o a sink type constant current output pin. 10 5 out o a sink type constant current output pin. 11 6out o a sink type constant current output pin. 12 7 out o a sink type constant current output pin. 13 8out o a sink type constant current output pin. 14 9 out o a sink type constant current output pin. 15 10out o a sink type constant current output pin. 16 11 out o a sink type constant current output pin. 17 12out o a sink type constant current output pin. 18 13 out o a sink type constant current output pin. 19 14out o a sink type constant current output pin. 20 15 out o a sink type constant current output pin. 21 oe i the constant current output enable signal input pin. during the ?h? level, the output will be forced off. also used for ood/osd mode settings. 22 sout o the serial data output pin. this pin outputs the od/osd detection result data. 23 r ext ? the constant current value setting resistor connection pin. 24 v dd ? the power supply input pin.
tca62746afg/afng 2007-11-27 6 absolute maximum rating s (t a = 25c) characteristics symbol rating *1 unit power supply voltage v dd ? 0.4 to 6.0 v output current i o 55 ma logic input voltage v in ? 0.3 to v dd + 0.3 *2 v output voltage v o ? 0.3 to 17 v operating temperature t opr ? 40 to 85 c storage temperature t stg ? 55 to 150 c thermal resistance r th(j-a) 94(afg type when mounted pcb)/120(afng type when mounted pcb) *3 c/w power dissipation p d 1.32(afg type when mounted pcb)/1.04(afng type when mounted pcb) *3,4 w note1: voltage is ground referenced. note2: however, do not exceed 6v. note3: pcb condition 76.2 x 114.3 x 1.6 mm, cu 30% (semi conforming) note4: the power dissipation decreases t he reciprocal of the saturated thermal resistance (1/ rth(j-a)) for each degree (1c) that the ambient temperature is exceeded (ta = 25c). recommended operating conditions dc items (unless otherwise specified, t a = ? 40c to 85c) characteristics symbol test conditions min typ. max unit power supply voltage v dd ? 4.5 ? 5.5 v output voltage when off v o (off) outn ? ? 16 v output voltage when on v o (on) outn 0.7 ? 4 v high level logic input voltage v ih ? 2.0 ? v dd v low level logic input voltage v il ? gnd ? 0.8 v high level sout output current i oh v dd = 5 v ? ? ? 1 ma low level sout output current i ol v dd = 5 v ? ? 1 ma constant current output i o outn 2 ? 50 ma ac items (unless otherwise specified, v dd = 4.5 to 5.5 v, t a = ? 40c to 85c) characteristics symbol test circui ts test conditions min typ. max unit serial data transfer frequency f sck 7 ? ? ? 25 mhz clock pulse width t wsck 7 sck = ?h? or ?l? 20 ? ? ns latch pulse width t wslat 7 slat = ?h? 20 ? ? ns t woe1 7 oe = ?h? or ?l? ,r ext = 500 100 ? ? ns enable pulse width t woe2 ? when error is detected *1 2 ? ? s t hold1 7 ? 5 ? ? ns t hold2 7 ? 5 ? ? ns t hold3 7 ? 10 ? ? ns hold time t hold4 7 ? 10 ? ? ns t setup1 7 ? 5 ? ? ns t setup2 7 ? 5 ? ? ns t setup3 7 ? 10 ? ? ns setup time t setup4 7 ? 10 ? ? ns maximum clock rise time t r 7 *2 ? ? 500 ns maximum clock fall time t f 7 *2 ? ? 500 ns note1: please refer to page 16 for details of the error detection. note2: if the device is connected in a cascade and the tr/tf of t he clock waveform increases due to deceleration of the clock w aveform, it may not be possible to achiev e the timing required for data transfer. pleas e keep these timing condi tions in mind when designing your application.
tca62746afg/afng 2007-11-27 7 electrical characteristics (unless otherwise specified, v dd = 4.5 to 5.5 v and t a = 25c) characteristics symbol test circui ts test conditions min typ. max unit high level logic output voltage v oh 1 i oh = ? 1 ma, sout v dd ? 0.4 ? ? v low level logic output voltage v ol 1 i oh = + 1 ma, sout ? ? 0.4 v high level logic input current i ih 2 v in = v dd , oe , sin, sck ? ? 1 a low level logic input current i il 3 v in = gnd, slat , sin, sck ? ? ? 1 a i dd1 4 v o = 16 v, no r ext sck = ?l?, oe = ?h? ? 0.1 0.5 ma i dd2 4 r ext = 1.56 k , all output off ? ? 7.0 ma i dd3 4 r ext = 500 , all output off ? ? 14.0 ma i dd4 4 r ext = 1.2 k , all output on ? ? 7.0 ma power supply current i dd5 4 r ext = 500 , all output on ? ? 14.0 ma i o1 *1 5 v dd = 5.0v, v o = 1.0 v, r ext = 1.56 k 14.1 15 15.9 ma constant current output i o2 5 v dd = 5.0v, v o = 1.0 v, r ext = 500 44.2 47 49.8 ma output off leak current i ok 5 v o = 16 v, r ext = 1.56 k , all output off ? ? 0.5 a constant current error i o 5 v dd = 5.0v, v o = 1.0 v, r ext = 1.56 k , 0 out to 15out ? 1 3 % constant current power supply voltage regulation %v dd 5 v dd = 4.5 to 5.5v, v o = 1.0 v, r ext = 1.56 k , 0 out to 15out ? 1 4 %/v constant current output voltage regulation %v o 5 v dd = 5.0v, v o = 1.0 to 3.0 v, r ext =1.56 k , 0 out to 15out ? 1 4 %/v pull-up resistor r up 3 oe 250 500 800 k pull-down resistor r down 2 slat 250 500 800 k note1: tca62746afg is guaranteed by t his specification manufactured after the week 47 of 2007 (weekly code 747). tca62746afng is guaranteed by t his specification. electrical characteristics during ood/osd mode (unless otherwise specified, v dd = 4.5 to 5.5 v and t a = 25c) characteristics symbol test circui ts test conditions min typ. max unit ood voltage v ood 6 r ext = 464 to 11.5 k ? 0.30 0.40 v osd voltage v osd 6 r ext = 464 to 11.5 k 2.85 3.0 ? v
tca62746afg/afng 2007-11-27 8 switching characteristics (unless otherwise specified, t a = 25c and v dd = 5.0 v) characteristics symbol test circui ts test conditions min typ. max unit sck- 0out t plh1 7 slat = ?h?, oe = ?l? ? 20 100 slat - 0 out t plh2 7 oe = ?l? ? 20 100 oe - 0out t plh3 7 slat = ?h? ? 20 100 sck-sout t plh 7 ? 5 10 ? sck- 0out t phl1 7 slat = ?h?, oe = ?l? ? 50 100 slat - 0 out t phl2 7 oe = ?l? ? 50 100 oe - 0out t phl3 7 slat = ?h? ? 50 100 propagation delay time sck-sout t phl 7 ? 15 20 ? ns output rise time t or 7 10 to 90% of voltage waveform ? 30 150 ns output fall time t of 7 90 to 10% of voltage waveform ? 70 150 ns output delay time t dly (on) 7 outn - )1n(out + between adjacent outputs ? 20 ? ns output delay time t dly (off) 7 outn - )1n(out + between adjacent outputs ? 20 ? ns
tca62746afg/afng 2007-11-27 9 i/o equivalent circuits 1. sck, sin 2. oe 3. slat 4. sout 5. out0 to out15 v dd gnd slat v dd (sck) (sin) gnd v dd sout gnd v dd oe gnd 0 out to 15out gnd
tca62746afg/afng 2007-11-27 10 test circuits sck sin oe v dd out0 out7 out15 sout gnd r ext i o = -1ma to 1ma c l 10.5 pf v dd 4.5 to 5.5 v f. g v ih v dd v il 0 v t r t f 10 ns (10 to 90%) slat test circuit1: high level logic input voltage / low level logic input voltage r ext sck sin oe v dd out0 out7 out15 sout gnd r ext c l 10.5 pf v dd 4.5 to 5.5 v slat test circuit2: high level logic input current / pull-down resistor r ext v in = v dd a a a a sck sin oe v dd out0 out7 out15 sout gnd r ext c l 10.5 pf v dd 4.5 to 5.5 v slat test circuit3: low level logic input current / pull-up resistor r ext a a a a v
tca62746afg/afng 2007-11-27 11 test circuit4: po wer supply current test circuit6: ood voltage / osd voltage all output terminals is set to turning on, only one output terminal is connected with the v o2 power supply, and v o2 is changed. v ood /v osd is confirmed by the error detection result from sout. test circuit5: constant current output / output off leak curr ent / constant current error test circuit5: constant current power supply voltage regulati on / constant current output voltage regulation v o = 1v, 3v, 16v r ext = 1.56k , 500 sck sin oe v dd out0 out7 out15 sout gnd r ext c l = 10.5 pf v dd = 4.5 to 5.5v slat f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) a a a sck sin oe v dd out0 out7 out15 sout gnd r ext c l = 10.5 pf v dd = 4.5 to 5.5v slat r ext = 1.56k , 500 f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) a sck sin oe v dd out0 out7 out15 sout gnd r ext c l = 10.5 pf v dd = 4.5 v to 5.5 v slat r ext = 464 , 11.5k f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) v o1 = 1 v v v v v o2
tca62746afg/afng 2007-11-27 12 output delay circuit this is designed for high speed switching between outp uts and is intended to have the effect of reducing switching noise by reducing the di/dt when all outputs are on or off at the same time. there is a switching time lag (20 ns typ.) between adjacent outputs. the equivalent circuit chart of the de lay circuit is shown in the following. sck sin oe v dd out0 r l = 85 c l out7 c l r l out15 c l = 10.5 pf r l sout gnd r ext c l = 10.5 pf v dd = 4.5 to 5.5 v slat test circuit7: switching characteristics r ext = 500 f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) v led =5v delay delay out2 2 delay delay out15 15 d15 d2 delay out1 1 d1 out0 d0 oe
tca62746afg/afng 2007-11-27 13 timing waveforms 1. sck, sin, sout 2. sck, sin, slat , oe , out0 3. out0 t hold1 t plh /t phl t wsck 50% 50% 50% 50% t setup1 sin sck sout 50% 90% 10% t r t f 90% 10% t wsck 50% t woe1 50% t hold2 sin sck 50% 50% 50% 50% t phl1 /t plh1 t phl2 /t plh2 t wslat oe out0 50% slat 50% t setup2 10% 90% 10% 90% t or out0 off on 50% 50% 50% 50% t woe1 tplh3 tphl3 oe t of
tca62746afg/afng 2007-11-27 14 4. ood mode/osd mode 5. ood/osd read mode t hold3 twsck 50% 50% t setup3 sck 50% 50% 50% t setup4 t hold4 50% 50% slat oe sck 50% 50% 50% t woe2 50% oe
tca62746afg/afng 2007-11-27 15 pwm grayscale control this ic is possible to pwm grayscale control by the input of the pwm signal to the en terminal. when pwm grayscale control is done, we recommend the led power-supply voltage to be set to become the satiety region of the constant current ch aracteristic. when using this ic outside the satura tion area, pwm grayscale control cannot be normally done. switching to open circuit detection (ood ) and short circuit detection (osd) mo des switching to osd mode the signal sequence set to be in the osd mode. here, the slat active pulse would not latch any data. switching to ood mode the signal sequence set to be in the ood mode. here, the slat active pulse would not latch any data. h sck slat oe 1 2 3 4 5 6 lh h h h l ll h l l h sck slat oe 1 2 3 4 5 6 lh h h h l ll l l h
tca62746afg/afng 2007-11-27 16 reading error status code when the above signal sequence is set in the ood and os d modes, the error state code can be read through the terminal sout. error state code of ood detection mode error state code state of output terminal v ood v o 0 open circuit v ood < v o 1 normal error state code of osd detection mode error state code state of output terminal v osd v o 0 short circuit v osd > v o 1 normal description in the ood and osd modes, the state of oe must be switched from ?h? to ?l?. and, then, this ic would execute open-/short-circuit detection as well as enabling output port s to drive current. at least three clock must be inputs at the ?l? state of oe and the third clock should be at least 2 s after the falling edge of oe . the detected error status into the built-in shift register is done by rising edge of this third clock. when oe is ?l", the serial data cannot be input from the terminal sin. when oe is changed from ?l" to ?h", the error stat e code is output from the terminal sout synchronizing wi th the clock. switching to normal mode the signal sequence set to be in the normal mode. h sck slat oe 1 2 3 4 5 6 lh h h h l ll l l l ?l? level h sck oe 12 l h h h h error status code sout bit 15 h bit 14 bit 13 bit 12 bit 11 bit 10 l 3 min 2 s n > = 3 l
tca62746afg/afng 2007-11-27 17 timing chart of error detection mode (osd mode) sck slat oe sin, 0 tca62746, 0 sout, 0 tca62746, 1 sout, 1 sin, 1 tca62746, 2 sout, 2 sin, 2 tca62746, n-2 tca62746, n-1 sout, n-1 3 clk or more n 15 clk a. switching to error detection mode sck sin slat oe 1 2 3 4 5 6 1 2 3 4 5 6 sin, 0 0 12 2clk 2 s don?t care 1415 sout, 0 3031 sout, 1 n 16-1 sout, n-1 b. setting of output terminal that does the erro r e. switching to normal c. detection the error d. reading back the error status code error: 0, normal: 1 n 16 clk n 16-1
tca62746afg/afng 2007-11-27 18 reference data *this data is provided for reference only. thorough evaluation and testing should be implemented when designing your application's mass production design. set output current ? duty cycle graph i o - duty 0 10 20 30 40 50 60 0 20 40 60 80 100 duty - turn on rate (%) i o (ma) tca62746fg tca62746fng i o - duty 0 10 20 30 40 50 60 0 20 40 60 80 100 duty - turn on rate (%) i o (ma) tca62746fg tca62746fng i o - duty 0 10 20 30 40 50 60 0 20406080100 duty - turn on rate (%) i o (ma) tca62746fg tca62746fng p d - ta 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 102030405060708090 ta ( ) p d (w) tca62746fg tca62746fng on pcb v dd =5.5v v o =1.0v t a =25c on pcb all output on tca62746afg tca62746afng tca62746afg tca62746afng tca62746afg tca62746afng tca62746afg tca62746afng v dd =5.5v v o =1.0v t a =55c on pcb all output on v dd =5.5v v o =1.0v t a =80c on pcb all output on
tca62746afg/afng 2007-11-27 19 reference data *this data is provided for reference only. thorough evaluation and testing should be implemented when designing your application's mass production design. output current ? r ext resistor constant current characteristic i o - r ext 0 5 10 15 20 25 30 35 40 45 50 0123456789101112 r ext (k ? ) i o (ma) theoretical value i o (a) = (1.23(v) y r ext (: )) u 19 v dd =5.0v v o =1.0v t a =25c i o - v o 0 10 20 30 40 50 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v o (v) i o (ma) v dd =5.0v v o =1.0v t a =25c
tca62746afg/afng 2007-11-27 20 package dimensions weight: 0.32 g (typ.)
tca62746afg/afng 2007-11-27 21 package dimensions weight: 0.14 g (typ.)
tca62746afg/afng 2007-11-27 22 serge resisting the terminals which are weak to electro static discharge are shown in the following table. mm model esd test result (internal standard 200v) - serge + serge pin standard test result standard test result 1 v dd 200v v dd 200v 2 v dd ,gnd 200v v dd ,gnd 200v 3 v dd ,gnd 200v v dd ,gnd 200v 4 v dd ,gnd 200v v dd ,gnd 200v 5 v dd ,gnd 200v v dd ,gnd 160v 6 v dd ,gnd 200v v dd ,gnd 160v 7 v dd ,gnd 200v v dd ,gnd 160v 8 v dd ,gnd 200v v dd ,gnd 160v 9 v dd ,gnd 200v v dd ,gnd 160v 10 v dd ,gnd 200v v dd ,gnd 160v 11 v dd ,gnd 200v v dd ,gnd 160v 12 v dd ,gnd 200v v dd ,gnd 160v 13 v dd ,gnd 200v v dd ,gnd 160v 14 v dd ,gnd 200v v dd ,gnd 160v 15 v dd ,gnd 200v v dd ,gnd 160v 16 v dd ,gnd 200v v dd ,gnd 160v 17 v dd ,gnd 200v v dd ,gnd 160v 18 v dd ,gnd 200v v dd ,gnd 160v 19 v dd ,gnd 200v v dd ,gnd 160v 20 v dd ,gnd 200v v dd ,gnd 160v 21 v dd ,gnd 200v v dd ,gnd 200v 22 v dd ,gnd 200v v dd ,gnd 200v 23 v dd ,gnd 200v v dd ,gnd 200v 24 gnd 200v gnd 200v
tca62746afg/afng 2007-11-27 23 notes on contents 1. block diagrams some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. test circuits components in the test circuits are used only to ob tain and confirm the device characteristics. these components and circuits are not gua ranteed to prevent malfunction or failure from occurring in the application equipment.
tca62746afg/afng 2007-11-27 24 ic usage considerations notes on handling of ics [1] the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or det erioration, and may result injury by explosion or combustion. [2] use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or ic failure. the ic will fully brea k down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed im properly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a la rge current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resu lting from the inrush current at power on or the negative current resulting from the back elec tromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built-in protec tion functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. [4] do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative termi nals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, dam age or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. if there is a large amount of leakage current such as input or negative feedback condenser, the ic output dc voltage will increase. if this output voltage is conn ected to a speaker with low input withstand voltage, overcurrent or ic failure can cause smoke or ignition . (the over current can cause smoke or ignition from the ic itself.) in particular, please pay attenti on when using a bridge tied load (btl) connection type ic that inputs output dc voltage to a speaker directly.
tca62746afg/afng 2007-11-27 25 restrictions on product use 20070701-en ? the information contained herein is subject to change without notice. ? toshiba is continually working to improve the quality a nd reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshib a products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semicondu ctor devices,? or ?toshiba semiconductor reliability handbook? etc. ? the toshiba products listed in this document are in tended for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.).these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage incl ude atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traf fic signal instruments, comb ustion control instruments, medical instruments, all types of safety devices, et c.. unintended usage of toshiba products listed in his document shall be made at the customer?s own risk. ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. ? the information contained herein is presented only as a gui de for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implic ation or otherwise under any patents or other rights of toshiba or the third parties. ? please use these products in this document in compliance wi th all applicable laws and regulations that regulate the inclusion or use of controlled substances. toshiba assume s no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. ? the products described in this document are subject to foreign exchange and foreign trade control laws.

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