,', table 2. summary of WD8250 accessible registers .,jl3,h ,)fa\. 2 ~~gl~'~r addntu ,lnterh/th ideriti'i- - 1 line , catioo;," ,control., 'regster ' 'registei, data bitl data bit 1 enable tra ns- mitter holding register empty, interrupt (etbei) , enable receiver line status interrupt (els!) ,"" 2' data bit 2 oatabl12,- v,", 3 data bii 3 . enable modem status interrupt (eossi) data blt;3 4 o data 81!4 5 data bit s o data 81t 5 6 data bit 6 data bit 6 o 7 data 81t 7 data bit 7 o ::. "o'~iv:" interrupt pending interrupt id bit (o) interrupt id bit (1) , o o o o o word " length;, , select' bit o : i ,; (wlso) word length select bit i (wls 1) n'jmber of stop i bits (stb) set break divisor latch access bit (dlab) odlab 1 !~i~ i ~;~jt~~~~~t < r~igt,lg:'a~~tr:'\:l'\,l=ieg!~te;'}: jf~~ff4 ii:~i !~~~~; c' " out i trailing parity i edge fb,ng error,~ indica,tor, (pe) (teri) , trans- mitter > holding register e~pty (thre) data set i ready (osr) . bit 5 '. o trans. mitter shltt register empty (tsre) bit 6 ring indlcator (ri) '" ',' c! / o o '8,t o is the least significant bit it is the first bit senally transmitted or .. ~6 bi~ ~ .". ' _if':;;' , ',o \lll o'::ot. ~ "';';,"'. -. " table 5. 'interrupt control 'funtions. .' . ,:".-j<";;, .'. ""', , ,'.' intcrrupt identification rcgl::!cr bit 2 o ' bit f priority interrupt .. level flag '. ~-:'r none bit o 1 o , . ,',' - ,.,",. . o . :0-;. o ,--- - gic 1 ~~n-e~e~ number of bits is transmitted or '. iecked, t 5: this bit is the stick parity bit. when bit 3 is a 9'c 1 and bits is a 109ic 1, the parity bit is transmit- d and then detected by the receiver in the opposite jle indicated by bit 4, t 6: this bit is the set break control bit. when bit 6 a 10gic 1, th~ serial output (so ut) is forced 10 the sle 3. baud rates using 1.8432 mhz crystal. 'eo 18432 mhlls inc sta dard'oo80 trequcr1cy drvlded by 10. ~ 201 ; ~ djjjj ~~ xk~ .:- ',>.'.' receiver ;.);,;. . data available ' interrupt set and reset functloi18-.: "'..:: ' .. "'. .'.-:.:.:;..' ...',.:';'v;"--- - : interrupt, -', - int.errupt~,.. sou'rce -: '; '; r~~~tc()nt,ro,1 :- none. . ~zf.~;:~~:~,;i!;~::i.:;:-, overrunerror or . . p,arity ,error ot;, fr~rding error or "'.' :break:lnterruptn. jf~;if~f~j"~1~fil .'~~~jw1i~!f~f;?"],'~: . . . . jf;!e~ci.ingjhe.iif:1,;,~\.:, ~, r~gls"tel(it~4rc:~""j ,,- ;:~~fr~~~~i1~~~y~~~;;~" .,1 transmltter;holding;.:-; , 'ij~9is}~(~1~;~h~~q{i-?~;;~:-'. clearto se"d ors;d-ib:~~:~tf~x'~~~~:~'f~i:j;", . -data set ready ore ~r~adlng:!~:tz).1~';!r;;:.~\~'~ ring'lndicator or\' :modem~s.af~s~~/~.:: :~\;)~: . ~~~e~~~e~~~~ .,"". ~~~'st~r.:::x~:~~6~'~;',.:~,~ : generat?'k-3:t m hz:' however:~:whe-r. -.usrng"".' , dlvl.sors of 6, a~d below,'the maximu'mfrequeri~y, , . is equal to 1/2 the divisor inmhz. for example, " .. . if the divi sor is 1, then the maximum frequenoy is 1/2 mhz. in no case should the data rate be greater than 56k baud, line status register this 8-bit register provides status information to the cpu concerning the data transfer. the contenls of table 4. baud rates using 3.072 mhz crystal. -- -- desired divisor used percent error baud 10 generale dilference 8etween rate 16x clock desired and actual 5j 2304 - 75 1536 - 110 1047 0.026 13 5 657 0.058 150 768 - 300 384 - 600 192 - 1200 96 - 1800 64 - 2000 58 0.69 2400 48 - 3600 32 - 4800 24 - 7200 16 - 9600 12 - 19200 6 - 38<100 3 - - 56000 2 286 desired divisor used percent error baud to generale dilltence between rate 16x clock des ed and aclual 50 3840 - 75 2560 - 110 1745 0.026 1345 1428 0.034 150 1280 - 300 640 - 600 320 - 1200 160 - 1800 107 - 2000 96 - 2400 80 - 3600 53 ' 0628 4800 -. 40 - 7200 27 1.23 9600 20 - 19200 1(}. - 38400 5 - 56000 3 '4 285
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