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HT82A850R audio mcu rev. 1.10 1 july 25, 2007 general description the HT82A850R is an 8-bit high performance risc-like microcontroller designed for usb phone product appli - cations. the HT82A850R integrates a 16-bit pcm adc and an 8-bit mcu into a single device. the dac in the HT82A850R operates at a sampling rate of 48/8khz and the 16-bit pcm adc operates at a frequency of 8khz for the microphone input. the dac in the HT82A850R also has a digital programmable gain am- plifier, whose gain ranges from 32db to +6db. for the adc input, the digital gain range is from 0db to 19.5db. features operating voltage: f sys = 6mhz/12mhz: 3.3v~5.5v low voltage reset function (3.0v 0.3v) embedded high performance 16 bit pcm dac built-in digital programmable gain amplifier - pga high-performance 48khz/8khz sampling rate for au - dio software playback 8khz audio recording sampling rate embedded class ab power amplifier for speaker driving audio playback digital volume control 4096 15 program memory 384 8 data memory ram (bank0,1) programmable frequency divider - pfd integrated spi hardware circuit play/record interrupt halt function and wake-up feature reduce power consumption 24 bidirectional i/o lines (max.) two 16-bit programmable timer/event counter and overflow interrupts watchdog timer 16-level subroutine nesting bit manipulation instruction 15-bit table read instruction 63 powerful instructions all instructions executed within one or two machine cycles 48-pin lqfp package
block diagram HT82A850R rev. 1.10 2 july 25, 2007

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pin assignment pin description pin name i/o description pa0~pa7 i/o bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by a con - figuration option. software instructions determine if the pin is a cmos output or a schmitt trigger input. pull-high resistor can be connected to the pins via configuration options - nib- ble option. avdd2 audio power amplifier positive power supply rout o right driver analog output lout o left driver analog output avss2 audio power amplifier negative power supply, ground avss1 audio dac negative power supply, ground bias a capacitor should be connected between this pin and ground for half-supply stability music_in i power amplifier signal source if register bit selw = 1 . the analog signal input will be am - plified by the power amp then output to pins rout and lout at the same time. avdd1 audio dac positive power supply avdd3 adc positive power supply vagref o adc analog ground reference voltage - should be left open or connected via a bypass ca - pacitor (ex:100pf) to ground vag o adc analog ground voltage - should be connected via a bypass capacitor (ex:1 f) to ground ti+ i op amp non-inverting input ti- i op amp inverting input tg o op amp gain setting output avss3 adc negative power supply, ground pb0~pb7 i/o bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or a schmitt trigger input. pull-high resistor can be connected to the pins via configu - ration options - nibble option. dvss2 negative digital & i/o power supply, ground pc7/sck i/o can be software optioned as a bidirectional input/output or serial interface clock signal. HT82A850R rev. 1.10 3 july 25, 2007
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pin name i/o description pc6/scs i/o can be software optioned as a bidirectional input/output or serial interface slave select signal. pc5/sdi i/o or o can be software optioned as a bidirectional input/output or serial data input. pc4/sdo i/o or o can be software optioned as a bidirectional input/output or serial data output. pc3 i/o bidirectional i/o lines. software instructions determine if the pin is a cmos output or a schmitt trigger input. pull-high resistor can be connected to the pins via configuration options. pc2/tmr1, pc1/tmr0 i/o software instructions determine if the pin is a cmos output or a schmitt trigger input. pull-high resistor can be connected to the pins via configuration options.tmr0, tmr1 are pin shared with pc1, pc2 respectively. pc0/bz i/o or o can be software optioned as a bidirectional input/output or as a pfd output. osci osco i o osci, osco are connected to an 6mhz or 12mhz crystal/resonator (determined by soft - ware instructions) for the internal system clock reset i schmitt trigger reset input, active low nc no connection dvdd1 positive digital power supply dvss1 negative digital power supply, ground absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3.3v 3.3 3.6 5.5 v i dd1 operating current 3.3v no load, f sys =12mhz adc on, dac on 9 ma i dd2 operating current 3.3v no load, f sys =12mhz adc off, dac off 5 ma i stb standby current 3.3v no load, system halt 155 a v il1 input low voltage for i/o ports 3.3v 0 0.3v dd v v ih1 input high voltage for i/o ports 3.3v 0.7v dd v dd v v il2 input low voltage (reset ) 3.3v 0 0.4v dd v v ih2 input high voltage (reset ) 3.3v 0.9v dd v dd v i ol i/o port sink current 3.3v v ol =0.1v dd 3 ma i oh i/o port source current 3.3v v oh =0.7v dd 2 ma r ph pull-high resistance 3.3v 110 80 40 k v lvr low voltage reset 3.3v 2.7 3 3.3 v HT82A850R rev. 1.10 4 july 25, 2007
symbol parameter test conditions min. typ. max. unit v dd conditions dac+power amp test condition: measurement bandwidth 20hz to 20khz, f s = 48khz. line output series capacitor with 220 f. thd+n thd+n note 5v 4 load 30 db 8 load 35 snr da signal to noise ratio note 5v 4 load 81 db 8 load 82 dr dynamic range 5v 4 load 87 db 8 load 88 p out output power 5v 4 load, thd=10% 400 mw/ch 8 load, thd=10% 200 pcm adc snr ad signal to noise ratio 3.3v 77 db vag reference voltage 3.3v 1.12 v v peak peak single frequency tone amplitude without clipping 3.3v 1.575 v pk note: sine wave input at 1khz, 6db a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc) 3.3v 0.4 12 mhz t wdtosc watchdog oscillator period 3.3v 100 s t res reset input pulse width 1 s t sst system start-up timer period 1024 t sys t int interrupt pulse width 1 s note: t sys =1/f sys HT82A850R rev. 1.10 5 july 25, 2007
HT82A850R rev. 1.10 6 july 25, 2007 functional description execution flow the microcontroller system clock is sourced from a crys - tal oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle con - sists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to be effectively executed in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter, pc, controls the sequence in which the instructions stored in the program memory are executed. its contents specify the full program memory range. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, a conditional skip execution, loading to the pcl register, performing a subroutine call or returning from a subroutine, an initial reset, an internal interrupt, external interrupt or return from interrupts, the pc manipulates the program trans - fer by loading the address corresponding to each in - struction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise the next instruction is executed. the lower byte of the program counter, pcl, is a read - able and writeable register. moving data into the pcl performs a short jump. the destination will be within the current program memory page. when a control transfer takes place, an additional dummy cycle is required. . 4 - . 4 - . 4 - 8 " % % : < ' @ % % : 1 < 8 " % % : = < ' @ % % : < 8 " % % : = . < ' @ % % : = < = = . % &
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& < execution flow mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000 reserved 000000000100 timer/event counter 0 overflow 000000001000 timer/event counter 1 overflow 000000001100 play interrupt 000000010000 serial interface interrupt 000000010100 record interrupt 000000011000 skip program counter+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *11~*0: program counter bits s11~s0: stack register bits #11~#0: instruction code bits @7~@0: pcl bits
HT82A850R rev. 1.10 7 july 25, 2007 program memory the program memory is used to store the executable program instructions. it also contains data, table, and in - terrupt entries, and is organized into 4096 15 bits, ad - dressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage: location 000h this location is reserved for program initialisation. af - ter a device reset, the program always begins execu - tion at location 000h. location 008h this location is reserved for the timer/event counter 0 interrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in - terrupt is enabled and the stack is not full, the program will jump to this location and begin execution. location 00ch this location is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter - rupt is enabled and the stack is not full, the program will jump to this location and begin execution. location 010h this location is reserved for the play interrupt service program. if the play data is valid, and the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution. location 014h this location is reserved for when 8 bits of data have been received or transmitted successful from the se - rial interface. if the related interrupts are enabled, and the stack is not full, the program will jump to this loca - tion and begin execution. location 018h this location is reserved for the record interrupt ser - vice program. if the record data valid, the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution. table location any location in the program memory can be used as a look-up table. there are three method to read the pro - gram memory data. the first method uses the tabrdc instruction to transfer the contents of the current page lower-order byte to the specified data memory, and the current page higher-order byte to the tblh register. the second method uses the tabrdl instruction to transfer the contents of the last page lower-order byte to the specified data memory, and the last page higher-order byte to the tblh register. the third method uses the tabrdc instruction to - gether with the tblp and tbhp pointers to transfer the contents of the lower order byte at the specified address to the specified data memory, and the higher order byte at the specified address to the tblh regis- ter. before accessing the table data, the address to be read must be placed in the table pointer registers, tblp and tbhp. note that if the configuration option tbhp is disabled, then the value in tbhp has no ef- fect. only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the remaining 1-bit word is read as 0 .the table higher-order byte register, tblh, is read only. the tblh register is read only and cannot be restored. if the main routine and the isr (interrupt service rou - tine) both employ the table read instruction, the con - tents of tblh in the main routine are likely to be changed by the table read instruction used in the isr. in such cases errors can occur. therefore, using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the ta - ble read instruction has to be used in both the main routine and the isr, the interrupt should be disabled
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) ) ) c ) ) c ) ) c ) - c ) > c ) . ) c 8 8 8 c ) / c program memory instruction table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111@7@6@5@4@3@2@1@0 table location note: *11~*0: table location bits p11~p8: current program counter bits when tbhp is disabled @7~@0: table pointer bits tbhp register bit3~bit0 when tbhp is enabled
HT82A850R rev. 1.10 8 july 25, 2007 prior to the table read instruction. it should not be re-enabled until tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending upon require - ments. stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organised into 16 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer, sp, which is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, using ret or reti, the inter - rupt will be serviced. this feature prevents a stack over- flow allowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is subsequently executed, a stack overflow will occur and the first entry will be lost. only the most recent 16 re- turn addresses are stored. data memory the data memory is divided into two functional groups. these are the special function registers and the general purpose data memory in bank0 and bank1: 384 8 bits. most are read/write, but some are read only. the special function registers are overlapped in all banks. any unused space before 40h is reserved for future ex - panded usage and if read will return a value of 00h . the general purpose data memory, addressed from 40h to ffh, is used for data and control information under in - struction commands. all data memory areas can handle arithmetic, logical, in - crement, decrement and rotate operations directly. ex - cept for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through the memory pointer registers, mp0 or mp1. & %
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HT82A850R rev. 1.10 9 july 25, 2007 indirect addressing register locations 00h and 02h are the indirect addressing reg - isters, however they are not physically implemented. any read/write operation to [00h] or [02h] will access the data memory pointed to by mp0 and mp1. reading location 00h or 02h indirectly will return a result of 00h. writing indirectly results in no operation. data transfer between two indirect addressing registers is not supported. the memory pointer registers, mp0 and mp1, are 8-bit registers which are used to access the data memory in combination with indirect address - ing registers. bank pointer the bank pointer is used to select the required data memory bank. if data memory bank 0 is to be selected, then a 0 should be loaded into the bp register. data memory locations before 40h in any bank are over - lapped. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera- tions. the alu provides the following functions: arithmetic operations - add, adc, sub, sbc, daa logic operations - and, or, xor, cpl rotation - rl, rr, rlc, rrc increment and decrement - inc, dec branch decision - sz, snz, siz, sdz .... the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the op - eration sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults from those intended. the to flag can be affected only by a system power-up, a wdt time-out or executing the clr wdt or halt instruction. the pdf flag can be affected only by exe - cuting the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, upon entering the interrupt sequence or exe - cuting a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides an internal timer/event counter in- terrupt, play/record data valid interrupt and a serial inter- face interrupt. the interrupt control register0, intc0, and the interrupt control register1, intc1:1eh, both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. once an interrupt subroutine is serviced, other inter - rupts are all blocked, as the emi bit is cleared automati - cally, preventing further interrupt nesting. other interrupt bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register
HT82A850R rev. 1.10 10 july 25, 2007 requests may take place during this interval, but only the interrupt request flag will be recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of intc0 or of intc1 may be set in order to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowl - edged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack should be prevented from becoming full. all interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the pro - gram counter onto the stack, followed by a branch to a subroutine at a specified location in the program mem - ory. only the program counter is pushed onto the stack. if the contents of the register or status register are al - tered by the interrupt service program, which may cor - rupt the desired control sequence, the contents should be saved in advance. the internal timer/event counter 0 interrupt is initial - ised by setting the timer/event counter 0 interrupt re - quest flag, bit 5 of intc0, caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag, t0f, will be re - set and the emi bit cleared to disable further interrupts. the internal timer/even counter 1 interrupt is initialised by setting the timer/event counter 1 interrupt request flag, bit 6 of intc0, caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and the t1f is set, a subroutine call to location 0ch will occur. the related interrupt request flag, t1f, will be reset and the emi bit cleared to disable further interrupts. the play interrupt is initialised by setting the play inter - rupt request flag, bit 4 of intc1, caused by a valid play interrupt. when the interrupt is enabled, the stack is not full and playf is set, a subroutine call to location 10h will occur. the related interrupt request flag, playf, will be reset and the emi bit cleared to disable further inter - rupts. if play_mode, bit 3 of the mode_ctrl regis - ter, is set to 1 , the play interrupt frequency will change to 8khz, otherwise the interrupt frequency is 48 khz. the firmware will write 16-bit unsigned data to the dac when a play interrupt occurs. the serial interface interrupt is indicated by the interrupt flag, sif; bit 5 of intc1, that is generated by the recep - tion or transfer of a complete 8-bits of data between the HT82A850R and the external device. the serial inter - face interrupt is controlled by setting the serial interface interrupt control bit, esii; bit 1 of intc1. after the inter - rupt is enabled, by setting sben; bit 4 of sbcr, and the stack is not full and the sif bit is set, a subroutine call to location 14h occurs. the record interrupt is initialised by setting the record in - terrupt request flag, bit 6 of intc1, caused by a record data valid. when the interrupt is enabled, the stack is not full and recf is set, a subroutine call to location 18h will occur. the related interrupt request flag, recf, will be reset and the emi bit cleared to disable further inter- rupts. if the adc is powered down, ad_enb =1, the re- cord interrupt will be disabled. bit no. label function 0 emi controls the master (global) interrupt (1=enabled; 0=disabled) 1, 4, 7 unused bit, read as 0 2 et0i controls the timer/event counter 0 interrupt (1=enabled; 0=disabled) 3 et1i controls the timer/event counter 1 interrupt (1=enabled; 0=disabled) 5 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 6 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) intc 0 (0bh) register bit no. label function 0 eplayi play interrupt (1= enabled; 0= disabled) 1 esii control serial interface interrupt (1= enabled; 0= disabled) 2 ereci record interrupt (1= enabled; 0= disabled) 3, 7 unused bit, read as 0 4 playf play interrupt request flag (1= active; 0= inactive) 5 sif serial interface interrupt request flag (1= active; 0= inactive) 6 recf record interrupt request flag (1= active; 0= inactive) intc 1 (1eh) register
HT82A850R rev. 1.10 11 july 25, 2007 during the execution of an interrupt subroutine, other in - terrupt acknowledge signals are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, a ret or reti instruction should be executed. a reti instruction will set the emi bit to enable an interrupt service, but a ret instruction will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector reserved 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch play interrupt 4 10h serial interface interrupt 5 14h record interrupt 6 18h it is recommended that a program does not use the call subroutine within the interrupt subroutine. inter- rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con- trolled, the original control sequence will be damaged once the call operates in the interrupt subroutine. oscillator configuration an internal oscillator circuit is integrated within the microcontroller to implement the system clock. when the device enters the power-down mode the system os - cillator will stop running and external signals will be ignored to conserve power. a crystal across osci and osco is required to provide the feedback and phase shift required for the oscillator. no other external components are required. instead of a crystal, a resonator can also be connected between osci and osco to obtain the correct frequency refer - ence, however two external capacitors between the osci, osco pins and ground are required. a wdt oscillator is also contained within the device. this is a free running fully integrated rc oscillator requiring no external components. even if the system enters the power down mode, where the system clock is stopped, the wdt oscillator continues to run. the wdt oscillator can be disabled by a configuration option to conserve power. watchdog timer wdt the wdt clock source is implemented by its own dedi - cated internal rc oscillator (wdt oscillator) or by using the instruction clock, which is the system clock/4. the wdt timer is designed to prevent a software malfunc - tion or sequence from jumping to an unknown location with unpredictable results. the wdt can be disabled using a configuration option. note that if the wdt is dis - abled, all executions of instructions related to the wdt will result in no operation. when the wdt clock source is selected, it will be first di - vided by 256 (8-stage) to obtain a nominal time-out pe - riod. by using this wdt prescaler, longer time-out periods can be implemented. this is achieved by writing data to the the ws2, ws1, ws0 bits. the wdt osc period has a typical value of 65 s. this time-out period may vary with temperature, vdd and process variations. the wdt osc keeps running in any operational mode. if the instruction clock is selected as the wdt clock source, the wdt operates in the same manner except when the device is in the power-down mode. here the wdt stops counting and loses its protecting function. in this situation the device can only be re-started by exter- nal logic. the high nibble and bit3 of the wdts are re- served for user defined flags, which can be used to indicate some specified status. the wdt overflow under normal operation initialises a chip reset and sets the status bit to .inthe power-down mode, the overflow initialises a warm re - set , where only the pc and sp are reset to zero. to clear the contents of the wdt, there are three methods that can be used, i.e., external reset (a low level on the reset pin), a software instruction, and a halt in - struction. there are two types of software instructions; clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one type of instruction can be active at a time depending on the options clr wdt times selection option. if the clr wdt is selected (i.e., clr wdt times equal one), any execution of the clr wdt instruction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e., clr wdt times equal two), these two in - structions have to be executed to clear the wdt; other - wise, the wdt may reset the chip due to time-out. & % & &
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HT82A850R rev. 1.10 12 july 25, 2007 power down operation the power-down mode is entered by the execution of a halt instruction and results in the following: the system oscillator will be turned off but the wdt oscillator keeps running if the internal wdt oscillator is selected. the contents of the on-chip data memory and regis- ters remain unchanged. the wdt and wdt prescaler will be cleared and will start counting again if the wdt clock is sourced from the internal wdt oscillator. all of the i/o ports remain in their original condition. the pdf flag is set and the to flag is cleared. the system can leave the power-down mode by means of an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external re - set causes a device initialisation and the wdt overflow performs a warm reset . after the to and pdf flags are examined, the cause for the device reset can be de - termined. the pdf flag is cleared by a system power-up or by executing the clr wdt instruction and is set when executing the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; the others remain in their original status. a port a wake-up and interrupt methods can be consid- ered as a continuation of normal execution. each pin in port a can be independently selected to wake-up the de- vice using configuration options. after awakening from an i/o port stimulus, the program will resume execution at the next instruction. if the device is awakened from an interrupt, two sequence may occur. if the related inter- rupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next in - struction. if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. if an in - terrupt request flag is set to 1 before entering the power-down mode, the wake-up function of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock periods) to resume nor - mal operation, i.e., a dummy period is inserted. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimise power consumption, all the i/o pins should be carefully managed before entering the power-down mode. the adc, dac and pa will all be powered down when in the halt mode. % &
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& % watchdog timer bit no. label function 0 1 2 ws0 ws1 ws2 watchdog timer division ratio selection bits bit 2,1,0 = 000, division ratio = 1:1 bit 2,1,0 = 001, division ratio = 1:2 bit 2,1,0 = 010, division ratio = 1:4 bit 2,1,0 = 011, division ratio = 1:8 bit 2,1,0 = 100, division ratio = 1:16 bit 2,1,0 = 101, division ratio = 1:32 bit 2,1,0 = 110, division ratio = 1:64 bit 2,1,0 = 111, division ratio = 1:128 3 unused bit, read as 0 7~4 t3~t0 test mode setting bits (t3, t2, t1, t0)=(0, 1, 0, 1), enter dac write mode. otherwise normal operation. wdts (09h) register
HT82A850R rev. 1.10 13 july 25, 2007 reset there are four ways in which a reset can occur: res reset during normal operation res reset when in the power-down mode wdt time-out reset during normal operation usb reset the wdt time-out when in the power-down mode is dif - ferent from other device reset conditions, since it can perform a warm reset that resets only the program counter and stack pointer, leaving the other circuits in their original state. some registers remain unchanged during other reset conditions. most registers are reset to their initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different device resets . to pdf reset conditions 0 0 reset reset during power-up u u reset reset during normal operation 0 1 reset wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilised, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses when the sys- tem resets (power-up, wdt time-out or res reset) or the system awakes from the power-down mode. when a system reset occurs, the sst delay is added during the reset period. any wake-up from the power-down mode will enable the sst delay. the status of the device after a reset is shown below. program counter 000h interrupt disabled wdt cleared. after a master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack 3 ' ' reset circuit % c !
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HT82A850R rev. 1.10 14 july 25, 2007 the registers status are summarised in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu usvc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu intc1 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ucc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu dac_limit_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu dac_limit_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu dac_wr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pga_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 pfdc 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 pfdd 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 mode_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu sbcr 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu sbdr uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu recoed_ data_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu recoed_ data_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown _ stands for undefined
HT82A850R rev. 1.10 15 july 25, 2007 timer/event counter two timer/event counters are implemented in the microcontroller. each timer contains a 16-bit program - mable count-up counter whose clock may be sourced from an external or internal clock source. the internal clock source comes from f sys /4. the external clock in - put allows external events to be counted, time intervals or pulse widths to be measured, or to generate an accu - rate time base. there are three registers related to timer/event counter 0, tmr0h, tmr0l and tmr0c, and another three related to timer/event counter 1, tmr1h, tmr1l and tmr1c. when writing data to the tmr0l and tmr1l registers, note that the data will only be written into a lower-order byte buffer. the data will not be actually written into the tmr0l and tmr1l reg - isters until a write operation to the tmr0h and tmr1h registers is implemented. reading the tmr0l and tmr1l registers will read the contents of the lower-or - der byte buffer. the tmr0c and tmr1c registers are the timer/event counter control registers, which define the operating mode, the count enable or disable and the active edge. the tm0 and tm1 bits define the operation mode. the event count mode is used to count external events, which means that the clock source is sourced from the external tmr0 or tmr1 pin. the timer mode functions as a normal timer with the clock source coming from the internal clock. finally, the pulse width measurement mode can be used to count the high level or low level du- ration of an external signal on pins tmr0 or tmr1, whose counting is based on the internal clock source. in the event count or timer mode, the timer/event coun- ter starts counting from the current contents in the timer/event counter and ends at ffffh. once an over- flow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re - quest flag (t0f; bit 5 of intc0, or t1f; bit 6 of intc0). in the pulse width measurement mode with the values of the ton and te bits equal to 1, after the tmr0 or tmr1 pin has received a transient from low to high, or high to low if the te bit is 0 , it will start counting until the tmr0 or tmr1 pin returns to its original level and resets the ton bit. the measured result remains in the timer/event counter even if the activated transient occurs again. therefore, only 1-cycle measurement is made. not until the ton bit is again set can the cycle measurement re-function. in this operational mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter over - flows, the counter is reloaded from the timer/event coun - ter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable a count operation, the timer on bit (ton; bit 4 of tmr0c or tmr1c) should be set to 1. in the pulse width measurement mode, ton is automatically cleared after the measurement cycle is completed. but in the other two modes, the ton bit can only be reset by instructions. a timer/event counter overflow is one of the wake-up sources. no matter what the operational mode is, writin ga0to et0i or et1i disables the related interrupt service. if the timer/event counter is turned off, writing data to the timer/event counter preload register will also reload the data into the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event coun- ter preload register. the timer/event counter keeps op- erating until an overflow occurs. when the timer/event counter is read, the clock is blocked to avoid errors, which may result in a counting error. blocking of the clock should be taken into account by the programmer. bit no. label function 0~2, 5 unused bit, read as 0 3te defines the tmr active edge of the timer/event counter in event counter mode (tm1, tm0)=(0, 1): 1=count on falling edge; 0=count on rising edge in pulse width measurement mode (tm1, tm0)=(1, 1): 1=start counting on the rising edge, stop on the falling edge; 0=start counting on the falling edge, stop on the rising edge 4 ton enable/disable the timer counting (0=disable; 1=enable) 6 7 tm0 tm1 defines the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh), tmr1c (11h) register
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: ) ( < # timer/event counter 0/1 input/output ports there are 24 bidirectional input/output lines in the microcontroller, labeled from pa to pc. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h or 16h). for output opera - tion, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc or pcc) to control the input/output configuration. with this control register, either a cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the con - trol register must write 1 . the input source also de- pends on the control register. if the control register bit is 1 the input will read the pad state. if the control register bit is 0 the contents of the latches will move to the in- ternal bus. the latter is possible in the read-modify-write instruction. for output function, cmos configurations can be selected. after a device reset, the input/output lines will default to input high levels or a floating state, depending on the pull-high configuration options. each bit of these in - put/output latches can be set or cleared using the set [m].i and clr [m].i (m=12h, 14h or 16h) instruc - tions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. low voltage reset lvr the lvr function is enabled or disabled using a configu- ration option. the lvr voltage is 3.0v. the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr such as when changing a battery, the lvr will automatically reset the device internally. 3 ) * + / ) * / + ) ( / 9 ( ) . ( 4 - ( ( 0 ( + (
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HT82A850R rev. 1.10 17 july 25, 2007 the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in this condition for a time greater than 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. the lvr uses an or function with the external reset signal to perform a device reset. system clock selection this register consists of system clock selection (sysclk) bit no. label r/w reset functions 0~2 0 reserved 5 f sys 16mhz r/w 0 defines the mcu system clock - sourced from the external osc or from the pll output - 16mhz clock. 0: system clock sourced from osc 1: system clock sourced from the pll output - 16mhz 6 sysclk r/w 0 used to specify the system clock oscillator frequency used by mcu. if a 6mhz crystal oscillator or resonator is used, this bit should be set to 1 . if a 12mhz crystal oscillator or resonator is used. this bit should be cleared to 0 . ucc (22h) register the speaker output volume and speaker mute/un-mute are controlled by the digital volume control register. the range of volume is set from 6 db to 32 db using software. speaker mute control: mute = 0: mute speaker output. mute = 1: normal. bit no. label r/w power-on functions 0~6 usvc0~ usvc6 r/w 0 volume control bit 0~bit 6 7 mute r/w 0 mute control, low active digital volume control (1ch) register result (db) usvc result (db) usvc result (db) usvc result (db) usvc 6 000_1100 2 111_1100 10 110_1100 24 101_1100 5.5 000_1011 2.5 111_1011 10.5 110_1011 25 101_1011 5 000_1010 3 111_1010 11 110_1010 26 101_1010 4.5 000_1001 3.5 111_1001 11.5 110_1001 27 101_1001 4 000_1000 4 111_1000 12 110_1000 28 101_1000 3.5 000_0111 4.5 111_0111 13 110_0111 29 101_0111 3 000_0110 5 111_0110 14 110_0110 30 101_0110 2.5 000_0101 5.5 111_0101 15 110_0101 31 101_0101 2 000_0100 6 111_0100 16 110_0100 32 101_0100 1.5 000_0011 6.5 111_0011 17 110_0011 1 000_0010 7 111_0010 18 110_0010 0.5 000_0001 7.5 111_0001 19 110_0001 0 000_0000 8 111_0000 20 110_0000 0.5 111_1111 8.5 110_1111 21 101_1111 1 111_1110 9 110_1110 22 101_1110 1.5 111_1101 9.5 110_1101 23 101_1101 speaker volume control table
HT82A850R rev. 1.10 18 july 25, 2007 the dac_limit_l and dac_limit_h registers are used to define the 16-bit dac output limit. dac_limit_l and dac_limit_h have unsigned values. if the 16-bit data from the host exceeds the range defined by the dac_limit_l and dac_limit_h, the output digital code to the dac will be clamped. dac_limit_l dac output limit low byte dac_limit_h dac output limit high byte example to set the dac output limit value: ;----------------------------------------------------------- ; set dac limit value=ff00h ;----------------------------------------------------------- clr [02dh] ; set dac limit low byte=00h set [02eh] ; set dac limit high byte=ffh ;----------------------------------------------------------- in order to prevent speaker popping sounds, the power amplifier should be setup to output a value of vdd/2, imple - mented by sending 8000h to the dac, during the initial power on state. a falling edge on the dac_wr_trig bit (bit 3 of dac_wr register), will write the values in the dac_limit_l and dac_limit_h registers into the dac. bit no. label r/w power-on functions 0~2, 4~7 r0 undefined bit, read as 0 . 3 dac_wr_trig r/w 0 dac write trigger bit dac_wr (2fh) register example to avoid speaker popping noise: system_initial: ;----------------------------------------------------------- ; avoid pop noise ;----------------------------------------------------------- mov a,wdts mov fifo_temp,a ;save wdts value mov a,01010000b andm a,wdts mov a,01010000b orm a,wdts ;enter dac write data mode, high nibble of wdts=0101b clr [02dh] ;set dac data low byte=00h mov a,80h mov [02eh],a ;set dac data high byte=80h nop ;write 8000h to dac set [02fh].3 nop clr [02fh].3 nop ;----------------------------------------------------------- mov a,fifo_temp ;restore wdts value mov wdts,a ;quit dac write data mode ;----------------------------------------------------------- note: when in the dac write data mode(high nibble of wdts register is 0101b), the dac_limit_l and dac_limit_h registers will be used as the 16-bit dac input data registers during the falling edge of the dac_wr_trig. oth - erwise, these two registers are used to define the 16-bit dac output limits.
HT82A850R rev. 1.10 19 july 25, 2007 digital pga bit no. label functions 0~5 pga0~pga5 digital pga control bits with range 0~19.5 db. the pga is a digital amplifier used to amplify the 16-bit data that comes from the pcm adc. the pga value versus gain relationship is shown in the following table. 6 adc_reset adc_reset= 1 : pcm adc at reset condition adc_reset= 0 : pcm adc during normal operation - default=0 the following conditions will reset the adc: - mcu reset - set adc_reset to 1 using the program 7 mute_mkb microphone mute control: mute_mkb =0: mute microphone input. mute_mkb =1: normal. pga_ctrl register pga_crtl value (pga5~pga0) gain (db) 000000
0 000001
0.5 : : : : 100111
19.5 101000
19.5 : : : : 111111
19.5 pfd control label bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pfdc 0 pres1 pres0 pfden 0 0 pfd_io selw pfdd pfdd7 pfdd6 pfdd5 pfdd4 pfdd3 pfdd2 pfdd1 pfdd0 pfdc (31h), pfdd (32h) register a programmable frequency divider, pfd, is implemented within the HT82A850R. it is composed of two sections, a prescaler and a general counter. the prescaler is controlled by the register bits, pres0 and pres1. the 4-stage prescaler is divided by 16. the general counter is programmed by an 8-bit register known as pfdd. the pfdd is write inhibited while the pfd is disabled. to modify the pfdd contents, the pfd must be enabled. when the generator is disabled, the pfdd is cleared by hardware. pfd prescaler selection: pres1 pres0 prescaler output 00 pfd frequency source 1 01 pfd frequency source 2 10 pfd frequency source 4 11 pfd frequency source 8
HT82A850R rev. 1.10 20 july 25, 2007 the bit pfd_io is used to determine whether pc0 is a general purpose i/o pin or a pfd output. pfd_io= 1 pc0 is pfd output pfd_io= 0 pc0 is a general io pin port - default=0 the selw bit is used to control the power amplifier input source. the software should set selw = 1 when the power amplifier signal is sourced from music_in, otherwise the speaker output is the usb audio data. selw= 1 the power amplifier signal is sourced from the music_in pin selw= 0 the power amplifier signal is sourced from the usb audio data (default=0) spi the serial interface function is similar to the motorola spi, where four basic signals are included. these are the sdi (serial data input), sdo (serial data output), sck (serial clock) and scs (slave select pin). label functions d7 d6 d5 d4 d3 d2 d1 d0 sbcr serial bus control register cks m1 m0 sben mls csen wcol trf default 01100000 sbdr serial bus data register d7 d6 d5 d4 d3 d2 d1 d0 default uuuuuuuu note: u unchanged # , ( - - 1 % & : ( 0 < 8 8 g & ' ; % ' ) & 8 8 8 '
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HT82A850R rev. 1.10 21 july 25, 2007 two registers, sbcr and sbdr, are provided for serial interface control, status and data storage. sbcr: serial bus control register bit7 (cks): clock source selection: f sio =f sys /2, select as 0; f sio =f sys , select as 1 bit6 (m1), bit5 (m0): master/slave mode and baud rate selection m1, m0= 00: master mode, baud rate = f sio 01: master mode, baud rate = f sio /4 10: master mode, baud rate = f sio /16 11: slave mode bit4 (sben): serial bus enable/disable (1/0) enable: (scs dependent on csen bit) disable enable: sck, sdi, sdo, scs =0 (sck = 0 ) and wait to write data to sbdr (txrx buffer) master mode: write data to sbdr (txrx buffer) start transmission/reception automatically master mode: when data has been transferred set trf slave mode: when a sck (and scs dependent on csen) is received, data in the txrx buffer is shifted-out and data on sdi is shifted-in. disable: sck (sck ), sdi, sdo, scs floating and related pins are io ports. label functions sben=1 pc4~pc7 are spi function pins (pin scs will go low if csen=1). sben=0 pc4~pc7 are general purpose i/o port pins - default note: 1. if sben= 1 , the pull-high resistors on pc4~pc7 will be disabled. when this happens external pull-high resistors should be added to the spi related pins if necessary (ex: pin scs ). 2. if csen= 0 , the scs pin will enter a floating state. bit3 (mls): msb or lsb (1/0) shift first control bit bit2 (csen): serial bus selection signal enable/disable (scs ), when csen=0, scs is floating bit1 (wcol): this bit is set to 1 if data is written to sbdr (txrx buffer) when the data is transferring writing will be ignored if data is written to sbdr (txrx buffer) when the data is transferring wcol will be set by hardware and cleared by software. bit 0 (trf): data transferred or data received used to generate an interrupt note: data reception is still operational when the mcu enters the power-down mode sbdr: serial bus data register data written to sbdr write data to the txrx buffer only data read from sbdr read from sbdr only operating mode description: master transmitter: clock sending and data i/o started by writing to sbdr master clock sending started by writing to sbdr slave transmitter: data i/o started by clock reception slave receiver: data i/o started by clock reception
HT82A850R rev. 1.10 22 july 25, 2007 clock polarity = rising (clk ) or falling (clk): 1 or 0 (software option) serial interface operation: label functions master select cks and select m1,m0 = 00, 01, 10 select csen, mls (same as slave) set sben writing data to sbdr data is stored in the txrx buffer output clk (and scs ) signals go to step 5 (sio internal operation data stored in the txrx buffer, and the sdi data is shifted into the txrx buffer data transferred, data in the txrx buffer is latched into sbdr) check wcol; wcol = 1 clear wcol and go to step 4; wcol = 0 go to step 6 check trf or waiting for sbi (serial bus interrupt) read data from sbdr clear trf go to step 4 slavehans cks don t care and select m1, m0 = 11 select csen, mls (same as master) set sben writing data to sbdr data is store in the txrx buffer waiting for master clock signal (and scs ): clk go to step 5 (sio internal operations clk (scs ) received output data in txrx buffer and sdi data is shifted into the txrx buffer data transferred, data in the txrx buffer is latched into sbdr) check wcol; wcol = 1 clear wcol, go to step 4; wcol = 0 go to step 6 check trf or waiting for sbi (serial bus interrupt) read data from sbdr clear trf go to step 4 wcol: master/slave mode, set if writing to sbdr when data is transferring (transmitting or receiving) and this writing will be ignored. the wcol function can be enabled/disabled by a software option (sio_wcol bit of mode_ctrl register). wcol is set by sio and cleared by the user. data transmission and reception will continue to operated when the mcu enters the power-down mode. cpol is used to select the clock polarity of clk and is a software option (sio_cpol bit of mode_ctrl register). mls: msb or lsb first selection csen: chip select function enable/disable, csen = 1 scs signal function is active. the master should output a scs signal before the clk signal and slave data transferring should be disabled(enabled) before(after) scs signal received. csen = 0, scs signal is not needed, scs pin (master and slave) should be floating. csen: csen software option (sio_csen bit of mode_ctrl register) is used to enable/disable software csen function. if csen software option is disable, software csen always disabled. if csen software option is enabled, software csen function can be used. sben = 1 serial bus standby; scs (csen = 1) = 1; scs = floating (csen = 0); sdi = floating; sdo = 1; master clk = output 1/0 (dependent on cpol software option), slave clk = floating sben = 0 serial bus disable; scs = sdi = sdo = clk = floating trf is set by sio and cleared by the user. when the data is transferring (transmission and reception) is complete, trf is set to generate sbi (serial bus interrupt).
HT82A850R rev. 1.10 23 july 25, 2007 label functions d7 d6 d5 d4 d3 d2 d1 d0 sbcr serial bus control register cks m1 m0 sben mls csen wcol trf default 01100000 sbdr serial bus data register d7 d6 d5 d4 d3 d2 d1 d0 default uuuuuuuu + ( ) 0 ( ( . - ( 4 4 ( - . ( ( 0 ) ( + + ( ) 0 ( ( . - ( 4 4 ( - . ( ( 0 ) ( + ! ! / ' h ; % ' h % % 6 % %
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HT82A850R rev. 1.10 24 july 25, 2007 label functions wcol set by sio cleared by users cesn enable or disable device selection function pin master mode: 1/0=with/without scs output control slave mode: 1/0= with/without scs input control sben enable or disable serial bus (0= initialize all status flags) when sben=0, all status flags should be initialized when sben=0, all sio related function pins should stay in a floating state trf 1= data transmitted or received 0= data is transmitting or still not received if the clock polarity set to rising edge (sio_cpol=1), the serial clock timing will follow clk , otherwise (sio_cpol=0) clk is the serial clock timing. mode control the mode_ctrl register is used to control the dac and adc operational mode and the spi function. bit no. label functions 0 da_l_enb dac enable/disable control (left channel) 1= dac left channel disable 0= dac left channel enable (default) 1 da_r_enb dac enable/disable control (right channel) 1= dac right channel disable 0= dac right channel enable (default) 2 ad_enb adc enable/disable control 1= adc power down 0= adc power on (default) 3 play_mode dac play mode control 1= 8khz/16-bit 0= 48khz/16-bit (default) 4 sio_cpol there are three bits used to control the mode of spi operation. 1= clock polarity rising edge 0= clock polarity falling edge (default) 5 sio_wcol 1= wcol bit of sbcr register enable 0= wcol bit of sbcr register disable (default) 6 sio_csen 1= csen bit of sbcr register enable 0= csen bit of sbcr register disable (default) 7 undefined bit, read as 0 mode_ctrl (34h) register spi usage example spi_test: clr ucc.@ucc_sysclk ;12mhz sysclk set sio_csen ;spi chip select function enable clr sio_cpol ;falling edge change data ;master mode, sclk=fsio clr m1 clr m0 ;-------------- clr cks ;f sio =f sys /2 clr trf ;clear trf flag clr trf_int ;clear interrupt spi flag set mls ;msb shift first set csen ;chip select enable set sben ;spi enable, scs will go low
HT82A850R rev. 1.10 25 july 25, 2007 if polling_mode clr esii ;spi interrupt disable ;write into "write enable" instruction mov a,op_wren mov sbdr,a $0: snz trf jmp $0 clr trf else set esii ;spi interrupt enable ;write into "write enable" instruction mov a,op_wren mov sbdr,a $0: snz trf_int ;set at spi interrupt jmp $0 clr trf_int endif record data the record interrupt will be activated when the record data is valid in the record_data registers. the re - cord_data registers will latch data until next interrupt occurs. the record_data is 2 s complement value (8000h~7fffh). the update rate of the record_data is 8khz. all these registers (3eh~3fh) are read only. address label bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3eh record_data_l r_d7 r_d6 r_d5 r_d4 r_d3 r_d2 r_d1 r_d0 3fh record_data_h r_d15 r_d14 r_d13 r_d12 r_d11 r_d10 r_d9 r_d8 configuration options the following table shows the microcontroller configuration options . all of the otp options must be defined to ensure proper system functioning. no. option 1 pa0~pa7 pull-high resistor enabled or disabled - bit option 2 lvr enable or disable 3 wdt enable or disable 4 wdt clock source: f sys /4 or wdtosc 5 clrwdt instruction(s): 1 or 2 6 pa0~pa7 wake-up enabled or disabled - bit option 7 pb0~pb7 pull-high resistor enabled or disable - bit option 8 pc0~pc7 pull-high resistor enabled or disabled - nibble option 9 tbhp enable or disable - default disable
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HT82A850R rev. 1.10 27 july 25, 2007 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT82A850R rev. 1.10 28 july 25, 2007 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT82A850R rev. 1.10 29 july 25, 2007 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82A850R rev. 1.10 30 july 25, 2007
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT82A850R rev. 1.10 31 july 25, 2007
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82A850R rev. 1.10 32 july 25, 2007
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT82A850R rev. 1.10 33 july 25, 2007
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). if an in- terrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82A850R rev. 1.10 34 july 25, 2007
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT82A850R rev. 1.10 35 july 25, 2007
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82A850R rev. 1.10 36 july 25, 2007
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT82A850R rev. 1.10 37 july 25, 2007
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82A850R rev. 1.10 38 july 25, 2007
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT82A850R rev. 1.10 39 july 25, 2007
package information 48-pin lqfp (7 7) outline dimensions symbol dimensions in mm min. nom. max. a 8.9 9.1 b 6.9 7.1 c 8.9 9.1 d 6.9 7.1 e 0.5 f 0.2 g 1.35 1.45 h 1.6 i 0.1 j 0.45 0.75 k 0.1 0.2 0 7 HT82A850R rev. 1.10 40 july 25, 2007 4 0 . 4 + . - 4 . - > / ' 8 $ c j
HT82A850R rev. 1.10 41 july 25, 2007 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2007 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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