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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. december 2009 doc id 15819 rev 4 1/35 35 stp1612pw05 16-channel led driver with 16-bit pwm, 8-bit gain and full led error detection features 16 constant current output channels supply voltage: 3.3 v or 5 v two pwm selectable counters 12/16-bit of grayscale selectable enhanced pwm for ghost effect reduction open and short led detection 8-bit current gain control by means of 256 steps in two selectable ranges single resistor to set the current from 3 ma to 60 ma programmable progressive output delay thermal protection and thermal flag uvlo schmitt trigger input selectable 16-bit or 256-bit serial data-in format max clock frequency: 30 mhz esd protection 2.5 kv hbm, 200 v mm drop-in compatible with stp16cp\s\dp05 series available in high thermal efficiency tssop exposed pad applications video display led panels rgb backlighting special lighting description the stp1612pw05 is a 16-channel constant current sink led driver. the maximum output current value for all the 16 channels is set by a single resistor from 3 ma to 60 ma. the device features 8-bit gain (256 steps) for global led brightness adjustment with two selectable ranges. this function is accessible via a serial interface. the device has an individual adjustable pwm brightness control for each output channel. the pwm counters are selectable via a serial interface with 4096 or 65536 steps (12 or 16 bit). the stp1612pw05 also provides enhanced pulse-width modulation counting algorithms called e-pwm to reduce flickering effects (ghost visual effects) improving the overall image quality. the device has a dual size 16-bit or 256-bit shift register. all the control and the shift register read back data are accessible via serial interface. the stp1612pw05 has the cap ability to detect open and short led failure and overtemperature, reporting the status through spi line. the device guarantees a 20 v output driving capability, allowing the user to connect more leds in series. so-24 tssop24 tssop24 exposed pad qfn-24 table 1. device summary order code package packaging stp1612pw05qtr qfn-24 4000 parts per reel STP1612PW05MTR so-24 1000 parts per reel stp1612pw05ttr tssop24 2500 parts per reel stp1612pw05xttr tssop24 exposed pad 2500 parts per reel www.st.com
contents stp1612pw05 2/35 doc id 15819 rev 4 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 definition of conf iguration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 grey scales data loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 setting the pwm gray scale count er . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1 pwm data synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2 synchronization for pwm counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 setting output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 current gain adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13 delay time of staggered output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 14 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 15 time-out alert of gclk di sconnection . . . . . . . . . . . . . . . . . . . . . . . . . 24 stp1612pw05 contents doc id 15819 rev 4 3/35 16 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 block diagram stp1612pw05 4/35 doc id 15819 rev 4 1 block diagram figure 1. block diagram pwm a nd e-pwm 12/16 b it co u nter a nd s ync control s eri a l interf a ce uvlo & por vdd gnd s di clk le s do con s t a nt c u rrent o u tp u t ch a nnel s 1----------16 t s d 16- b it config u r a tion regi s ter s hift regi s ter d ua l s ize mode (16 or 256 b it) pwclk d ua l r a nge g a in 7- b it dac pwm d a t a bu ffer (16x16 b it) gr a d ua l o u tp u t s del a y ctrl comm a nd a nd ctrl logic open/ s hort error detection r-ext stp1612pw05 summary description doc id 15819 rev 4 5/35 2 summary description table 2. typical current accuracy at 5 v output voltage current accuracy output current v dd temp. between bits between ics 1.0 1.5% 6% 15 to 60 5 v 25 c 0,2 1.5% 6% 3 to 15 table 3. typical current accuracy at 3.3 v output voltage current accuracy output current v dd temp. between bits between ics 1.0 1.5% 6% 15 to 60 3.3 v 25 c 0,3 1.5% 6% 3 to 15 summary description stp1612pw05 6/35 doc id 15819 rev 4 2.1 pin connection and description figure 2. pin connection note: the exposed pad should be electrically conn ected to a metal land electrically isolated or connected to ground 14 1 3 15 16 17 1 8 5 6 4 3 2 1 8 7 9101112 2 3 24 22 21 20 19 clk s di vdd r-ext s do out7 out4 out6 out 3 out2 out1 out0 le out 8 out1 3 out12 out11 out10 out9 out5 out14 out15 pwclk gnd table 4. pin description pin n symbol name and function 1 gnd ground terminal 2 sdi serial data input terminal 3clk clock input terminal used to shift data on rising edge and carries command information when le is asserted. 4 le data strobe terminal and controlling command with clk 5-20 out 0-15 output terminals 21 pwclk gray scale clock terminal. reference clock for grey scale pwm counter. 22 sdo serial data out terminal 23 r-ext input terminal of an external resistor for constant current programing 24 v dd supply voltage terminal stp1612pw05 electrical ratings doc id 15819 rev 4 7/35 3 electrical ratings 3.1 absolute maximum ratings stressing the device above the rating listed in the ta bl e 5 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3.2 thermal data table 5. absolute maximum ratings symbol parameter value unit v dd supply voltage 0 to 7 v v o output voltage -0.5 to 20 v i o output current 60 ma v i input voltage -0.4 to v dd v i gnd gnd terminal current 1300 ma f clk clock frequency 50 mhz t j junction temperature range (1) 1. such absolute value is based on the thermal shutdown protection. -40 to + 170 c table 6. thermal data symbol parameter value unit t a operating free-air temperature range -40 to +125 c t j-opr operating thermal junction temperature range -40 to +150 c t stg storage temperature range -55 to +150 c r thja thermal resistance junction- ambient (1) 1. according to jedec standard 51-7b so-24 42.7 c/w tssop24 55 c/w tssop24 (2) exposed pad 2. the exposed pad should be soldered directly to the pcb to realize the thermal benefits. 37.5 c/w qfn-24 55 c/w electrical ratings stp1612pw05 8/35 doc id 15819 rev 4 3.3 recommended operating conditions table 7. recommended operating conditions at 25 c, v dd = 5 v symbol parameter test conditions min. typ. max. unit v dd supply voltage 3.0 - 5.5 v v o output voltage - 20 v i o output current outn 3 - 60 ma i oh output current serial-out - +1 ma i ol output current serial-out - -1 ma v ih input voltage 0.7 v dd -v dd v v il input voltage gnd - 0.3 v dd v t wlat le pulse width v dd = 3.3 v to 5.0 v 20 - ns t wclk clk pulse width 10 - ns t wen pwclk pulse width 20 - ns t setup(d) setup time for data 5 - ns t hold(d) hold time for data 5 - ns t setup(l) setup time for latch 5 - ns f clk clock frequency cascade operation (1) 1. if the device is connected in ca scade, it may not be possible achiev e the maximum data transfer. please considered the ti mings carefully. -30mhz stp1612pw05 electrical characteristics doc id 15819 rev 4 9/35 4 electrical characteristics t a = 25 c (unless otherwise specified) table 8. electrical characteristics (v dd = 5.0 v) symbol characteristics test conditions min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v o maximum output voltage out0 ~ out15 20 v i out output current v o = 1.2v 5 60 ma i oh sdo, t a = - 40 ~ 125 c -8 ma i ol sdo, t a = - 40 ~ 125 c 8 ma v ih input voltage ?h? level t a = - 40 ~ 125 c 0.7 * v dd v dd v v il input voltage ?l? level t a = - 40 ~ 125 c gnd 0.3 * v dd v i oh output leakage current v o = 20 v 10 a v ol output voltage sdo i ol = + 1.0 ma, t a = - 40 ~ 125 c 0.4 v v oh i oh = -1.0 ma t a = - 40 ~ 125 c v dd - 0.4 v di out1 current skew (channel) i out = 10 ma v o = 1.0 v, r ext = 69 k 1.5 3.0 % di out2 current skew (ic) i out = 10 ma v o = 1.0 v, r ext = 69 k 3.0 6.0 % %/d v o output current vs. output voltage regulation v o within 1.0 v and 3.0 v, r ext = 34.7 k @ 20 ma 0.1 0.5 % / v %/ dv dd output current vs. supply voltage regulation v dd within 4.5 v and 5.5 v 1.0 5.0 % / v v o,th 0.15 0.20 v r in(down) pull-down resistor le 150 200 250 k i dd(off) 1 supply current ? off ? r ext = open , out0 ~ out15 = off 71013 ma i dd(off) 2 i o = 20 ma, out0 ~ out15 = off 6.6 9.5 12 i dd(off) 3 i o = 60 ma, out0 ~ out15 = off 9 12.7 16.5 i dd(on) 1 supply current ? on ? i o = 20 ma, out0 ~ out15 = on 6.6 9.4 12.2 i dd(on) 2 i o = 60 ma, out0 ~ out15 = on 8 11.5 14.9 electrical characteristics stp1612pw05 10/35 doc id 15819 rev 4 table 9. electrical characteristics (v dd = 3.3 v) symbol characteristics test conditions min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v o sustaining voltage at out ports out0 ~ out15 20 v i out output current v o = 1.2 v 5 60 ma i oh sdo, t a = -40 ~ 125 c -1.0 ma i ol sdo t a = -40 ~ 125 c 1.0 ma v ih input voltage ?h? level t a = - 40 ~ 125 c 0.7 * v dd v dd v v il input voltage ? l ? level t a = - 40 ~ 125 c gnd 0.3 * v dd v i oh output leakage current v o = 17.0 v 0.5 a v ol output voltage sdo i ol = +1.0 ma, t a = -40 ~ 125 c 0.4 v v oh i oh = -1.0 ma t a = -40 ~ 125 c 2.9 v di out1 current skew (channel) i out = 10.5 ma, v o = 1.0 v, r ext = 69 k at 10 ma 1.5 3.0 % di out2 current skew (ic) i out = 10.8 ma, v o = 1.0 v, r ext = 69 k at 10 ma 3.0 6.0 % %/d v o output current vs. output voltage regulation v o within 1.0 v and 3.0 v, r ext = 34.7 k at 20 ma 0.1 0.5 % / v %/dv dd output current vs. supply voltage regulation v dd within 3.0 v and 3.6 v 1.0 5.0 % / v r in(down) pull-down resistor le 150 200 250 k i dd(off) 1 supply current ?off? r ext = open, out0 ~ out15 = off 7.2 9.3 ma i dd(off) 2 i o = 20 ma, out0 ~ out15 = off 8.6 11 i dd(off) 3 i o = 60 ma, out0 ~ out15 = off 11.7 15.2 i dd(on) 1 supply current ?on? i o = 20 ma, out0 ~ out15 = on 29 37.7 i dd(on) 2 i o = 60 ma, out0 ~ out15 = on 31.2 40 stp1612pw05 electrical characteristics doc id 15819 rev 4 11/35 figure 3. test circuit for electrical characteristics table 10. switching characteristics (v dd = 5.0 v) t a = -40 ~ 125 c symbol characteristics conditions min. typ. max. unit t su0 setup time sdi - clk v dd = 5.0 v v ih = v dd v il = gnd r ext = 460 v led = 4.5 v r l = 152 cl = 10 pf c1 = 100 nf c2 = 10 f i o = 20 ma 1 ns t su1 le ? dclk 1 ns t su2 le ? dclk 5 ns t h0 hold time clk - sdi 3 ns t h1 clk - le 7 ns t pd0 propagation delay time clk - sdo 30 40 ns t pd1 pwclk-outn4 (1) 1. refer to the timing waveform, where n = 0, 1, 2, 3. 100 ns t pd2 le ? sdo (2) 2. in timing of ?read configuration? and ?read error st atus code?, the next clk rising edge should be t pd2 after the falling edge of le. 30 40 ns t dl1 stagger delay time outn4 + 1 (1) 40 ns t dl2 outn4 + 2 (1) 80 ns t dl3 outn4 +3 (1) 120 ns t w(l) pulse width le 5 ns t w( clk) clk 20 ns t w(pwclk) pwclk 20 ns t on output rise time of output ports 10 ns t off output fall time of output ports 6 ns t edd error detection minimum duration (3) 3. refer to figure 5 on page 13 . 1s pwclk clk le dd v ext - r gnd sdo out0 . . . generator function dd i v ih =v dd v il =gnd waveform input logic sdi out15 out i v ih ,v il v dd r ext i ol i oh electrical characteristics stp1612pw05 12/35 doc id 15819 rev 4 figure 4. test circuit for switching characteristics table 11. switching characteristics (v dd = 3.3 v) symbol characterist ics conditions min. typ. max. unit t su0 setup time sdi - dclk v dd = 3.3 v v ih = v dd v il = gnd r ext = 460 v led = 4.5 v r l = 152 cl = 10 pf c1 = 100 nf c2 = 10 f 1 ns t su1 le ? dclk 1 ns t su2 le ? dclk 5 ns t h0 hold time clk - sdi 3 ns t h1 clk - le 7 ns t pd0 propagation delay time clk - sdo 45 40 ns t pd1 pwclk-outn4 (1) 1. refer to the timing waveform figure 4 , where n = 0, 1, 2, 3. 120 ns t pd2 le ? sdo (2) 2. in timing of ?read configurati on? and ?read error status code?, the next clk rising edge should be t pd2 after the falling edge of le. 45 40 ns t dl1 stagger delay time outn4 + 1 (1) 40 ns t dl2 outn4 + 2 (1) 80 ns t dl3 outn4 +3 (1) 120 ns t w(l) pulse width le 5 ns t w(clk) clk 20 ns t w(pwclk) pwclk 20 ns t on output rise time of output ports 11.6 ns t off output fall time of output ports 7 ns t dec error detection duration 0.5 1 s pwclk clk le dd v ext - r gnd sdo out0 . . . generator function dd i out i c l v led waveform input logic sdi out15 1 c 2 c v ih ,v il v ih =v dd v il =gnd r ext r l r l c l c l v dd stp1612pw05 timi ng waveform doc id 15819 rev 4 13/35 5 timing waveform figure 5. timing waveform pwclk pwclk pwclk principle of operation stp1612pw05 14/35 doc id 15819 rev 4 6 principle of operation table 12. control command signals combination description command name le number of clk rising edge when le is asserted the action after a falling edge of le data latch high 1 serial data are transferred to the buffers global latch high 2 or 3 buffer data are transferred to the comparators read configuration high 4 or 5 move out ?configuration register? to the shift register enable ?error detection? high 6 or 7 detect the status of each output?s led read ?error status code? high 8 or 9 move out ?error status code? of 16 outputs to the shift registers write configuration high 10 or 11 serial data are transferred to the ?configuration register? reset to 16-bit shift register length high 12 or 13 set to 16-bit the shift register length stp1612pw05 principle of operation doc id 15819 rev 4 15/35 figure 6. timing diagram $ a t a , a t c h ' l o b a l , a t c h 2 e a d # o n f i g u r a t i o n 7 r i t e # o n f i g u r a t i o n , % 3 $ / # , + 3 $ ) 0 r e v i o u s $ a t a . . . $ $ $ . e x t $ a t a $ $ $ $ $ $ $ $ $ $ $ $ $ - 3 " $ $ $ , % # , + 3 $ ) 3 $ / . . . 0 r e v i o u s $ a t a $ $ $ $ $ $ . e x t $ a t a $ $ $ $ $ $ $ $ $ $ $ $ $ - 3 " , % # , + 3 $ / 0 r e v i o u s $ a t a . . . . . . . . . & % $ # " ! , % 3 $ / # , + 3 $ ) 0 r e v i o u s $ a t a . . . . e x t $ a t a & |