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high common-mode voltage, difference amplifier ad629 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1999-2007 analog devices, inc. all rights reserved. features improved replacement for: ina117p and ina117ku 270 v common-mode voltage range input protection to 500 v common mode 500 v differential mode wide power supply range (2.5 v to 18 v) 10 v output swing on 12 v supply 1 ma maximum power supply current high accuracy dc performance 3 ppm maximum gain nonlinearity (ad629b) 20 v/c maximum offset drift (ad629a) 10 v/c maximum offset drift (ad629b) 10 ppm/c maximum gain drift excellent ac specifications 77 db minimum cmrr @ 500 hz (ad629a) 86 db minimum cmrr @ 500 hz (ad629b) 500 khz bandwidth applications high voltage current sensing battery cell voltage monitors power supply current monitors motor controls isolation functional block diagram 1 2 3 4 8 7 6 5 21.1k ? 380k ? 380k ? 380k ? 20k ? ref(?) ?in +in ?v s nc +v s output ref(+) ad629 nc = no connect 0 0783-001 figure 1. general description the ad629 is a difference amplifier with a very high input, common-mode voltage range. it is a precision device that allows the user to accurately measure differential signals in the presence of high common-mode voltages up to 270 v. the ad629 can replace costly isolation amplifiers in applications that do not require galvanic isolation. the device operates over a 270 v common-mode voltage range and has inputs that are protected from common-mode or differential mode transients up to 500 v. the ad629 has low offset, low offset drift, low gain error drift, low common-mode rejection drift, and excellent cmrr over a wide frequency range. the ad629 is available in low cost, 8-lead pdip and 8-lead soic packages. for all packages and grades, performance is guaranteed over the industrial temperature range of ?40c to +85c. frequency (hz) common-mode rejection r a tio (db) 100 50 55 60 65 70 75 80 85 90 95 20 100 1k 10k 20k 00783-002 figure 2. common-mode rejection ratio vs. frequency common-mode voltage (v) output error (2mv/div) ?240 240 120 ?120 0 00783-003 2mv/div 60v/div figure 3. error voltage vs. input common-mode voltage
ad629 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 typical performance characteristics ............................................. 5 theory of operation ........................................................................ 9 applications ..................................................................................... 10 basic connections ...................................................................... 10 single-supply operation ........................................................... 10 system-level decoupling and grounding .............................. 10 using a large sense resistor ..................................................... 11 output filtering .......................................................................... 11 output current and buffering .................................................. 12 a gain of 19 differential amplifier ......................................... 12 error budget analysis example 1 ............................................ 12 error budget analysis example 2 ............................................ 13 outline dimensions ....................................................................... 14 ordering guide ............................................................................... 15 revision history 3/07rev. a to rev. b updated format and layout .............................................universal changes to ordering guide .......................................................... 15 3/00rev. 0 to rev. a 10/99revision 0: initial version
ad629 rev. b | page 3 of 16 specifications t a = 25c, v s = 15 v, unless otherwise noted. table 1. ad629a ad629b parameter condition min typ max min typ max unit gain v out = 10 v, r l = 2 k nominal gain 1 1 v/v gain error 0.01 0.05 0.01 0.03 % gain nonlinearity 4 10 4 10 ppm r l = 10 k 1 1 3 ppm gain vs. temperature t a = t min to t max 3 10 3 10 ppm/c offset voltage offset voltage 0.2 1 0.1 0.5 mv v s = 5 v 1 mv vs. temperature t a = t min to t max 6 20 3 10 v/c vs. supply (psrr) v s = 5 v to 15 v 84 100 90 110 db input common-mode rejection ratio v cm = 250 v dc 77 88 86 96 db t a = t min to t max 73 82 db v cm = 500 v p-p, dc to 500 hz 77 86 db v cm = 500 v p-p, dc to 1 khz 88 90 db operating voltage range common mode 270 270 v differential 13 13 v input operating impedance common mode 200 200 k differential 800 800 k output operating voltage range r l = 10 k 13 13 v r l = 2 k 12.5 12.5 v v s = 12 v, r l = 2 k 10 10 v output short-circuit current 25 25 ma capacitive load stable operation 1000 1000 pf dynamic response small signal C3 db bandwidth 500 500 khz slew rate 1.7 2.1 1.7 2.1 v/s full power bandwidth v out = 20 v p-p 28 28 khz settling time 0.01%, v out = 10 v step 15 15 s 0.1%, v out = 10 v step 12 12 s 0.01%, v cm = 10 v step, v diff = 0 v 5 5 s output noise voltage 0.01 hz to 10 hz 15 15 v p-p spectral density, 100 hz 1 550 550 nv/hz power supply operating voltage range 2.5 18 2.5 18 v quiescent current v out = 0 v 0.9 1 0.9 1 ma t min to t max 1.2 1.2 ma temperature range for specified performance t a = t min to t max ?40 +85 ?40 +85 c 1 see figure 19.
ad629 rev. b | page 4 of 16 absolute maximum ratings table 2. parameter rating supply voltage, v s 18 v internal power dissipation 1 8-lead pdip (n) see figure 4 8-lead soic (r) see figure 4 input voltage range, continuous 300 v common-mode and differential, 10 sec 500 v output short-circuit duration indefinite pin 1 and pin 5 Cv s ? 0.3 v to +v s + 0.3 v maximum junction temperature 150c operating temperature range ?55c to +125c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c 1 specification is for device in free air: 8-lead pdip, ja = 100c/w; 8-lead soic, ja = 155c/w. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ambient temperature (c) maximum power dissip a tion (w) 2.0 1.5 1.0 0.5 0 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 00783-004 8-lead soic t j = 150c 8-lead pdip figure 4. maximum power dissipation vs. temperature for soic and pdip esd caution
ad629 rev. b | page 5 of 16 typical performance characteristics t a = 25c, v s = 15 v, unless otherwise noted. frequency (hz) common-mode rejection r a tio (db) 100 90 80 70 60 50 40 30 20 10 0 100 1k 10k 100k 1m 10m 00783-006 figure 5. common-mode rejection ratio vs. frequency v out (v) output error (2mv/div) ?20 ?16 ?8 ?4 0 4 8 12 16 ?12 20 00783-007 r l = 10k ? v s = 18v v s = 15v v s = 12v v s = 10v 2mv/div 4v/div figure 6. typical gain error normalized @ v out = 0 v and output voltage operating range vs. supply voltage, r l = 10 k (curves offset for clarity) v out (v) output error (2mv/div) ?20 ?16 ?8 ?4 0 4 8 12 16 ?12 20 00783-008 r l = 1k ? v s = 18v v s = 15v v s = 12v v s = 10v 4v/div figure 7. typical gain error normalized @ v out = 0 v and output voltage operating range vs. supply voltage, r l = 1 k (curves offset for clarity) power supply voltage (v) common-mode voltage (v) 400 360 320 280 240 200 160 120 80 40 0 02 6 10 4 8 12 14 1816 20 00783-009 t a = +25c t a = +85c t a = ?40c figure 8. common-mode operating range vs. power supply voltage v out (v) output error (2mv/div) ?20 ?16 ?8 ?4 0 4 8 12 16 ?12 20 00783-010 r l = 2k ? v s = 18v v s = 15v v s = 12v v s = 10v 4v/div figure 9. typical gain error normalized @ v out = 0 v and output voltage operating range vs. supply voltage, r l = 2 k (curves offset for clarity) v out (v) output error (2mv/div) ?20 ?16 ?8 ?4 0 4 8 12 16 ?12 20 00783-011 v s = 5v, r l = 2k ? v s = 5v, r l = 1k ? v s = 2.5v, r l = 1k ? 1v/div v s = 5v, r l = 10k ? figure 10. typical gain error normalized @ v out = 0 v and output voltage operating range vs. supply voltage (curves offset for clarity)
ad629 rev. b | page 6 of 16 v out (v) error (0.8ppm/div) ?10 ?5 0 5 10 00783-012 20v/div 2.5v/div v s = 15v r l = 10k ? figure 11. gain nonlinearity; v s = 15 v, r l = 10 k v out (v) error (1ppm/div) ?10 ?2?4?6 ?8 0246810 00783-013 20v/div 2v/div v s = 12v r l = 10k ? figure 12. gain nonlinearity; v s = 12 v, r l =10 k v out (v) error (6.67ppm/div) ?3.0 ?0.6?1.2 ?1.8 ?2.4 0 0.6 1.2 1.8 2.4 3.0 00783-014 40v/div 0.6v/div v s = 5v r l = 1k ? figure 13. gain nonlinearity; v s = 5 v, r l = 1 k v out (v) error (2ppm/div) ?10 ?2?4?6 ?8 0246810 00783-015 40v/div 2v/div v s = 15v r l = 2k ? figure 14. gain nonlinearity; v s = 15 v, r l = 2k output current (ma) output voltage (v) 14.0 13.0 12.0 11.0 10.0 9.0 ?11.5 ?12.0 ?12.5 ?13.0 ?13.5 02468101214161820 00783-016 ?40c ?40c ?40c +85c +85c +25c +25c v s = 15v figure 15. output voltage operat ing range vs. output current; v s = 15 v output current (ma) output voltage (v) 11.5 10.5 9.5 8.5 7.5 6.5 ?9.0 ?9.5 ?10.0 ?10.5 ?11.0 02468101214161820 00783-017 v s = 12v ?40c ?40c +85c +25c ?40c +85c +85c +25c figure 16. output voltage operat ing range vs. output current; v s = 12 v
ad629 rev. b | page 7 of 16 output current (ma) output voltage (v) 4.5 3.5 2.5 1.5 0.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 02468101214161820 00783-018 v s = 5v ?40c +85c +85c ?40c +25c +25c ?40c +25c +85c +85c figure 17. output voltage operat ing range vs. output current; v s = 5 v frequency (hz) power supply rejection r a tio (db) 120 110 100 90 80 70 60 50 40 30 0.1 10 1.0 100 1k 10k 00783-019 ?v s +v s figure 18. power supply reje ction ratio vs. frequency frequency (hz) vol t age noise spectral densi t y (v/ hz) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.01 1.0 0.1 100 10 1k 100k 10k 00783-020 figure 19. voltage noise spectral density vs. frequency 00783-021 25mv/div 4s/div g = +1 r l = 2k ? c l = 1000pf figure 20. small signal pulse response 00783-022 25mv/div 4s/div g = +1 r l = 2k ? c l = 1000pf figure 21. small signal pulse response 00783-023 5v/div 5s/div g = +1 r l = 2k ? c l = 1000pf figure 22. large signal pulse response
ad629 rev. b | page 8 of 16 00783-024 v out 5v/div 1mv/div output error 0v +10v 10s/div 1mv = 0.01% figure 23. settling time to 0.01%, for 0 v to 10 v output step; g = ?1, r l = 2 k common-mode rejection ratio (ppm) number of units 350 300 250 200 150 100 50 0 ?150 ?50 ?100 50 01 100 00783-025 5 0 n = 2180 n 200 pcs. from 10 assembly lots figure 24. typical distribution of common-mode rejection; package option n-8 ?1 gain error (ppm) number of units 400 300 250 350 200 150 100 50 0 ?600 ?200 ?400 200 06 400 00783-026 0 0 n = 2180 n 200 pcs. from 10 assembly lots figure 25. typical distribution of ?1 gain error; package option n-8 00783-027 v out 5v/div 1mv/div output error 0v ?10v 10s/div 1mv = 0.01% figure 26. settling time to 0.01% for 0 v to ?10 v output step; g = ?1, r l = 2k offset voltage (v) number of units 300 250 200 150 100 50 0 ?900 ?300 ?600 300 09 600 00783-028 0 0 n = 2180 n 200 pcs. from 10 assembly lots figure 27. typical distribution of offset voltage; package option n-8 +1 gain error (ppm) number of units 400 300 250 350 200 150 100 50 0 ?600 ?200 ?400 200 0 600 400 00783-029 n = 2180 n 200 pcs. from 10 assembly lots figure 28. typical distribution of +1 gain error; package option n-8
ad629 rev. b | page 9 of 16 theory of operation the ad629 is a unity gain, differential-to-single-ended amplifier (diff amp) that can reject extremely high common- mode signals (in excess of 270 v with 15 v supplies). it consists of an operational amplifier (op amp) and a resistor network. to achieve high common-mode voltage range, an internal resistor divider (pin 3 or pin 5) attenuates the noninverting signal by a factor of 20. other internal resistors (pin 1, pin 2, and the feedback resistor) restore the gain to provide a differential gain of unity. the complete transfer function equals v out = v ( +in ) ? v ( ?in ) laser wafer trimming provides resistor matching so that common-mode signals are rejected while differential input signals are amplified. to reduce output drift, the op amp uses super beta transistors in its input stage. the input offset current and its associated temperature coefficient contribute no appreciable output voltage offset or drift, which has the added benefit of reducing voltage noise because the corner where 1/f noise becomes dominant is below 5 hz. to reduce the dependence of gain accuracy on the op amp, the open-loop voltage gain of the op amp exceeds 20 million, and the psrr exceeds 140 db. 1 2 3 4 8 7 6 5 21.1k ? 380k ? 380k ? 380k ? 20k ? ref(?) ?in +in ?v s nc +v s output ref(+) ad629 nc = no connect 0 0783-001 figure 29. functional block diagram
ad629 rev. b | page 10 of 16 applications basic connections figure 30 shows the basic connections for operating the ad629 with a dual supply. a supply voltage of between 3 v and 18 v is applied between pin 7 and pin 4. both supplies should be decoupled close to the pins using 0.1 f capacitors. electrolytic capacitors of 10 f, also located close to the supply pins, may be required if low frequency noise is present on the power supply. while multiple amplifiers can be decoupled by a single set of 10 f capacitors, each in amp should have its own set of 0.1 f capacitors so that the decoupling point can be located right at the ics power pins. ref (?) ref (+) ?v s ?v s + v s +v s v out = i shunt r shunt nc ?in +in r shunt i shunt (see text) (see text) 0.1f 0.1f +3v to +18v ?3v to ?18v nc = no connect 21.1k ? 380k ? 380k ? 20k? 380k ? ad629 1 2 3 4 8 7 6 5 00783-030 figure 30. basic connections the differential input signal, which typically results from a load current flowing through a small shunt resistor, is applied to pin 2 and pin 3 with the polarity shown to obtain a positive gain. the common-mode range on the differential input signal can range from ?270 v to +270 v, and the maximum differential range is 13 v. when configured as shown in figure 30 , the device operates as a simple gain-of-1, differential-to-single- ended amplifier; the output voltage being the shunt resistance times the shunt current. the output is measured with respect to pin 1 and pin 5. pin 1 and pin 5 (ref(C) and ref(+)) should be grounded for a gain of unity and should be connected to the same low impedance ground plane. failure to do this results in degraded common- mode rejection. pin 8 is a no connect pin and should be left open. single-supply operation figure 31 shows the connections for operating the ad629 with a single supply. because the output can swing to within only about 2 v of either rail, it is necessary to apply an offset to the output. this can be conveniently done by connecting ref(+) and ref(C) to a low impedance reference voltage (some adcs provide this voltage as an output), which is capable of sinking current. therefore, for a single supply of 10 v, v ref may be set to 5 v for a bipolar input signal. this allows the output to swing 3 v around the central 5 v reference voltage. alternatively, for unipolar input signals, v ref can be set to about 2 v, allowing the output to swing from 2 v (for a 0 v input) to within 2 v of the positive rail. ref (?) ref (+) ?v s v y v x +v s +v s nc ?in +in r shunt i shunt 0.1f nc = no connect 21.1k ? 380k ? 380k? 20k? 380k ? ad629 1 2 3 4 8 7 6 5 00783-031 output = v out ? v ref v ref figure 31. operation with a single supply applying a reference voltage to ref(+) and ref(C) and operating on a single supply reduces the input common-mode range of the ad629. the new input common-mode range depends upon the voltage at the inverting and noninverting inputs of the internal operational amplifier, labeled v x and v y in figure 31 . these nodes can swing to within 1 v of either rail. therefore, for a (single) supply voltage of 10 v, v x and v y can range between 1 v and 9 v. if v ref is set to 5 v, the permissible common-mode range is +85 v to C75 v. the common-mode voltage ranges can be calculated by v cm () = 20 v x /v y () ? 19 v ref system-level decoupling and grounding the use of ground planes is recommended to minimize the impedance of ground returns (and therefore the size of dc errors). figure 32 shows how to work with grounding in a mixed-signal environment, that is, with digital and analog signals present. to isolate low level analog signals from a noisy digital environment, many data acquisition components have separate analog and digital ground returns. all ground pins from mixed-signal components, such as adcs, should return through a low impedance analog ground plane. digital ground lines of mixed-signal converters should also be connected to the analog ground plane. typically, analog and digital grounds should be separated; however, it is also a requirement to minimize the voltage difference between digital and analog grounds on a converter, to keep them as small as possible (typically <0.3 v). the increased noise, caused by the converters digital return currents flowing through the analog ground plane, is typically negligible. maximum isolation between analog and digital is achieved by connecting the ground planes back at the supplies. note that figure 32 suggests a star ground system for the analog circuitry, with all ground lines being connected, in this case, to the adcs analog ground. however, when ground planes are used, it is sufficient to connect ground pins to the nearest point on the low impedance ground plane.
ad629 rev. b | page 11 of 16 analog power supply digital power supply 0.1f 0.1f 0.1f 0.1f +in ?in ?v s v in1 v in2 v dd v dd output agnd gnd microprocessor dgnd +v s ad629 ad7892-2 ref(?) ref(+) 6 7 14 4 1 3 3 2 6 4 1 5 12 +5v gnd +5v gnd ?5v 00783-032 figure 32. optimal grounding practice for a bipolar supply environment with separate analog and digital supplies power supply v in1 v in2 v dd agnd dgnd adc 0.1f 0.1f +in ?in +v s output ?v s ad629 ref(?) ref(+) 4 7 3 2 6 1 5 v dd gnd microprocessor +5v gnd 0.1f 00783-033 figure 33. optimal grou nd practice in a single-supply environment if there is only a single power supply available, it must be shared by both digital and analog circuitry. figure 33 shows how to minimize interference between the digital and analog circuitry. in this example, the adcs reference is used to drive pin ref(+) and pin ref(C). this means that the reference must be capable of sourcing and sinking a current equal to v cm /200 k. as in the previous case, separate analog and digital ground planes should be used (reasonably thick traces can be used as an alternative to a digital ground plane). these ground planes should connect at the power supplys ground pin. separate traces (or power planes) should run from the power supply to the supply pins of the digital and analog circuits. ideally, each device should have its own power supply trace, but these can be shared by a number of devices, as long as a single trace is not used to route current to both digital and analog circuitry. using a large sense resistor insertion of a large value shunt resistance across the input pins, pin 2 and pin 3, will imbalance the input resistor network, introducing a common-mode error. the magnitude of the error will depend on the common-mode voltage and the magnitude of r shunt . table 3 shows some sample error voltages generated by a common-mode voltage of 200 v dc with shunt resistors from 20 to 2000 . assuming that the shunt resistor is selected to use the full 10 v output swing of the ad629, the error voltage becomes quite significant as r shunt increases. table 3. error resulting from large values of r shunt (uncompensated circuit) r s () error v out (v) error indicated (ma) 20 0.01 0.5 1000 0.498 0.498 2000 1 0.5 to measure low current or current near zero in a high common- mode environment, an external resistor equal to the shunt resistor value can be added to the low impedance side of the shunt resistor, as shown in figure 34 . ref (?) ref (+) ?v s ?v s +v s +v s v out nc ?in +in r shunt r comp i shunt 0.1f 0.1f nc = no connect 21.1k ? 380k ? 380k ? 20k? 380k ? ad629 1 2 3 4 8 7 6 5 00783-034 figure 34. compensating for large sense resistors output filtering a simple 2-pole, low-pass butterworth filter can be implemented using the op177 after the ad629 to limit noise at the output, as shown in figure 35 . table 4 gives recommended component values for various corner frequencies, along with the peak-to- peak output noise for each case. ref (?) ref (+) ? v s ?v s +v s +v s +v s v out nc ?in +in 0.1f 0.1f 0.1f 0.1f nc = no connect 21.1k ? 380k ? 380k ? 20k? 380k ? ad629 1 2 3 4 8 7 6 5 00783-035 r1 r2 c1 c2 op177 figure 35. filtering of output noise using a 2-pole butterworth filter table 4. recommended values for 2-pole butterworth filter corner frequency r1 r2 c1 c2 output noise (p-p) no filter 3.2 mv 50 khz 2.94 k 1% 1.58 k 1% 2.2 nf 10% 1 nf 10% 1 mv 5 khz 2.94 k 1% 1.58 k 1% 22 nf 10% 10 nf 10% 0.32 mv 500 hz 2.94 k 1% 1.58 k 1% 220 nf 10% 0.1 f 10% 100 v 50 hz 2.7 k 10% 1.5 k 10% 2.2 f 20% 1 f 20% 32 v
ad629 rev. b | page 12 of 16 output current and buffering the ad629 is designed to drive loads of 2 k to within 2 v of the rails but can deliver higher output currents at lower output voltages (see figure 15 ). if higher output current is required, the output of the ad629 should be buffered with a precision op amp, such as the op113, as shown in figure 36 . this op amp can swing to within 1 v of either rail while driving a load as small as 600 . ref (?) ref (+) ? v s ?v s +v s v ou t nc ?in +in 0.1f 0.1f 0.1f 0.1f nc = no connect 21.1k ? 380k ? 380k ? 20k ? 380k ? ad629 1 2 3 4 8 7 6 5 00783-036 op113 figure 36. output buffering application a gain of 19 differential amplifier while low level signals can be connected directly to the Cin and +in inputs of the ad629, differential input signals can also be connected, as shown in figure 37 , to give a precise gain of 19. however, large common-mode voltages are no longer permissible. cold junction compensation can be implemented using a temperature sensor, such as the ad590 . ref (?) ref (+) +v s +v s nc ?in +in 0.1f nc = no connect 21.1k ? 380k ? 380k ? 20k ? 380k ? ad629 1 2 3 4 8 7 6 5 00783-037 v ou t v ref thermocouple figure 37. a gain of 19 thermocouple amplifier error budget analysis example 1 in the dc application that follows, the 10 a output current from a device with a high common-mode voltage (such as a power supply or current-mode amplifier) is sensed across a 1 shunt resistor (see figure 38 ). the common-mode voltage is 200 v, and the resistor terminals are connected through a long pair of lead wires located in a high noise environment, for example, 50 hz/60 hz, 440 v ac power lines. the calculations in table 5 assume an induced noise level of 1 v at 60 hz on the leads, in addition to a full-scale dc differential voltage of 10 v. the error budget table quantifies the contribution of each error source. note that the dominant error source in this example is due to the dc common-mode voltage. ref (?) output current 60hz power line 1 ? shunt ref (+) ?v s +v s v out nc ?in +in 0.1f 0.1f nc = no connect 21.1k ? 380k ? 380k ? 20k? 380k ? ad629 1 2 3 4 8 7 6 5 00783-038 10 amps 200v cm dc to ground figure 38. error budget analysis example 1: v in = 10 v full-scale, v cm = 200 v dc, r shunt = 1 , 1 v p-p, 60 hz power-line interference table 5. ad629 vs. ina117 erro r budget analysis example 1 (v cm = 200 v dc) error, ppm of fs error source ad629 ina117 ad629 ina117 accuracy, t a = 25c initial gain error (0.0005 10)/10 v 10 6 (0.0005 10)/10 v 10 6 500 500 offset voltage (0.001 v/10 v) 10 6 (0.002 v/10 v) 10 6 100 200 dc cmr (over temperature) (224 10 -6 200 v)/10 v 10 6 (500 10 -6 200 v)/10 v 10 6 4480 10,000 total accurac y error 5080 10,700 temperature drift (85c) gain 10 ppm/c 60c 10 ppm/c 60c 600 600 offset voltage (20 v/c 60c) 10 6 /10 v (40 v/c 60c) 10 6 /10 v 120 240 total drift error 720 840 resolution noise, typical, 0.01 hz to 10 hz, v p-p 15 v/10 v 10 6 25 v/10 v 10 6 2 3 cmr, 60 hz (141 10 -6 1 v)/10 v 10 6 (500 10 -6 1 v)/10 v 10 6 14 50 nonlinearity (10 -5 10 v)/10 v 10 6 (10 -5 10 v)/10 v 10 6 10 10 total resolution error 26 63 total error 5826 11,603
ad629 rev. b | page 13 of 16 error budget analysis example 2 this application is similar to the previous example except that the sensed load current is from an amplifier with an ac common-mode component of 100 v (frequency = 500 hz) present on the shunt (see figure 39 ). all other conditions are the same as before. note that the same kind of power-line interference can happen as detailed in example 1. however, the ac common-mode component of 200 v p-p coming from the shunt is much larger than the interference of 1 v p-p; therefore, this interference component can be neglected. ref (?) output current 60hz power line 1 ? shunt ref (+) ?v s +v s v out nc ?in +in 0.1f 0.1f nc = no connect 21.1k ? 380k ? 380k ? 20k? 380k ? ad629 1 2 3 4 8 7 6 5 00783-039 10 amps 100v ac cm to ground figure 39. error budget analysis example 2: v in = 10 v full-scale, v cm = 100 v at 500 hz, r shunt =1 table 6. ad629 vs. ina117 ac error budget example 2 (v cm = 100 v 500 hz) error, ppm of fs error source ad629 ina117 ad629 ina117 accuracy, t a = 25c initial gain error (0.0005 10)/10 v 10 6 (0.0005 10)/10 v 10 6 500 500 offset voltage (0.001 v/10 v) 10 6 (0.002 v/10 v) 10 6 100 200 total accurac y error 600 700 temperature drift (85c) gain 10 ppm/c 60c 10 ppm/c 60c 600 600 offset voltage (20 v/c 60c) 10 6 /10 v (40 v/c 60c) 10 6 /10 v 120 240 total drift error 720 840 resolution noise, typical, 0.01 hz to 10 hz, v p-p 15 v/10 v 10 6 25 v/10 v 10 6 2 3 cmr, 60 hz (141 10 -6 1 v)/10 v 10 6 (500 10 -6 1 v)/10 v 10 6 14 50 nonlinearity (10 -5 10 v)/10 v 10 6 (10 -5 10 v)/10 v 10 6 10 10 ac cmr @ 500 hz (141 10 -6 200 v)/10 v 10 6 (500 10 -6 200 v)/10 v 10 6 2820 10,000 total resolution error 2846 10,063 total error 4166 11,603
ad629 rev. b | page 14 of 16 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 40. 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) ? 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 41. 8-lead standard small outline package [soic_n] (r-8) dimensions shown in millimeters and (inches)
ad629 rev. b | page 15 of 16 ordering guide model temperature range package description package option ad629an C40c to +85c 8-lead pdip n-8 ad629anz 1 C40c to +85c 8-lead pdip n-8 ad629ar C40c to +85c 8-lead soic_n r-8 ad629ar-reel C40c to +85c 8-lead soic_n r-8 ad629ar-reel7 C40c to +85c 8-lead soic_n r-8 ad629arz 1 C40c to +85c 8-lead soic_n r-8 ad629arz-rl 1 C40c to +85c 8-lead soic_n, 13-inch tape and reel, 2,500 pieces r-8 ad629arz-r7 1 C40c to +85c 8-lead soic_n, 7-inch tape and reel, 1,000 pieces r-8 ad629bn C40c to +85c 8-lead pdip n-8 ad629bnz 1 C40c to +85c 8-lead pdip n-8 ad629br C40c to +85c 8-lead soic_n r-8 ad629br-reel C40c to +85c 8-lead soic_n, 13-inch tape and reel, 2,500 pieces r-8 ad629br-reel7 C40c to +85c 8-lead soic_n, 7-inch tape and reel, 1,000 pieces r-8 ad629brz 1 C40c to +85c 8-lead soic_n r-8 ad629brz-rl 1 C40c to +85c 8-lead soic_n, 13-inch tape and reel, 2,500 pieces r-8 ad629brz-r7 1 C40c to +85c 8-lead soic_n, 7-inch tape and reel, 1,000 pieces r-8 AD629-EVAL evaluation board 1 z = rohs compliant part.
ad629 rev. b | page 16 of 16 notes ?1999-2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00783-0-2/07(b)

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