rev 0.6 / mar. 2005 1 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash document title 1gbit (128mx8bit / 64mx16 bit) nand flash memory revision history revision no. history draft date remark 0.0 1) initial draft. aug. 2004 preliminary 0.1 1) correct fig.10 sequential out cycle after read 2) add the text to fig.1, table.1, table.2 - text : io15 - io8 (x16 only) 3) delete ?3.2 page program note 1. - note : if possible it is better to remove this constrain 4) change the text ( page 10,13, 45) - 2.2 address input : 28 addresses -> 27 addresses - 3.7 reset : fig.29 -> fig.30 - 5.1 automatic page read after power up : fig.30 -> fig.29 5) add 5.3 addressing for program operation & fig.34 sep. 2004 preliminary 0.2 1) change tsop, wsop, fbga package dimension & figures. - change tsop, wsop, fbga package mechanical data - change fbga thickness (1.2 -> 1.0 mm) 2) correct tsop, wsop pin configurations. - 38th nc pin has been changed lockpre (figure 3,4) 3) edit figure 15,19 & table 4 4) add bad block management 5) change device identifier 3rd byte - 3rd byte id is changed. (reserved -> don't care) - 3rd byte id table is deleted. oct. 2004 preliminary 0.3 1) add errata 2) lockpre is changed to pre. - texts, table, figures are changed. 3) add note.4 (table.14) 4) block lock mechanism is deleted. - texts, table, figures are deleted. 5) add application note(power-on/off sequence & auto sleep mode.) - texts & figures are added. 6) edit the figures. (#10~25) nov.29 2004 preliminary 0.4 1) change ac characteristics(treh) before: 20ns -> after: 30ns 2) edit note.1 (page. 21) 3) edit the application note 1,2 4) edit the address cycle map (x8, x16) jan.19 2005 preliminary tcls tclh twp tals talh tds twc tr specification 0 10 25 0 10 20 50 25 relaxed value 5 15 40 5 15 25 60 27 ( datasheet : )
rev 0.6 / mar. 2005 2 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash revision history - continued - revision no. history draft date remark 0.5 1) correct ac characteristics(treh) before: 30ns-> after: 20ns 2) add errata jan. 25. 2005 preliminary 0.6 1) change ac characteristics 2) add tadl parameter - tadl=100ns 3) correct table.9 mar. 09. 2005 preliminary case trc trp treh trea specification read(all) 50 20 20 30 relaxed value except for id read 50 20 20 30 id read 60 25 30 30 tdh before 10 after 15
rev 0.6 / mar. 2005 3 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27ufxx1g2m - 1.8v device: vcc = 1.7 to 1.95v : hy27sfxx1g2m memory cell array = (2k+ 64) bytes x 64 pages x 1,024 blocks = (1k+32) words x 64 pages x 1,024 blocks page size - x8 device : (2k + 64 spare) bytes : hy27(u/s)f081g2m - x16 device: (1k + 32 spare) words : hy27(u/s)f161g2m block size - x8 device: (128k + 4k spare) bytes - x16 device: (64k + 2k spare) words page read / program - random access: 25us (max.) - sequential access: 50ns (min.) - page program time: 300us (typ.) copy back program mode - fast page copy without external buffering cache program mode - internal cache register to improve the program throughput fast block erase - block erase time: 2ms (typ.) status register electronic signature - manufacturer code - device code chip enable don't care option - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27(u/s)f(08/16)1g2m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27(u/s)f(08/16)1g2m-t (lead) - hy27(u/s)f(08/16)1g2m-tp (lead free) - hy27(u/s)f(08/16)1g2m-v(p) : 48-pin wsop1 (12 x 17 x 0.7 mm) - hy27(u/s)f(08/16)1g2m-v (lead) - hy27(u/s)f(08/16)1g2m-vp (lead free) - hy27(u/s)f(08/16)1g2m-f(p) : 63-ball fbga (9.5 x 12 x 1.0 mm) - hy27(u/s)f(08/16)1g2m-f (lead) - hy27(u/s)f(08/16)1g2m-fp (lead free)
rev 0.6 / mar. 2005 4 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 1. summary description the hynix hy27(u/s)f(08/16)1g2m series is a 128mx8bit with spare 4mx8 bit capacity. the device is offered in 1.8v vcc power supply and in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 1024 blocks, composed by 64 pages cons isting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in typical 2ms on a 128k-byte(x8 device) block. data in the page mode can be read out at 50ns cycle time per word. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously in troduced using ce#, we#, ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp# input pin or using the extended lock block feature described later. the output pin rb# (open drain buffer) signals the status of the device during each operat ion. in a system with mul- tiple memories the rb# pins can be connected al l together to provide a global status signal. even the write-intensive systems can take advantage of th e hy27(u/s)f(08/16)1g2m extend ed reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. optionally the chip could be offered with the ce# don?t care function. this option allows the direct download of the code from the nand flash memory device by a microcontrol ler, since the ce# transitions do not stop the read opera- tion. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. the cache program feature allows the data insertion in the ca che register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemente d. this feature allows to dramatically improve the read throughput when con- secutive pages have to be streamed out. this device includes also extra features like otp/unique id area, automatic read at power up, read id2 extension. the hynix hy27(u/s)f(08/16)1g2m seri es is available in 48 - tsop1 12 x 20 mm , 48 - wsop1 12 x 17 mm, fbga 9.5 x 12 mm. 1.1 product list part number orization vcc range package hy27sf081g2m x8 1.70 - 1.95 volt 63fbga / 48tsop1 / 48wsop1 HY27SF161G2M x16 hy27uf081g2m x8 2.7v - 3.6 volt hy27uf161g2m x16
rev 0.6 / mar. 2005 5 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash figure1: logic diagram 9 & |