?2002 fairchild semiconductor corporation RF1K49157 rev. b RF1K49157 6.3a, 30v, 0.030 ohm, single n-channel littlefet? power mosfet this single n-channel power mosfet is manufactured using an advanced megafet process. this process, which uses feature sizes approaching those of lsi integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. it was designed for use in applications such as switching regulators, switching convertors, motor drivers, relay drivers, and low voltage bus switches. this device can be operated directly from integrated circuits. formerly developmental type ta49157. features ?6.3a, 30v r ds(on) = 0.030 ? temperature compensating pspice? model peak current vs pulse width curve uis rating curve related literature - tb334 ?guidelines for soldering surface mount components to pc boards? symbol packaging jedec ms-012aa ordering information part number package brand RF1K49157 ms-012aa RF1K49157 note: when ordering, use the entire part number. for ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4915796. source (2) drain (8) nc (1) drain (7) drain (6) drain (5) source (3) gate (4) branding dash 1 2 3 4 5 data sheet january 2002
?2002 fairchild semiconductor corporation RF1K49157 rev. b absolute maximum ratings t a = 25 o c unless otherwise specified RF1K49157 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v gs 20 v drain current continuous (pulse width = 1s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed (figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 6.3 refer to peak current curve a pulsed avalanche rating (figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as refer to uis curve power dissipation t a = 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0.016 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. t j = 25 o c to 125 o c. electrical specifications t a = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v, (figure 12) 30 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a, (figure 11) 1 - 3 v zero gate voltage drain current i dss v ds = 30v, v gs = 0v t a = 25 o c--1 a t a = 150 o c--50 a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance r ds(on) i d = 6.3a (figures 9, 10) v gs = 10v - - 0.030 ? v gs = 4.5v - - 0.060 ? turn-on time t on v dd = 15v, i d 6.3a, r l = 2.38 ? , v gs = 10v, r gs = 25 ? - - 85 ns turn-on delay time t d(on) -22-ns rise time t r -43-ns turn-off delay time t d(off) - 125 - ns fall time t f -85-ns turn-off time t off - - 265 ns total gate charge q g(tot) v gs = 0v to 20v v dd = 24v, i d = 6.3a, r l = 3.81 ? (figure 14) -7088nc gate charge at 10v q g(10) v gs = 0v to 10v - 38 48 nc threshold gate charge q g(th) v gs = 0v to 2v - 2.8 3.5 nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 13) - 1575 - pf output capacitance c oss - 700 - pf reverse transfer capacitance c rss - 200 - pf thermal resistance junction-to-ambient r ja pulse width = 1s device mounted on fr-4 material - - 62.5 o c/w source to drain diode specifications parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 6.3a - - 1.25 v reverse recovery time t rr i sd = 6.3a, di sd /dt = 100a/ s--60ns RF1K49157
?2002 fairchild semiconductor corporation RF1K49157 rev. b typical performance curves figure 1. normalized power dissipation vs ambient temperature figure 2. maximum cont inuous drain current vs ambient temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area figure 5. peak current cap ability t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 2 1 0 25 50 75 100 125 15 0 3 i d , drain current (a) t a , ambient temperature ( o c) 7 6 5 4 t, rectangular pulse duration (s) 10 -3 10 -1 10 0 10 1 10 2 0.01 10 0.1 1 10 -2 10 3 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 z ja , normalized thermal impedance single pulse 0.5 0.2 0.1 0.05 0.01 0.02 v ds , drain to source voltage (v) 11010 0 0.01 1 100 10 0.1 0.1 i d , drain current (a) dc 100ms 1s 10ms limited by r ds(on) area may be operation in this v dss(max) = 30v t j = max rated, t a = 25 o c 5ms t, pulse width (s) 300 10 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 i dm , peak current capability (a) i = i 25 150 - t a 125 for temperatures above 25 o c derate peak current as follows: t a = 25 o c thermal impedance may limit current in this region v gs = 10v v gs = 20v RF1K49157
?2002 fairchild semiconductor corporation RF1K49157 rev. b note: refer to fairchild app lication notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature figure 11. normalized gate threshold voltage vs junction temperature typical performance curves (continued) 11010 0 10 0.1 50 1 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 150 o c starting t j = 25 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 10 20 30 01 2 3 45 v gs = 4v 40 50 i d , drain current (a) v ds , drain to source voltage (v) v gs = 7v v gs = 10v v gs = 20v pulse duration = 80 s v gs = 5v t a = 25 o c duty cycle = 0.5% max 0 3.0 4.5 6.0 7. 5 1.5 0 10 20 30 40 50 150 o c v dd = 15v i d(on) , on-state drain current (a) v gs , gate to source voltage (v) -55 o c 25 o c pulse duration = 80 s duty cycle = 0.5% max 50 100 150 200 250 0 4 v gs , gate to source voltage (v) r ds(on) , on-state resistance (m ? ) 2 i d = 15a 6 8 10 pulse duration = 80 s i d = 1.75a i d = 3.5a i d = 6.3a v dd = 15v duty cycle = 0.5% max 0 0.5 1.0 1.5 2.0 -80 -40 0 40 80 120 16 0 normalized on resistance t j , junction temperature ( o c) pulse duration = 80 s v gs = 10v, i d = 6.3a duty cycle = 0.5% max -80 -40 0 40 80 120 16 0 0 0.5 1.0 1.5 2.0 normalized gate threshold voltage t j , junction temperature ( o c) v gs = v ds , i d = 250 a RF1K49157
?2002 fairchild semiconductor corporation RF1K49157 rev. b figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an 7260. figure 14. normalized switching waveforms for constant gate current test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms typical performance curves (continued) 2.0 1.5 1.0 0.5 0 -80 -40 0 40 80 120 16 0 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 2500 0 0 5 10 15 20 2 5 c, capacitance (pf) c rss 500 c iss c oss v ds , drain to source voltage (v) 2000 1500 1000 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss = c ds + c gd 30 22.5 15 7.5 0 20 i gref () i gact () --------------------- - t, time ( s) 80 i gref () i gact () --------------------- - 10.0 7.5 5.0 2.5 0 v ds , drain-source voltage (v) v gs , gate-source voltage (v) r l = 4.76 ? i g(ref) = 0.8ma v gs = 10v v dd = bv dss v dd = 0.75 bv dss v dd = 0.50 bv dss v dd = 0.25 bv dss plateau voltages in descending order: v dd = bv dss t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av RF1K49157
?2002 fairchild semiconductor corporation RF1K49157 rev. b soldering precautions the soldering process creates a considerable thermal stress on any semiconductor component. the melting temperature of solder is higher than the maximum rated temperature of the device. the amount of time the device is heated to a high temperature should be minimized to assure device reliability. therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. always preheat the device. 2. the delta temperature between the preheat and soldering should always be less than 100 o c. failure to preheat the device can result in excessive thermal stress which can damage the device. 3. the maximum temperature gradient should be less than 5 o c per second when changing from preheating to soldering. 4. the peak temperature in the soldering process should be at least 30 o c higher than the melting point of the solder chosen. 5. the maximum soldering temperature and time must not exceed 260 o c for 10 seconds on the leads and case of the device. 6. after soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. during cooling, mechanical stress or shock should be avoided. figure 17. switching time test circuit figure 18. resistive switching waveforms figure 19. gate charge test circuit figure 20. gate charge waveform test circuits and waveforms (continued) v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20 v v ds v gs i g(ref) 0 0 RF1K49157
?2002 fairchild semiconductor corporation RF1K49157 rev. b pspice electrical model subckt RF1K49157 2 1 3 ;rev 3/14/95 ca 12 8 1.834e-9 cb 15 14 1.72e-9 cin 6 8 1.416e-9 dbody 7 5 dbdmod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 34.89 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthresh 6 21 19 8 1 eztempco 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 1.04e-9 lsource 3 7 0.237e-9 mos1 16 6 8 8 mstrong m = 0.99 mos2 16 21 8 8 mweak m = 0.01 rbreak 17 18 rbreakmod 1 rdrain 5 16 rdrainmod 4.39e-3 rgate 9 20 1.53 rin 6 8 1e9 rldrain 2 5 1.0 rlgate 1 9 10.4 rlsource 3 7 0.237 rsource 8 7 rsourcemod 4.44e-3 rthresh 22 8 rthresmod 1 rztempco 18 19 rztempcomod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 .model dbdmod d (is = 1.14e-12 rs = 6.01e-3 trs1 = 1.05e-4 trs2 = -2.46e-5 cjo = 2.62e-9 tt = 2.44e-8) .model dbreakmod d (rs = 4.89e- 1trs1 = 2.11e- 3trs2 = -3.19e-6) .model dplcapmod d (cjo = 1.007e- 9is = 1e-3 0n = 10) .model mstrong nmos (vto = 2.567 kp = 33.21 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweak nmos (vto=2.0225 kp = 33.21 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model rbreakmod res (tc1 = 9.59e- 4tc2 = -2.87e-7) .model rdrainmod res (tc1 = 8.08e-3 tc2 = 1.6e-5) .model rsourcemod res (tc1=0 tc2=0) .model rthreshmod res (tc1=-6.4e-4 tc2=-8.1e-6) .model rztempcomod res (tc1 = -2.43e- 3tc2 = 1.57e-6) .model s1amod vswitch (ron = 1e-5 r off = 0.1 von = -6.47 voff= -4.47) .model s1bmod vswitch (ron = 1e-5 r off = 0.1 von = -4.47 voff= -6.47) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -3.3 voff= 1.7) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 1.7 voff= -3.3) .ends note: for further discussion of the pspice m odel, consult a new pspice sub-circuit for the power mosfet featuring global temperature options; ieee power electronics specialist conference records, 1991. 1 gate lgate rgate eztempco + 12 13 8 13 15 s1a s1b s2a s2b ca cb egs eds rin cin mos1 mos2 rdrain dbreak ebreak dbody ldrain drain rsource lsource source rbreak rztempco vbat it evthresh esg dplcap 6 10 5 16 21 11 8 14 7 3 17 18 2 + + + + + + 20 9 rlgate rlsource rldrain 19 22 rvthresh 14 13 - 6 8 19 8 - - - 18 22 5 8 - - 6 8 17 18 - RF1K49157
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
|
