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Ordering number : ENN6471 Monolithic Linear IC LA8519M I/O Switch/Voice Signal-Processing IC for Cordless Telephones Overview The LA8519M is a cordless telephone base unit IC that provides I/O switching, voice signal processing, and other functions. It integrates, on a single chip, crosspoint switch, power amplifier, electronic volume and tone control, microphone amplifier, speech network, and other functions. Features * Allows switching between two anti-sidetone networks (near terminal/far terminal) depending on the line current, and thus achieves excellent sidetone characteristics over a wide range of line currents. * Built-in transmitter/receiver amplifier driver power supply switching circuit allows communication using extension without power from the telephone network. * The receiver amplifier supports both ceramic receivers (BTL) and dynamic receiver (single). * Built-in power amplifier (load: 8 to 32 ): VCC = 5 V, RL = 8 , Pomax = 200 mW * The power amplifier signal path includes an electronic volume control (7 steps of about 3.8 dB each) * Includes a 10-input/9-output crosspoint switch that provides mixing functions for easy implementation of systems that support a diverse range of signal path switching functions. Functions * Speech network block -- Impedance matching, 2-wire/4-wire converter, line driver, BN circuit network switching circuit, transmitter amplifier, BTL receiver amplifier, DTMF input, key tone input, receiver volume level switching, and power supply switching circuit. * Audio signal-processing block -- Power amplifier, electronic volume and tone control, preamplifier with ALC, voice level detection (VOX), beep tone input, ring tone (OSC) input, ring tone level switching, line volume level switching, microphone amplifier, crosspoint switch (10 x 9 point equivalent), and serial interface. Package Dimensions Unit:mm 3159-QIP64E [LA8519M] 17.2 14.0 0.35 33 1.0 1.6 1.0 48 49 0.8 1.6 1.0 0.15 32 17.2 14.0 0.8 17 1.0 1 16 3.0max 0.8 64 0.1 2.7 15.6 SANYO: QIP64E Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N3000RM (OT) No. 6471-1/29 LA8519M Specifications Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Line current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VL max IL max Pd max Topr Tstg Ta 70C (Mounted on a glass epoxy board: 120 x 120 x 1.6 mm3) Conditions Ratings 15 15 130 1000 -20 to +70 -40 to +150 Unit V V mA mW C C Operating Conditions at Ta = 25C Parameter Recommended supply voltage Allowable operating supply voltage range Symbol VCC VCC op VCC oppwr Conditions Other than the speech network Pin 17 Pin 28 Ratings 5.0 4.5 to 6.5 4.5 to 9.5 Unit V V V Electrical Characteristics Ratings Parameter Symbol Conditions min typ max [Speech Network Block] at Ta = 25C, Power supplied: VCC = 5 V, fIN = 1 kHz Line voltage (20 mA, power supplied/power off) Line voltage (50 mA, power supplied/power off) Line voltage (120 mA, power supplied) Line voltage (120 mA, power off) Transmitter gain (20 mA, power supplied) Transmitter gain (20 mA, power off) Transmitter gain (120 mA, power supplied/power off) Receiver gain (20 mA, power supplied) Receiver gain (120 mA, power supplied) Receiver gain (20 mA, power off) Receiver gain (120 mA, power off) DTMF gain (20 mA, power supplied/power off) DTMF gain (120 mA, power supplied/power off) KT gain (power supplied) KT gain (20 mA, power off) KT gain (120 mA, power off) Transmitter dynamic range (20 mA, power supplied/power off) Transmitter dynamic range (120 mA, power supplied/power off) Receiver dynamic range (power supplied) Receiver dynamic range (20 mA, power off) Receiver dynamic range (120 mA, power off) VL1 VL2 EVL3 LV3 EGt1 Gt1 Gt2 EGr1 EGr2 Gr1 Gr2 Gmf1 Gmf2 EGkt Gkt1 Gkt2 DRt1 DRt2 EDRs DRs1 DRs2 IL = 20 mA IL = 50 mA IL = 120 mA IL = 120 mA IL = 20 mA, VIN = -55 dBV IL = 20 mA, VIN = -55 dBV IL = 120 mA, VIN = -55 dBV IL = 20 mA, VIN = -20 dBV IL = 120 mA, VIN = -20 dBV IL = 20 mA, VIN = -20 dBV IL = 120 mA, VIN = -20 dBV IL = 20 mA, VIN = -30 dBV IL = 120 mA, VIN = -30 dBV IL = 20 mA/120 mA, VIN = -40 dBV IL = 20 mA, VIN = -40 dBV IL = 120 mA, VIN = -40 dBV IL = 20 mA, THD = 4% IL = 120 mA, THD = 4% IL = 20 mA/120 mA, RL = 150 , THD = 10% RL = 150 , IL = 20 mA, THD = 10% RL = 150 , IL = 120 mA, THD = 10% 3.3 4.5 7.1 7.0 42.5 42.3 38.3 -0.9 -7.4 -5.4 -8.7 27.7 23.6 10.0 5.8 9.0 2.5 4.5 0.5 0.3 0.5 3.8 5.2 8.5 8.4 44.5 44.3 40.3 1.1 -5.4 -3.4 -6.7 29.7 25.6 12.0 7.8 11.0 5.6 7.7 1.5 0.55 1.4 4.3 6.0 9.9 9.8 46.5 46.3 42.3 3.1 -3.4 -1.4 -4.7 31.7 27.6 14.0 9.8 13.0 V V V V dB dB dB dB dB dB dB dB dB dB dB dB Vp-p Vp-p Vp-p Vp-p Vp-p unit Continued on next page. No. 6471-2/29 LA8519M Continued from preceding page. Ratings Parameter Receiver BTL dynamic range (power supplied) Receiver BTL dynamic range (20 mA, power off) Receiver BTL dynamic range (120 mA, power off) MUTE input high-level voltage (power supplied/power off) MUTE input low-level voltage (power supplied/power off) Transmitter PADC attenuation (power supplied/power off) Receiver PADC attenuation (power supplied/power off) Internal supply voltage (power supplied) Internal supply voltage (20 mA, power off) Internal supply voltage (120 mA, power off) Internal reference voltage (power supplied) Internal reference voltage (20 mA, power off) Internal reference voltage (120 mA, power off) Symbol EDRb DRb1 DRb2 VIH VIL Gt Gr EVSP VSP1 VSP2 ES-VREF S-VREF1 S-VREF2 Conditions IL = 20 mA/120 mA, RL = 3 k, THD = 10% RL = 3 k, IL = 20 mA, THD = 10% RL = 3 k, IL = 120 mA, THD = 10% IL = 20 mA to 120 mA IL = 20 mA to 120 mA IL = 40 mA, pin 34: grounded through 24 IL = 40 mA, pin 34: grounded through 24 IL = 20 mA/120 mA IL = 20 mA IL = 120 mA IL = 20 mA/120 mA IL = 20 mA IL = 120 mA min 5 2 5 0.6 VSP 0 4.0 6.0 4.75 1.92 4.74 2.26 0.79 1.92 0.4 typ 10 3.4 8.4 max unit Vp-p Vp-p Vp-p V V dB dB V V V V V V [Voice Signal-Processing Block] at Ta = 25C, VCC = 5 V, fIN = 1 kHz, RL = 10 k (Crosspoint switch) Voltage gain Maximum input level Output noise voltage GSW VIN max VNOSW VGC THD VOS ALCW VNO VGm THD VNO VGp Po THD SVRR VNO VOXL VOXH Evrw GR GL GO VIN = -13 dBV, pin 58 input, pin 2 output THD = 1.5% Rg = 620 , 20 to 20 kHz VIN = -45 dBV VIN = -20 dBV VIN = -20 dBV From the point the ALC circuit turns on to the point the THD reaches 1%. Rg = 620 , 20 to 20 kHz VIN = -40 dBV VIN = -40 dBV Rg = 620 , 20 to 20 kHz RL = 8 , VIN = -30 dBV RL = 8 , THD = 10% VIN = -30 dBV Rg = 620 , fr = 100 kHz, Vr = -20 dBV Rg = 620 , 20 to 20 kHz VIN = -40 dBV, RL = 100 k VIN = -44 dBV, RL = 100 k 4.8 40 27.5 200 27.5 93 15 65 250 8.5 -2.5 -13.5 -0.5 -7.5 7.0 40 1.5 dB dBV Vrms (Preamplifier: input from the crosspoint switch) Voltage gain Total harmonic distortion ALC saturated output level ALC range Output noise voltage (Microphone amplifier) Voltage gain Total harmonic distortion Output noise voltage (Power amplifier) Voltage gain Maximum output power Total harmonic distortion Ripple rejection ratio Output noise voltage (VOX) Sensitivity 1 low level Sensitivity 2 high level (Electronic volume control) Step width (Attenuator) R-ATT attenuation LINE-ATT attenuation OSC-ATT attenuation 5.4 4.6 13.1 6.4 5.6 14.6 7.4 6.6 16.1 dB dB dB 2.9 3.8 4.7 dB 0.1 4.95 0.3 V V 29.5 275 0.8 50 35 100 1.5 31.5 dB mW % dB Vrms 29.5 0.05 65 31.5 1.0 250 dB % Vrms 10.5 0.26 115 12.5 1.0 137 dB % mVrms dB Vrms Continued on next page. No. 6471-3/29 LA8519M Continued from preceding page. Ratings Parameter (VREF) Output voltage (Serial Control) Clock frequency Input signal high level Input signal low level (Power Supply Switching) Pin 17 voltage 1 Pin 17 voltage 2 Quiescent current Vch1 Vch2 ICCO The voltage applied to pin 17 is valid. The voltage supplied from pin 48 is valid. With the power amplifier on 24 3.5 1.0 33.5 V V mA Fck VH VL 2.3 1.0 500 kHz V V VREF 2.07 2.27 2.47 V Symbol Conditions min typ max unit No. 6471-4/29 DTMF T R MUTE PAD C 34 33 + + + Block Diagram 48 POWER SUPPLY 47 46 45 44 43 42 41 40 39 38 37 36 35 TRANSMIT-AMP SW2 SW3 SW1 32 CLOCK SW4 31 DATA 30 CE 29 VOX OUT PWR-VCC 28 08 27 SP 26 PWR-GND 25 24 23 PWR MONI 22 21 NC MIC 20 -9.5DB MIC AMP SW5 REG 19 18 VCC 17 + + + + + R-ATT 0/-6DB 49 GAIN CTL HAND LINE-AMP 9.5DB -9.5DB 50 Line amplifier 51 BN1 RESET (PWR ON RESET) KT CPU INTERFACE 52 BN2 53 10 11 09 0A 0B 04 05 29 06 07 0F 2A 31 36 0E 16 1D 23 35 Electronic volume control EVR 30 3B 0D 15 1C 22 34 3A 0C 14 1B 21 33 39 P.VREF 13 1A 28 2F 12 20 27 2E 19 1F 26 2D POWER AMP 18 1E 25 2C 38 17 24 2B 32 37 54 01 02 03 RECEIVER-AMP 41.TI-NF 42.TI-OUT 43.TA-IN 44.DTMF-IN 45.SP-VREF 46.VSP 47.SP-VCC 48.VL 49.TOI 50.TOO 51.BN1 52.BN2 53.SP-GND 54.RI-IN 55.RI-OUT 56.HAND-NF 57.HAND-MONI 58.RF1-IN 59.RF2-IN 60.DOOR-IN 61.FIL-IN 62.FIL-OUT 63.CDC2-IN 64.LINE-OUT 55 56 57 HAND-AMP LA8519M Compander 1 58 RF1 Compander 2 59 RF2 Door phone 60 DOOR 61 CODEC1 DSP 62 FILTER 63 CODEC2 1.RF1-OUT 2.RF2-OUT 3.DOOR-OUT 4.CDC1-OUT 5.CDC2-OUT 6.ALC-CNT 7.BEEP-IN 8.OSC-IN 9.GND 10.ALC-IN 11.PRE-OUT 12.PRE-NF 13.VOXA-IN 14.VOXA-OUT 15.VREF 16.VOX-RCT 17.VCC 18.MIC-OUT 19.MIC-NF 20.MIC-IN 21.NC 22.EVR-OUT 23.PWR-IN 24.P-VREF 25.PWR-NF 26.P-GND 27.PWR-OUT 28.P-VCC 29.VOX-OUT 30.CE 31.DATA 32.CLOCK 33.RESET 34.PAD-CNT 35.MUTE 36.RV-NF 37.RV-OUT1 38.RV-OUT2 39.KT-IN 40.TI-IN 64 OSC-ATT 0/-16DB VOX RECT CMP VR ALC 7 8 9 10 11 L-ATT 0/-6DB VREF ALC-OUT VOX-RCT PRE AMP 12 13 VOX-IN 14 5V 15 + EXT.REG 16 + + + 1 2 3 4 5 6 Power supply BEEP-IN OSC-IN No. 6471-5/29 A13120 SW4-1 SW4-2 SW4-3 + 620 SW5-1 150 BTL-SW 1kHz 0.1F MUTE-SW 0.45V VCNT SW4-4 SP-IN VL RV2 3k INPUT RV1 20k + 10F 0.1F 0.1F 0.01F 47F 300 10F RAD-C-SW Test Circuit Diagram 100 k 100 k 38 33 RESET CLOCK 32 DATA 31 CE 30 VOX-OUT 29 100 k + 3.3k 48 VL VSP TI-NF TI-IN TA-IN KT-IN TI-OUT RV-NF MUTE CLOCK DATA CE SP-VOC SP-VREF DTMF-IN RV-OUT2 RV-OUT1 PAD-CNT 47 46 45 44 43 42 39 37 36 35 34 51 2SA608NP IL 51k 41 40 (10W) 82 (1W) 0.1F 49 TOI 5.6K 6800pF 8200pF 8.2K 82 7.5K 82 50 TOO 0.1F 600 620 6.2k 0.47F + 220F + + 22F 0.1F RESET-SW 330pF + 24k Data generator 51 BN1 1.3k VOX-OUT 100F 470F + 52 BN2 P-VCC 28 0.1F PWR-OUT 27 0.1F P-GND 26 PWR-NF 25 P-VREF 24 PWR-IN 23 0.22F EVR-OUT 22 NC 21 0.1F MIC-IN 20 3.3k MIC-NF 19 MIC-OUT 18 VOXA-IN VREF VCC 17 12 13 14 100 k 100k 0.1F 0.22F 10k 0.22F 10k 15 + 1.8k 53 SP-GND 0.22F 11k 54 RI-IN 180pF 150 k 8 (1W) 62k 150pF PWR-OUT 55 RI-OUT 56 HAND-NF 100 k 57 HAND-MONI LA8519M 2k + 0.22F 22k 0.1F 220F LA8519M 58 RF1-IN 0.1F 59 RF2-IN 0.1F 39k 60 DOOR-IN DRCT-SW 0.1F 47k 47K 61 FIL-IN 62 FILOUT 63 CDC2-IN BEEP-IN OSC-IN GND ALC-IN PRE-NF 0.1F 1 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 2 3 4 5 6 7 8 9 10 11 RF1-OUT RF2-OUT DOOR-OUT CDC1-OUT CDC2-OUT ALC-CNT PRE-OUT VOXA-OUT VOX-RCT 64 LINE-OUT 0.1F 100F 16 + 100k 1F VCC 5V 220F VOX-IN-SW 1F SW1-1 SW1-2 SW1-4 SW1-6 SW1-7 10k SW2-1 SW2-2 SW2-3 SW2-4 SW2-5 SW2-6 10F SW2-7 220k SW2-8 + SW3-1 SW3-2 SW3-3 SW3-4 OUTPUT 620 + INPUT 1kHz No. 6471-6/29 A13121 TIP LINE RING VCC 5V 0.1F DTMF-IN 20k KT-IN 0.1F 220F 100F 0.1F 24k Sample Application Circuit 100 k 43 33 RESET CLOCK 32 DATA 31 CE 30 0.1F + 0.1F 620 3.3k 48 VL VSP TI-NF TI-IN TA-IN KT-IN SP-VOC SP-VREF DTMF-IN TI-OUT RV-OUT2 RV-OUT1 RV-NF MUTE PAD-CNT 47 46 45 44 42 39 38 37 36 35 34 51 2SA608NP 51k 41 40 330 pF 100 k 82 (1W) 0.1F 49 TOI 5.6K 6800pF 8200pF 8.2K 82 7.5K 8.2 50 TOO 51 BN1 VOX-OUT 29 P-VCC 28 0.1F PWR-OUT 27 0.1F P-GND 26 PWR-NF 25 P-VREF 24 PWR-IN 23 0.22F EVR-OUT 22 NC 21 0.033F MIC-IN 20 100 k 1.3k + 1.8k 53 SP-GND 0.22F 11k 470F SP 62k 180pF 150 k 54 RI-IN LA8519M 55 RI-OUT 56 HAND-NF 100 k 330pF 57 HAND-MONI LA8519M 2k 0.22F 22k 0.1F + 220F Compander 1 58 RF1-IN 0.1F Compander 2 59 RF2-IN 0.1F 10k Door phone 60 DOOR-IN 61 FIL-IN 0.1F MIC-NF 19 MIC-OUT 18 ALC-IN PRE-NF VOXA-IN VREF VCC 17 9 0.1F 10 11 0.1F 330pF OSC-IN 12 13 100 k 0.1F 10k 14 15 100 k + 100F 3.3k MIC 330pF 1F + 52 BN2 DSP 62 FILOUT 63 CDC2-IN BEEP-IN OSC-IN GND 0.1F 1 0.1F 0.1F 0.1F 0.1F 0.1F 2 3 4 5 6 7 8 RF1-OUT RF2-OUT DOOR-OUT CDC1-OUT CDC2-OUT ALC-CNT PRE-OUT VOXA-OUT VOX-RCT 64 LINE-OUT 330pF 0.22F 10k 0.22F 47F 220k BEEP-IN 220F + 1F 220F 16 + 100 k FILTER 0.01F + + 47F + 0.1F 330pF R 6.2k T 0.47F CPU No. 6471-7/29 A13122 LA8519M Serial Data Format CE CLOCK DATA A6 A5 A4 A3 A2 A1 A0 D A6 to A0 Sets the address of the crosspoint switch or control switch (hexadecimal binary number) D Sets the on/off state of the crosspoint switch or control switch. (The switch is set to the on state when D is 1, and to the off state when 0.) Address Table Output Input LINE HAND RF1 RF2 DOOR CDC1 CDC2 MIC BEEP PRE LINE -- 01 02 03 -- 04 05 -- 06 07 HAND 08 -- 09 0A 0B 0C 0D -- 0E 0F RF1 10 11 -- 12 13 14 15 -- 16 -- RF2 17 18 19 -- 1A 1B 1C -- 1D -- DOOR -- 1E 1F 20 -- 21 22 -- 23 -- CDC1 24 25 26 27 28 -- -- 29 -- 2A CDC2 2B 2C 2D 2E 2F -- -- 30 -- 31 EVR 32 -- -- -- -- 33 34 -- 35 36 PRE 37 38 -- -- -- 39 3A 3B -- -- Other addresses Address No. 00 3C 3D 3E 3F 40 41 42 43 44 45 46 47 7D 7E 7F Mode Sets all crosspoint and control switches to the off state. *2 ALC control (D = 1: Off, D = 0: On) Transmitter/receiver control (SW1 and SW4 in the block diagram) *1 OSC input (SW5) control (D = 1: On, D = 0: Off) Power amplifier control (D = 1: On, D = 0: Off) Electronic volume control Electronic volume control Electronic volume control Electronic volume control Electronic volume control Electronic volume control Electronic volume control Electronic volume control 0 dB -4 dB -8 dB -12 dB -16 dB -20 dB -24 dB -28 dB *2 (Default value) Line attenuator (L-ATT) setting (D = 1: -6 dB, D = 0: 0 dB) Receiver attenuator (R-ATT) setting (D = 1: 0 dB, D = 0: -6 dB) Oscillator attenuator (OSC-ATT) setting (D = 1: 0 dB, D = 0: -16 dB) * With address 3D set to the on state, SW1 is set to enable the transmitter amplifier output (pin 42) and SW4 is set to enable either the receiver amplifier output (pin 55) or the KT (pin 39) signal. If a voltage is not supplied to VCC (pin 17) (i.e. the power off state), SW1 and SW4 are set to the same states as when address 3D is set to the on state. ** For addresses 00 and 40 to 47, the data D may be either 0 or 1. Notes: 1. The receiver attenuator (R-ATT) is set to -6 dB at power on or after a reset (pin 33 set to low, or address 00 accessed). 2. The line attenuator (L-ATT) is set to 0 dB at power on or after a reset (pin 33 set to low, or address 00 accessed). 3. The oscillator attenuator (OSC-ATT) is set to -16 dB at power on or after a reset (pin 33 set to low, or address 00 accessed). 4. The electronic volume control is set to 0 dB at power on or after a reset (pin 33 set to low, or address 00 accessed). 5. Addresses are expressed as hexadecimal numbers. 6. Since the LA8519M includes a power on reset function, all the crosspoint and control switches are reset to their default states when external power (pin 17: VCC) is applied. 7. Switches SW2 and SW3 in the block diagram are controlled by the MUTE pin (pin 35). The table lists the signals enabled by this pin. MUTE pin (pin 35) High/Open Low SW2 Transmitter (pin 42) and TA-IN (pin 43) DTMF pin (pin 44) SW3 Receiver (pin 55) KT pin (pin 39) No. 6471-8/29 LA8519M Serial Data Timing tCS CE fMAX tWH tWH tCH tWC CLOCK A6 A5 A3 A2 A5 DATA A4 A1 A0 D A6 tDS tDS * fMAX (maximum clock frequency) * tWL (clock low-level pulse width) * tWH (clock high-level pulse width) * tCS (chip enable setup time) * tCH (chip enable hold time) * tDS (data setup time) * tDH (data hold time) * tWC (chip enable pulse width) 500 kHz At least 1 s At least 1 s At least 1 s At least 1 s At least 1 s At least 1 s At least 1 s Note: The control data must be input at least 400 ms after the supply voltage is applied to the VCC pin (pin 17). No. 6471-9/29 LA8519M Pin Functions Pin No. Pin Notes Equivalent circuit VCC VREF 1 2 3 4 5 RF1-OUT RF2-OUT DOOR-OUT CDC1-OUT CDC2-OUT * These are the IC outputs. 10 k CP-SW 10 k 3 4 5 1 2 VCC 6 * Adjusts the ALC time constants 6 ALC-CNT This pin can be used to adjust the ALC attack time and recovery time. VCC VREF 7 8 58 59 63 BEEP-IN OSC-IN RF1-IN RF2-IN CDC2-IN * Beep tone amplifier input * Oscillator amplifier input * Compander 1 input * Compander 2 input * CDC2 amplifier input 30 k 8 58 59 63 7 30 k 9 GND Signal-processing system ground VCC VREF 24 k 10 ALC-IN * ALC input. The PRE output (pin 11) is input to this pin through a coupling capacitor. The ALC level can be adjusted by inserting a resistor in series. 10 10 k Continued on next page. No. 6471-10/29 LA8519M Continued from preceding page. Pin No. Pin Notes Equivalent circuit VCC VREF 11 12 PRE-OUT PRE-NF * Preamplifier output 12 11 VCC VREF 13 14 VOXA-IN VOXA-OUT * VOX amplifier input * VOX amplifier output 14 13 300 VCC 15 VREF * Internal reference voltage output 2.25 V 15 5 k VCC 4.7 k 16 VOX-RCT * VOX detection output. This circuit can also be used as a waveform shaping circuit by forcibly setting this pin to the high state. 4.7 k 16 17 VCC * External power supply input. This voltage is supplied to the signal-processing system and VSP (pin 46). Continued on next page. No. 6471-11/29 LA8519M Continued from preceding page. Pin No. Pin Notes Equivalent circuit VCC VRE 18 19 20 MIC-OUT MIC-NF MIC-IN * Microphone amplifier output * Microphone amplifier minus input * Microphone amplifier plus input 20 100 k 19 18 21 NC * Unused. 22 EVR-OUT * EVR amplifier output 22 P.VCC 23 24 25 27 PWR-IN P-VREF PWR-NF PWR-OUT * Power amplifier plus input * Power amplifier reference voltage (about 4/9 x P-VCC) * Power amplifier minus input * Power amplifier output 24 23 50 k 15 k 27 25 40 k 26 28 P-GND P-VCC * Power system ground * Power system power supply VCC 29 29 VOX-OUT * VOX output This is an open-collector output. Continued on next page. No. 6471-12/29 LA8519M Continued from preceding page. Pin No. Pin Notes VCC 100 k Equivalent circuit 30 31 32 33 CE DATA CLOCK RESET * Chip enable input * Data input * Clock input * Reset Power on reset. 30 31 32 33 1 k 1.5 V Logic S-VCC 4.7 k 34 PAD C * Pad control. The gain control based on line current and the BN switching operating current can be controlled by connecting this pin through a resistor to either ground or S-VCC (pin 47). 34 22 k VSP 50 k REF 35 MUTE * Muting control. This pin switches the transmitted audio and DTMF signals in the transmitter system and the KT and received signals in the receiver system. (Switches SW2 and SW3 in the block diagram.) When low, the DTMF and KT signals are enabled. 35 1 k VSP 37 REF 36 37 38 RV-NF RV-OUT1 RV-OUT2 * Receiver amplifier noise figure connection * Receiver amplifier 1 output * Receiver amplifier 2 output 36 10 k VSP 38 10 k Continued on next page. No. 6471-13/29 LA8519M Continued from preceding page. Pin No. Pin Notes Equivalent circuit VSP REF 44 k VSP 39 39 KT-IN * Key tone input VSP VSP 40 41 42 TI-IN TI-NF TI-OUT * Transmitter input amplifier plus input. Since no bias voltage is applied internally, a bias voltage must be applied through a resistor from the REF pin (pin 61). * Transmitter input amplifier minus input * Transmitter input amplifier output 41 40 42 VSP REF 40 k 43 43 TA-IN * Input for the line output VSP REF 20 k VSP 44 44 DTMF-IN * DTMF input Continued on next page. No. 6471-14/29 LA8519M Continued from preceding page. Pin No. Pin Notes VSP Equivalent circuit 15 k 45 REF * Speech network system internal reference voltage output. When the VCC (pin 17) voltage is over 3.5 V, the reference voltage is output from VREF (pin 15). When the VCC voltage is under 1.2 V, a voltage of about (2/5) x V is output. 45 10 k VREF 46 VSP * Speech network system internal power supply. A voltage of about 0.3 V less than the voltage applied to VCC is output when the VCC (pin 17) voltage is over 3.5 V. When the V CC voltage is under 1.2 V, a voltage of about 0.3 V less than the S-VCC (pin 47) voltage is output. 47 S-VCC * Speech network system power supply. When the VCC voltage is under 1.2 V, power is supplied to VSP (pin 46) based on the line power. 48 3 k 48 49 50 VL TOI TOO * Line current input and line voltage * Current input for the transmitter output current * Transmitter output current output 6.2 k 50 100 49 48 VL * First BN switching control input 51 52 BN1 BN2 * Second BN switching control input Connect these inputs when two balancing networks are used. When unused, leave these pins open. 51 52 53 SP-GND * Speech network system ground VSP REF 54 55 RI-IN RI-OUT * Receiver input amplifier minus input * Receiver input amplifier output 55 54 Continued on next page. No. 6471-15/29 LA8519M Continued from preceding page. Pin No. Pin Notes Equivalent circuit VCC 56 57 HAND-NF HAND-MONI * Handset amplifier minus input * Handset amplifier output 56 57 VCC VREF 60 DOOR-IN * Door phone input 50 k 60 10 k VCC VREF 61 62 FIL-IN FIL-OUT * FIL amplifier input * FIL amplifier output 61 300 62 VCC 64 LINE-OUT * Line amplifier output 64 10 k No. 6471-16/29 LA8519M Usage Notes Speech Network Circuit Block * External driver transistor R3 620 48 Line 7.5k 3.3k Tr 82 8200pF 82 R1 R2 8.2 51 BN1 8.2k 5.6k 1.3k 1.8k 52 BN2 6800pF A13123 C2 + 220F 47 VL 51 49 TOI C1 50 TOO S-VCC LA8519M Figure 1 Since the IC includes a built-in power amplifier, due to the allowable power dissipation limits, include a heat dissipation transistor as shown in figure 1, and dissipate the circuit current outside the IC. Set the allowable power dissipation for R1 and R2 according to the maximum expected circuit current. (The values shown are for reference purposes only.) Note: If oscillation occurs due to the load state between VL and ground, insert the capacitor C1 (about 0.1 F) shown in the figure. * Changing the DC resistance The DC resistance can be modified by using a variable resistor for R2 in figure 1. (See the figure below.) Note: Note that changing R2 will also change the transmitter gain and the balancing network conditions. * Determining the AC impedance The AC impedance is basically determined by R3 (620 ) and C2 (220 F) shown in figure 1 above page. Since in actual operation there will be other AC loads in addition to the speech network, adjust the total AC impedance for the whole system in combination with the speech network impedance. Note: Note that if R3 is changed, the DC resistance will change as well. Line Voltage vs. Line Current 12 Power supplied: VCC = 5 V 11 10 9 8 Power supplied: R2 = 10 Power off: R2 = 10 Power supplied: R2 = 8.2 Power off: R2 = 8.2 Line 7 6 5 4 3 2 10 20 30 40 50 60 70 80 90 100 110 120 130 Power supplied: R2 = 6.8 Power off: R2 = 6.8 Line current -- mA No. 6471-17/29 LA8519M * Anti-sidetone network The LA8519M can switch between two anti-sidetone networks, one for the near terminal and one for the far terminal, depending on the circuit current. (See figure 1 for the connections used.) The switching point can be changed by connecting PADC (pin 34) through a resistor to either ground or S-VCC (pin 47). If only one anti-sidetone network is used, short pin 51 to pin 52 as shown in figure 2. (The component values shown are for reference purposes only.) + 620 48 Line 1.5k 6.2k 0.01F 11k 82 8.2 51 BN1 3.3k Tr 82 50 TOO 51 49 TOI VL 47 S-VCC LA8519M 52 BN2 A13124 Figure 2 * Line voltage VL DC characteristics when VCC is not applied (Values shown are for reference purposes only.) + 620 48 VL BN Tr 82 82 50 TOO 8.2 3.3k 51 49 TOI 47 S-VCC + Load 46 VSP LA8519M A13125 The slope of the DC characteristics when VCC is not applied can be increased without changing the DC characteristics when VCC is applied by applying a load to VSP (pin 46). No. 6471-18/29 LA8519M * Receiver amplifier application circuits (1) When a dynamic receiver is used (Values shown are for reference purposes only.) Due to drive capacity considerations, a 300 resistor must be inserted in series. 300 0.47F + 10F 330pF 6.2k 100k 38 RV-OUT2 37 RV-OUT1 36 RV-NF A13126 (2) When a ceramic receiver is used (Values shown are for reference purposes only.) 0.47F 6.2k 330pF 100k 38 RV-OUT2 37 RV-OUT1 36 RV-NF A13127 * Receiver attenuator RV-OUT2 38 RV-OUT1 37 RV-NF 36 ATT SW4 A13128 Normally, the receiver attenuator is set to -6 dB. It can be set to 0 dB by setting address 7E to the on state with a serial data transfer. No. 6471-19/29 LA8519M * Speech network gain distribution DTMF-IN 44 TA-IN 43 42 VL 48 41 40 TI-IN Line driver amplifier 30 dB Transmitter PAD 0 dB *1 -3.5 dB *2 100 k 20 k SW2 0 dB SW1 0 dB Transmitter amplifier (15.5 dB) * IL = 20 mA ** IL = 120 mA Note: For a 600 line termination A13129 KT-IN 39 38 VL 48 BN 150 k 55 36 6.2 k 11 k 54 ATT 300 150 37 100 k Anti-sidetone circuit (-33.6 dB) Receiver input amplifier (22.7 dB) Receiver PAD 0 dB *1 -6.5 dB *2 SW3 0 dB SW4 4 dB ATT -6.5 dB 0 dB *3 Receiver output amplifier (24.7 dB) Attenuator (-9.5 dB) A13130 * IL = 20 mA ** IL = 120 mA *** When address 7E is set to the on state with a serial data transfer. Notes: 1. The gain values are rough values, and should be seen as target values during the design process. 2. Values in parentheses can be modified by external components. No. 6471-20/29 LA8519M * Speech network internal analog switch operation RESET (PWR ON RESET) 33 CPU INTERFACE BN1 GAIN CTL T R PAD-CNT 34 + + + 48 47 46 45 44 43 42 41 40 39 38 37 36 35 Power supply TRANSMIT AMP 1 2 1 2 SW1 2 1 ATT SW4 SW3 2 1 49 50 51 52 53 54 55 Line amplifier SW2 BN2 RECEIVER AMP MUTE -9.5 dB HAND A13131 Note: Switches SW2 and SW3 are controlled by the MUTE pin (pin 35). Switches SW1 and SW4 are controlled by address 3D as set by serial data transfers. Note that switches SW2 and SW3 operate together, as do switches SW1 and SW4. SW1 and SW4 Operation State Power supplied (initial state) Address 3D Power off SW1 1 2 2 SW4 1 2 2 Note: When the power is off, SW1 and SW4 go to the "2" positions, and their states cannot be changed. SW2 and SW3 Operation Pin 35 (MUTE) High Low SW2 1 2 SW3 1 2 Note: SW2 and SW3 operate as described above regardless of the power supplied/off state. * Line amplifier attenuator Normally, the line attenuator is set to 0 dB. It can be set to -6 dB by setting address to 7D and mode to D = 1 with a serial data transfer. 64 LINE-OUT A13132 ATT Crosspoint Switch * Oscillator amplifier attenuator Normally, the oscillator amplifier attenuator is set to -16 dB. It can be set to 0 dB by setting address to 7F and mode to D = 1 with a serial data transfer. 8 OSC-IN ATT SW5 A13133 No. 6471-21/29 LA8519M * VOX circuit (1) The VOX circuit detects whether there is conversation or not. When the signal level in the VOXA input block (when the application constants in the application circuit diagram are used) becomes over about -42 dBV, the VOX output pin (pin 29) goes low. The detection level can be set by setting the gain of the VOX input amplifier with resistors R1 and R2. (2) This circuit can be used as a waveform shaping circuit if VOX-RCT (pin 16) is connected to VCC, i.e. if pin 16 is set to the high level. Thus this circuit can also be used to recognize a 400 Hz beep tone. In this mode, there is no need to connect a capacitor to pin 16. RECT CMP 29 + - VREF 13 VOXA-IN R2 R1 A13134 VOX-RCT 16 + 14 15 * Power amplifier circuit applications (The component values are for reference purposes only.) C3 C4 PWR-VCC 28 C2 PWR-OUT 27 C1 PWR-GND 26 + C5 62 k + SP C1: 0.1 F C2: 0.1 F C3: 0.1 F C4: 220 F C5: 100 to 470 F C6: 220 F SP: 8 to 32 * Voltage gain: 20 to 30 dB * A frequency characteristics adjustment capacitor cannot be attached to the feedback resistor. PWR-NF 25 2 k PWR-VREF 24 + C6 PWR-IN 23 0.22 F PWR-MONI 22 Note: The power amplifier output goes to the high-impedance state in the muted state, i.e. when address 3F has been set to the off state. A13135 * Power amplifier phase compensation capacitors Of the external components, the capacitors C1 between pin 27 (output) and pin 26 (ground) and C2 between pin 27 and pin 28 (VCC) are power amplifier phase compensation capacitors. If these components are separated from their pins in the PCB layout, their phase compensation effect may be reduced and high-frequency oscillation may occur. We therefore strongly recommend using a layout in which the capacitors C1 and C2 are located as close as possible to their respective IC pins. In particular, C1, which is connected to ground, should be given priority in positioning close to the IC. Note that phase compensation not with capacitors alone, but with series resistors (on the order of 1 to 2.2 ) inserted is also possible. While this can increase the phase compensation effect, since it increases the parts count, we recommend using capacitors only. However, we do recommend phase compensation with resistors inserted if, due to the details of the layout, the power amplifier is subject to oscillation. Also note that the ceramic capacitor C3 between pins 26 and 28 has only a minimal phase compensation effect on normal power amplifiers, so is not required. However, there are cases where it does have a large effect due to the pattern layout, so we recommend creating a dummy pattern for this capacitor and handling it as a reserve component. No. 6471-22/29 LA8519M * Power amplifier VREF (pin 24) line Pin 24 is the reference voltage pin for the power amplifier, and is connected to pin 23 (the input) by an internal bias resistor. This means that pin 24 is part of the power amplifier plus input line system. If this line is affected by the power amplifier output or the VCC line, the resultant positive feedback can cause oscillation. Therefore, if at all possible, the pin 24 line should not be routed around other lines. If it must be routed around other lines, do not rout it adjacent to output or VCC lines, but rout it adjacent to ground lines to prevent interference. * LA8519M ground line rerouting (See the figure on the next page.) The LA8519M circuit blocks can be classified into three systems: (1) power amplifier, (2) speech network system, and (3) crosspoint switch and other small-signal processing systems. Since the IC itself, naturally, has a three-block structure, each block has independent VCC and ground pins. The best possible ground system design, is for external components that are connected to ground to be connected to the ground for the block to which they belong, and for the pattern to be formed so that these three lines are independent and connect to the ground of the power supply (regulator) that is the reference. However, since there are limitations on the area available on the printed circuit board, there are cases where a single line is connected to the reference ground. In this case, ground lines must be routed so that the ground lines that carry larger currents (power amplifier and line connection blocks) are closer to the power supply ground (and thus have a lower impedance)than ground lines for circuits with a lower current drain. If the large currents used by the power amplifier or other high-current system flow in the ground lines that handle the smaller currents from small-signal system or other low-current system, a loop may be formed and low band oscillation may occur. Therefore we recommend that the ground lines are designed, as described above, so that lines in which large currents flow are routed closest to the power supply ground. IC Usage Notes 1. If the LA8519M is used in the vicinity of its maximum ratings, even slight variations in operating conditions may result in the maximum ratings being exceeded. Since this can lead to damage to or destruction of the device, provide adequate margin in the fluctuations in the supply voltage and other parameters, and do not allow the maximum ratings to be exceeded. 2. Pin shorting If the LA8519M is left with output loads shorted for extended periods, it may be damaged or destroyed. Always use this device in a manner such that output loads are never shorted. No. 6471-23/29 VCC 5V 0.1F KT-IN Ground Line Routing DTMF-IN 20k 0.1F 220F 100F 0.1F 0.1F 100 k 43 33 RESET CLOCK 32 DATA 31 CE 30 0.1F + 3.3k 47 VSP TI-NF TI-IN TA-IN KT-IN SP-VOC SP-VREF DTMF-IN TI-OUT RV-OUT2 RV-OUT1 RV-NF MUTE PAD-CNT 46 45 44 42 39 38 37 34 51 2SA60BNP 48 51k 41 40 330 pF 100 k 36 35 24k 620 82 (1W) 0.1F 49 TOI 5.6K 6800pF 8200pF 8.2K 82 7.5K 8.2 50 TOO 51 BN1 VOX-OUT 29 P-VCC 28 0.1F PWR-OUT 27 0.1F 62k P-GND 26 PWR-NF 25 P-VREF 24 PWR-IN 23 0.22F EVR-OUT 22 NC 21 0.033F MIC-IN 20 3.3k MIC-NF 19 100 k MIC-OUT 18 PRE-NF VOXA-IN VREF VCC 17 10 11 0.1F 330pF OSC-IN 12 13 100 k 0.1F 10k 14 15 100 k + 1.3k 100 k + 1.8k 53 SP-GND 0.22F 11k 470F SP 180pF 150 K 54 RI-IN LA8519M 55 RI-OUT 56 HAND-NF 100 K 330pF 57 HAND-MONI LA8519M 2k 0.22F 22k 0.1F + 220F 58 RF1-IN 0.1F 59 RF2-IN 0.1F 10k 60 DOOR-IN 61 FIL-IN 0.1F 100F MIC 1F + 52 BN2 62 FILOUT 63 CDC2-IN BEEP-IN OSC-IN GND ALC-IN 0.1F 2 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 3 4 5 6 7 8 9 RF1-OUT RF2-OUT DOOR-OUT CDC1-OUT CDC2-OUT ALC-CNT PRE-OUT VOXA-OUT VOX-RCT 64 LINE-OUT + 330pF 0.22F 47F 220k BEEP-IN 0.22F 10k 220F 1F 220F 16 + 1 330pF FILTER VL 0.01F + + 47F + 0.1F 330pF R 6.2k T 0.47F No. 6471-24/29 A13136 LA8519M Line Voltage vs. Line Current 10 46 Transmitter Gain vs. Line Current (Power off) VCC = 0 V VIN= -55 dBV fin = 1 kHz Input: pin 40 Output: pin 48 Power supplied: VCC = 5 V 9 8 45 PA roun -C: G PAD Transmitter gain -- dB 44 f Of C: DPA D-C Line voltage -- V oun : Gr 7 6 5 4 3 2 0 Power supplied Power off 43 de d ded t hrou thro 42 ugh gh 3 6 k 75 k 41 40 PAD-C: Grounded through 51 k 10 20 30 40 50 60 70 PAD-C: Grounded through 24 k 80 90 100 110 120 130 140 10 20 30 40 50 60 70 80 90 100 110 120 130 140 39 0 Line current -- mA Line current -- mA Transmitter Gain vs. Line Current (Power supplied) 46 10 Transmitter Dynamic Range vs. Line Current (Power off) 9 Transmitter dynamic range -- Vp-p 45 Transmitter gain -- dB 44 VCC = 5 V VIN = -55 dBV fin = 1 kHz Input: pin 40 Output: pin 48 8 7 6 5 4 3 2 1 0 0 VCC = 0 V THD = 4 % fin = 1 kHz Input: pin 40 Output: pin 48 D PA -C: G PAD round ed th rough 24 k 10 20 30 10 20 30 -C: Gro und PA DC: 43 ed t hro ugh Of f 42 75 k 41 40 PAD-C: Grounded through 51 k PAD-C: Grounded through 36 k 39 0 40 50 60 70 80 90 100 110 120 130 140 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Line current -- mA Line current -- mA Transmitter Dynamic Range vs. Line Current (Power supplied) 10 9 32 DTMF Gain vs. Line Current (Power off) 31 30 Transmitter dynamic range -- Vp-p 8 7 6 5 4 3 2 1 0 0 DTMF gain -- dB VCC = 5 V THD = 4 % fin = 1 kHz Input: pin 40 Output: pin 48 VCC = 0 V VIN = -30 dBV fin = 1 kHz Input: pin 44 Output: pin 48 PA C: D- PA PAD -C: G ded t roun 4 gh 2 hrou k :G D-C 29 28 27 26 25 24 0 PAD-C: Grounded through 51 k PAD-C: Grounded through 36 k 10 20 30 40 50 60 70 80 90 100 110 120 130 140 rou nde d th Of f 75 k rou gh 40 50 60 70 80 90 100 110 120 130 140 Line current -- mA Line current -- mA DTMF Gain vs. Line Current (Power supplied) 32 31 30 0 DTMF Gain vs. Line Current (Power off) -1 -2 Receiver gain -- dB DTMF gain -- dB VCC = 5 V VIN = -30 dBV fin = 1 kHz Input: pin 44 Output: pin 48 PAD-C: Grounded through 51 k PAD -3 -4 -5 -6 -7 -8 -9 VCC = 0 V VIN = -20 dBV fin = 1 kHz Input: pin 48 Output: TP65 PAD -C: G round ed th rough 24 k 0 10 20 30 PA PA D-C D PA -C: D- 29 28 27 26 25 24 Gro C: -C: Of f PAD-C: Grounded through 51 k PAD-C: Grounded through 36 k 40 50 60 70 80 90 100 110 120 130 140 :G rou d th nde und ed t hro ugh Of f Line current -- mA gh rou 75 k PAD-C: Ground PAD-C: Grounded through 36 k -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Line current -- mA 75 k ed through 24 k No. 6471-25/29 LA8519M Receiver Characteristics vs. Line Current (Power supplied) 2 1 Receiver BTL Dynamic Range vs. Line Current (Power off) 10 Receiver BTL dynamic range -- Vp-p 0 Receiver gain -- dB -1 -2 -3 -4 -5 -6 -7 -8 0 VCC = 5 V VIN = -20 dBV fin = 1 kHz Input: pin 48 Output: TP65 9 8 7 6 5 4 3 2 1 0 0 VCC = 0 V THD = 10 % fin = 1 kHz Input: pin 48 Output: pins 37 and 38 RL = 3 k -C: PAD f Of C: D75 k PA ugh thro ded PAD-C: Grounded through 51 k PAD-C: Grounded through 36 k 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Receiver BTL Dynamic Range vs. Line Current (Power supplied) 12 2 : Grou PAD-C nded th rough 24 k 10 20 30 10 20 30 10 20 30 un Gro 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Line current -- mA Line current -- mA Receiver Dynamic Range vs. Line Current (Power off) VCC = 0 V THD = 10 % fin = 1 kHz Input: pin 48 Output: TP65 RL = 150 Receiver BTL dynamic range -- Vp-p Receiver dynamic range -- Vp-p 11 10 VCC = 5 V THD = 10 % fin = 1 kHz Input: pin 48 Output: pins 37 and 38 RL = 3 k 1.5 9 1 8 0.5 7 6 0 40 Line current -- mA 50 60 70 80 90 100 110 120 130 140 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Line current -- mA Receiver Dynamic Range vs. Line Current (Power supplied) 3 12 KT Gain vs. Line Current (Power off) VCC = 0 V VIN = -40 dBV fin = 1 kHz Input: pin 39 Output: TP65 Receiver dynamic range -- Vp-p 2.5 1.5 KT gain -- dB 2 VCC = 5 V THD = 10 % fin = 1 kHz Input: pin 48 Output: TP65 RL = 150 11 10 9 1 8 0.5 7 0 0 40 50 60 70 80 90 100 110 120 130 140 6 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Line current -- mA Line current -- mA KT Gain vs. Line Current (Power supplied) 14 13 25 12 30 Quiescent Current vs. Supply Voltage 11 10 9 8 7 6 Quiescent current -- mA Power amplifi er on KT gain -- dB 20 Power ampl ifier off 15 VCC = 5 V VIN = -40 dBV fin = 1 kHz Input: pin 39 Output: TP65 0 40 50 60 70 80 90 100 110 120 130 140 10 5 3 4 5 6 7 8 9 Line current -- mA Supply voltage, VCC -- V No. 6471-26/29 LA8519M Reference Voltage (pin 15) vs. Supply Voltage 2.6 2.4 2.2 Power Amplifier: Output Power vs. Distortion Total harmonic distortion, THD -- % 100 7 5 3 2 10 7 5 3 2 1 7 5 3 2 2 3 5 7 100 2 3 5 7 1000 Reference voltage (pin 15) fin = 1 kHz Input: pin 23 Output: pin 27 RL = 8 Voltage -- V 2.0 1.8 1.6 1.4 1.2 1.0 2 5V 7.5 V 3 4 5 6 7 8 9 Supply voltage, VCC -- V 0.1 10 Output power -- mW Power Amplifier: Output Noise Voltage vs. Supply Voltage 100 1000 Power Amplifier: Output Power vs. Power Dissipation 7 5 7 Output noise voltage -- Vrms With the input shorted Output: pin 27 RL = 8 Power dissipation -- mV 3 2 7.5 V fin = 1 kHz Input: pin 23 Output: pin 27 RL = 8 5 5V 100 7 5 3 2 3 2 10 4 5 6 7 8 9 10 11 12 Supply voltage, VCC -- V 10 10 2 3 5 7 100 2 3 5 7 1000 Output power -- mW Power Amplifier: Supply Voltage vs. Output Power 10000 7 5 3 2 Power Amplifier Ripple Rejection Ratio vs. Supply Voltage 60 Ripple rejection ratio -- dB Output power -- mV 1000 7 5 3 2 100 7 5 3 2 10 4 THD : 10 % fin = 1 kHz Input: pin 23 Output: pin 27 RL = 8 50 40 30 5 6 7 8 9 10 11 12 20 4 fin = 100 Hz Vrin = 100 mVrms RL = 8 RL = 620 5 6 7 8 9 10 11 12 Supply voltage, VCC -- V Supply voltage, VCC -- V Microphone Amplifier Input/Output Characteristics Total harmonic distortion, THD -- % 10000 7 5 3 2 Crosspoint Switch Input/Output Characteristics t le Total harmonic distortion, THD -- % 100 7 5 3 2 10000 7 5 3 2 Output voltage -- mVrms 1000 7 5 3 2 100 7 5 3 2 10 7 5 3 2 1 1 tp Ou ut l 10 7 5 3 2 1 7 5 3 2 Output voltage -- mVrms VCC = 5 V fin = 1 kHz Input: pin 20 Output: pin 18 eve l 1000 7 5 3 2 100 7 5 3 2 10 7 5 3 2 1 10 VCC = 5 V fin = 1 kHz Input: pin 58 Output: pin 2 Ou tpu vel 100 7 5 3 2 10 7 5 3 2 D rti isto on 1 7 5 3 2 0.1 7 5 3 2 Distortion 0.1 7 5 3 2 3 5 7 2 3 5 7 10 2 0.01 100 2 3 5 7 100 2 3 5 0.01 7 1000 Input voltage -- mVrms Input voltage -- mVrms No. 6471-27/29 LA8519M Preamplifier ALC Characteristics 1000 7 5 3 2 0 -2 -4 -6 Electronic Volume Control Step Width VCC = 5 V fin = 1 kHz VIN = -20 dBV Output level Voltage gain -- dB Output voltage -- mVrms 100 7 5 3 2 10 7 5 3 2 1 7 5 3 2 1.0 10 2 3 5 7 100 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 0 Distortio n VCC = 5 V fin = 1 kHz Input: pin 63 Output: pin 11 Address 3A: On 2 3 5 7 1000 1 2 3 4 5 6 7 Input voltage -- mVrms Step PRE/Microphone Amplifier Output Noise Voltage vs. Supply Voltage 100 Crosspoint Switch Output Noise Voltage vs. Supply Voltage 100 7 7 PRE-OUT Output noise voltage -- Vrms 5 3 2 Output noise voltage -- Vrms 5 MIC-OUT TP65-OUT EVR-OUT 3 10 7 5 3 2 RF1-OUT 2 10 4 5 6 7 8 9 1 4 5 6 7 8 9 Supply voltage, VCC -- V Supply voltage, VCC -- V Crosspoint Switch Crosstalk vs. Input Level -60 -70 Crosspoint Switch Crosstalk vs. Input Level -60 -70 VCC = 5 V with 1 k-BPF Input: pin 58 Output level -- dBV VCC = 5 V with 1 k-BPF Input: pin 58 Output level -- dBV -80 -80 -90 -90 TP65-OUT/ADDRESS : 08 ON T/AD RE-OU DRESS : 39 ON S ES : 12 ON TP65-OUT -100 -100 P PRE-OUT -110 MIC-OUT RF1-OUT EVR-OUT -110 MIC-OUT/ADDRESS : 30 ON RF -40 -30 -120 -130 -50 -120 -130 -50 1- T OU /AD DR EVR-OUT/ADDRESS : 33 ON -20 -10 0 -40 -30 -20 -10 0 Input level -- dBV Input level -- dBV VOX Waveform Shaper Duty Ratio vs. Input Level 100 90 80 70 VOX Attenuation vs. Supply Voltage -40 VCC = 5 V f = 1 kHz With the VOX.C pin connected to VCC Output level -- dBV f = 1 kHz Input: pin 13 Output: pin 29 -41 Duty -- % 60 50 40 30 20 10 0 -50 -45 -40 -35 -30 -25 -20 -15 -10 ON -42 OFF -43 -44 4 5 6 7 8 9 Input level -- dBV Supply voltage, VCC -- V No. 6471-28/29 LA8519M Equivalent Input Noise Voltage vs. Supply Voltage 10 Equivalent input noise voltage -- Vrms 7 PRE-OUT 5 3 2 MIC-OUT 1 4 5 6 7 8 9 Supply voltage, VCC -- V Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 2000. Specifications and information herein are subject to change without notice. PS No. 6471-29/29 |
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