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MCP4706/4716/4726
8-/10-/12-Bit Voltage Output Digital-to-Analog Converter with EEPROM and I2C Interface
Features
* Output Voltage Resolutions - 12-bit: MCP4726 - 10-bit: MCP4716 - 8-bit: MCP4706 * Rail-to-Rail Output * Fast Settling Time of 6 s (typical) * DAC Voltage Reference Options - VDD - VREF Pin * Output Gain Options - Unity (1x) - 2x, only when VREF pin is used as voltage source * Nonvolatile Memory (EEPROM) - Auto Recall of Saved DAC register setting - Auto Recall of Saved Device Configuration (Voltage Reference, Gain, Power Down) * Power-Down Modes - Disconnects output buffer - Selection of VOUT pull-down resistors (640 k, 125 k, or 1 k) * Low Power Consumption - Normal Operation: 210 A typ. - Power Down Operation: 60 nA typ. (PD1:PD0 = "11") * Single-Supply Operation: 2.7V to 5.5V * I2CTM Interface: - Eight Available Addresses - Standard (100 kbps), Fast (400 kbps), and High-Speed (3.4 Mbps) Modes * Small 6-lead SOT-23 and DFN (2x2) Packages * Extended Temperature Range: -40C to +125C
Package Types
MCP4706 / 16 / 26
VOUT 1 VSS 2 VDD 3
6 VREF VREF 1 5 SCL 4 SDA
6 VOUT EP 7 5 VSS 4 VDD
SCL 2 SDA 3
SOT-23-6
2x2 DFN-6*
* Includes Exposed Thermal Pad (EP); see Table 3-1.
Description
The MCP4706/4716/4726 are single channel 8-bit, 10-bit, and 12-bit buffered voltage output Digital-toAnalog Converters (DAC) with nonvolatile memory and an I2C Serial Interface. This family will also be referred to as MCP47X6. The VREF pin or the device VDD can be selected as the DAC's reference voltage. When VDD is selected, VDD is connected internally to the DAC reference circuit. When the VREF pin is used, the user can select the output buffer's gain to 1 or 2. When the gain is 2, the VREF pin voltage should be limited to a maximum of VDD/2. The DAC Register value and configuration bits can be programmed to nonvolatile memory (EEPROM). The nonvolatile memory holds the DAC Register and configuration bit values when the device is powered off. A device reset (such as a Power On Reset) latches these stored values into the volatile memory. Power-down modes enable system current reduction when the DAC output voltage is not required. The VOUT pin can be configured to present a low, medium, or high resistance load. These devices have a two-wire I2CTM compatible serial interface for standard (100 kHz), fast (400 kHz), or high speed (3.4 MHz) mode. These devices are available in small 6-pin SOT-23 and DFN 2x2 mm packages.
Applications
* * * * * * Set Point or Offset Trimming Sensor Calibration Low Power Portable Instrumentation PC Peripherals Data AcquisitionSystems Motor Control
(c) 2011 Microchip Technology Inc.
DS22272A-page 1
MCP4706/4716/4726
Block Diagram
VREF VREF1:VREF0 VDD VDD VSS I2C Interface Logic
Buffer
Reference Selection
VRL
Gain (1x or 2x) (G = 0 or 1) VOUT
PD1:PD0 Resistor Ladder
Op Amp
DAC Register EEPROM Control Logic
SDA SCL
PD1:PD0 125 k 640 k 1 k VW
DS22272A-page 2
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Voltage on VDD with respect to VSS ................ -0.6V to +6.5V Voltage on all pins with respect to VSS ................................................................................ -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI) ....................................................................................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ....................................................................................20 mA Maximum input current source/sunk by SDA, SCL pins ........................................................................................2 mA Maximum output current sunk by SDA Output pin ......................................................................................25 mA Maximum current out of VSS pin ...................................50 mA Maximum current into VDD pin ......................................50 mA Maximum current sourced by the VOUT pin ..................40 mA Maximum current sunk by the VOUT pin........................40 mA Maximum current sunk by the VREF pin .........................40 A Package power dissipation (TA = +50C, TJ = +150C) SOT-23-6 .......................................................452 mW DFN-6 ..........................................................1098 mW Storage temperature .....................................-65C to +150C Ambient temperature with power applied ......................................................................-55C to +125C ESD protection on all pins .................................... 6 kV (HBM) .................................................................................... 400V (MM) Maximum Junction Temperature (TJ) ......................... +150C
(c) 2011 Microchip Technology Inc.
DS22272A-page 3
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 k from VOUT to GND, CL = 100 pF, TA = -40C to +125C. Typical values at +25C.
Parameters Power Requirements Input Voltage Input Current
Symbol VDD IDD
Min 2.7 --
Typical -- 210
Max 5.5 400
Units V A
Conditions
VREF1:VREF0 = `00', SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 VREF1:VREF0 = `11', VREF = VDD, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 PD1:PD0 = `01' (Note 6), VOUT not connected RAM retention voltage, (VRAM) < VPOR (Note 1, Note 4)
--
210
400
A
Power-Down Current Power-On Reset Threshold Power-Up Ramp Rate
Note 1: 2: 3: 4: 5: 6: 7:
IDDP VPOR VRAMP
-- -- 1
0.09 2.2 --
2 -- --
A V V/S
This parameter is ensured by design and is not 100% tested. This gain error does not include offset error. See Section 2 for more details in plots. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. This parameter is ensured by characterization, and not 100% tested. The PD1:PD0 = `10', and `11' configurations should have the same current. VDD = 5.5V.
DS22272A-page 4
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 k from VOUT to GND, CL = 100 pF, TA = -40C to +125C. Typical values at +25C.
Parameters DC Accuracy Offset Error Offset Error Temperature Coefficient Zero Scale Error
Symbol VOS VOS/C
Min
Typical 0.02
Max 0.75 -- -- 2.0 7.7 30.8 5.2 20.5 82.0 2 2 2 --
Units
Conditions
% of FSR Code = 0x000h VREF1:VREF0 = `00', G = `0' ppm/C ppm/C LSb LSb LSb LSb LSb LSb -40C to +25C +25C to +85C MCP4706, Code = 0x00h MCP4716, Code = 0x000h MCP4726, Code = 0x000h MCP4706, Code = 0xFFh MCP4716, Code = 0x3FFh MCP4726, Code = 0xFFFh
-- --
1 2 0.13 0.52 2.05 0.3 1.1 4.1 -0.10 -0.10 -0.10 -3 8 10 12
EZS
-- -- --
Full Scale Error
EFS
-- -- --
Gain Error (Note 2)
gE
-2 -2 -2
% of FSR MCP4706, Code = 0xFFh VREF1:VREF0 = `00', G = `0' % of FSR MCP4716, Code = 0x3FFh VREF1:VREF0 = `00', G = `0' % of FSR MCP4726, Code = 0xFFFh VREF1:VREF0 = `00', G = `0' ppm/C bits bits bits MCP4706 MCP4716 MCP4726 MCP4706 (codes: 6 to 250) MCP4716 (codes: 25 to 1000) MCP4726 (codes: 100 to 4000) MCP4706 (codes: 6 to 250) MCP4716 (codes: 25 to 1000) MCP4726 (codes: 100 to 4000)
Gain Error Drift Resolution
G/C n
--
INL Error (Note 7)
INL
-0.907 -3.625 -14.5
0.125 0.5 2 0.0125 0.05 0.2
+0.907 +3.625 +14.5 +0.05 +0.188 +0.75
LSb LSb LSb LSb LSb LSb
DNL Error (Note 7)
DNL
-0.05 -0.188 -0.75
Note 1: 2: 3: 4: 5: 6: 7:
This parameter is ensured by design and is not 100% tested. This gain error does not include offset error. See Section 2 for more details in plots. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. This parameter is ensured by characterization, and not 100% tested. The PD1:PD0 = `10', and `11' configurations should have the same current. VDD = 5.5V.
(c) 2011 Microchip Technology Inc.
DS22272A-page 5
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 k from VOUT to GND, CL = 100 pF, TA = -40C to +125C. Typical values at +25C.
Parameters Output Amplifier Minimum Output Voltage Maximum Output Voltage Phase Margin Slew Rate Short Circuit Current Settling Time Power Down Output Disable Time Delay
Symbol VOUT(MIN) VOUT(MAX) PM SR ISC tSETTLING TPDD
Min -- -- -- -- 7 -- --
Typical 0.01 VDD - 0.04 66 0.55 15 6 1
Max -- -- -- -- 24 -- --
Units V V Degree () V/s mA s s Note 3
Conditions Output Amplifier's minimum drive Output Amplifier's maximum drive CL = 400 pF, RL =
PD1:PD0 = "00" -> `11', `10', or `01' started from falling edge SCL at end of ACK bit. VOUT = VOUT - 10 mV. VOUT not connected. PD1:PD0 = `11', `10', or `01' -> "00" started from falling edge SCL at end of ACK bit. Volatile DAC Register = FFh, VOUT = 10 mV. VOUT not connected. Buffered Mode Unbuffered Mode Unbuffered Mode Unbuffered Mode VREF = 2.048V 0.1V, VREF1:VREF0 = `10', G = `0' VREF = 2.048V 0.1V, VREF1:VREF0 = `10', G = `1' VREF = 2.048V 0.1V, VREF1:VREF0 = `10', G = `0', Frequency = 1 kHz 1 LSb change around major carry (800h to 7FFh)
Power Down Output Enable Time Delay
TPDE
--
10.5
--
s
External Reference (VREF) (Note 1) Input Range VREF 0.04 0 Input Impedance Input Capacitance -3 dB Bandwidth RVREF C_REF -- -- -- -- Total Harmonic Distortion THD -- -- -- 210 29 86.5 67.7 -73 VDD 0.04 VDD -- -- -- -- -- V V k pF kHz kHz dB
Dynamic Performance (Note 1) Major Code Transition Glitch Digital Feedthrough
Note 1: 2: 3: 4: 5: 6: 7:
-- --
45 <10
-- --
nV-s nV-s
This parameter is ensured by design and is not 100% tested. This gain error does not include offset error. See Section 2 for more details in plots. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. This parameter is ensured by characterization, and not 100% tested. The PD1:PD0 = `10', and `11' configurations should have the same current. VDD = 5.5V.
DS22272A-page 6
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 k from VOUT to GND, CL = 100 pF, TA = -40C to +125C. Typical values at +25C.
Parameters Digital Interface Output Low Voltage Input High Voltage (SDA and SCL Pins) Input Low Voltage (SDA and SCL Pins) Input Leakage Pin Capacitance EEPROM EEPROM Write Time Data Retention Endurance
Note 1: 2: 3: 4: 5: 6: 7:
Symbol VOL VIH VIL ILI CPIN TWRITE
Min -- 0.7VDD -- -- -- -- -- 1
Typical -- -- -- -- -- 25 200 --
Max 0.4 -- 0.3VDD 1 3 50 -- --
Units V V V A pF ms Years Million Cycles IOL = 3 mA
Conditions
SCL = SDA = VSS or SCL = SDA = VDD (Note 5)
At +25C, (Note 1) At +25C, (Note 1)
This parameter is ensured by design and is not 100% tested. This gain error does not include offset error. See Section 2 for more details in plots. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. This parameter is ensured by characterization, and not 100% tested. The PD1:PD0 = `10', and `11' configurations should have the same current. VDD = 5.5V.
(c) 2011 Microchip Technology Inc.
DS22272A-page 7
MCP4706/4716/4726
1.1
VDD tPORD SCL SDA VIH
I2C Mode Timing Waveforms and Requirements
VPOR (VBOR) tBORD VIH
VOUT I2C Interface is operational
VOUT pulled down by internal 500 k (typical) resistor
FIGURE 1-1:
Power-On and Brown-Out Reset Waveforms.
ACK Stop Start ACK
SDA
SCL tPDE VOUT tPDD
FIGURE 1-2: TABLE 1-1:
I2C Power-Down Command Timing. RESET TIMING
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym tPORD tBORD TPDD Min -- -- -- Typ 60 1 2.5 Max -- -- -- Units s s s Conditions Monitor ACK bit response to ensure device responds to command. VDD transitions from VDD(MIN) > VPOR VOUT driven to VOUT disabled VDD = 5V PD1:PD0 `00' (from `01', `10', or `11'), from falling edge SCL at end of ACK bit. VDD = 3V PD1:PD0 `00' (from `01', `10', or `11'), from falling edge SCL at end of ACK bit. PD1:PD0 `01', `10', or `11' (from `00'), from falling edge SCL at end of ACK bit.
Parameters Power Up Reset Delay Brown Out Reset Delay Power Down Disable Time Delay
--
5
--
s
Power Down Enable Time Delay
TPDE
--
10.5
--
s
DS22272A-page 8
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
VIH SCL 90 SDA VIL START Condition STOP Condition 91 92 93 111
FIGURE 1-3: TABLE 1-2:
I2C Bus Start/Stop Bits Timing Waveforms. I2C BUS START/STOP BITS REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in Electrical characteristics Characteristic SCL pin Frequency Min 0 0 0 0 -- -- -- -- 4700 600 160 160 4000 600 160 160 4000 600 160 160 4000 600 160 160 25 25 Max 100 400 1.7 3.4 400 400 400 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units kHz kHz MHz MHz pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns uS uS Conditions Cb = 400 pF, 2.7V - 5.5V Cb = 400 pF, 2.7V - 5.5V Cb = 400 pF, 4.5V - 5.5V Cb = 100 pF, 4.5V - 5.5V
I2C AC Characteristics
Param. Symbol No. FSCL
D102
90
91
92
93
94 95
Standard Mode Fast Mode High-Speed 1.7 High-Speed 3.4 Cb Bus capacitive 100 kHz mode loading 400 kHz mode 1.7 MHz mode 3.4 MHz mode TSU:STA START condition 100 kHz mode Setup time 400 kHz mode 1.7 MHz mode 3.4 MHz mode THD:STA START condition 100 kHz mode Hold time 400 kHz mode 1.7 MHz mode 3.4 MHz mode TSU:STO STOP condition 100 kHz mode Setup time 400 kHz mode 1.7 MHz mode 3.4 MHz mode THD:STO STOP condition 100 kHz mode Hold time 400 kHz mode 1.7 MHz mode 3.4 MHz mode THVCSU HVC to SCL Setup time THVCHD SCL to HVC Hold time
Only relevant for repeated START condition
After this period the first clock pulse is generated
High Voltage Commands High Voltage Commands
(c) 2011 Microchip Technology Inc.
DS22272A-page 9
MCP4706/4716/4726
103 SCL SDA In 109 SDA Out 109 110 100 101 90 91 106 107 92 102
FIGURE 1-4: TABLE 1-3:
I2C Bus Data Timing. I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in Electrical characteristics Min 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 4000 600 120 60 4700 1300 320 160 -- -- -- -- Max -- -- Units ns ns ns ns ns ns ns ns Conditions 2.7V-5.5V 2.7V-5.5V 4.5V-5.5V 4.5V-5.5V 2.7V-5.5V 2.7V-5.5V 4.5V-5.5V 4.5V-5.5V
I2C AC Characteristics
Param. No. 100
Sym THIGH
Characteristic Clock high time
101
TLOW
Clock low time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
Note 1: 2:
3:
4: 5: 6:
7: 8:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).
DS22272A-page 10
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in Electrical characteristics Min 100 kHz mode 400 kHz mode 1.7 MHz mode 1.7 MHz mode -- 20 + 0.1Cb 20 20 Max 1000 300 80 160 Units ns ns ns ns Conditions Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) After a Repeated Start condition or an Acknowledge bit After a Repeated Start condition or an Acknowledge bit Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) I2C AC Characteristics
Param. No. 102A(5)
Sym TRSCL
Characteristic SCL rise time
3.4 MHz mode 3.4 MHz mode
10 10
40 80
ns ns
102B(5)
TRSDA
SDA rise time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
-- 20 + 0.1Cb 20 10 -- 20 + 0.1Cb 20 10 -- 20 + 0.1Cb(4) 20 10
1000 300 160 80 300 300 80 40 300 300 160 80
ns ns ns ns ns ns ns ns ns ns ns ns
103A
(5)
TFSCL
SCL fall time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode)
103B
(5)
TFSDA
SDA fall time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode)
Note 1: 2:
3:
4: 5: 6:
7: 8:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).
(c) 2011 Microchip Technology Inc.
DS22272A-page 11
MCP4706/4716/4726
TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in Electrical characteristics Min 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 107 TSU:DAT Data input setup time 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 109 TAA Output valid from clock 100 kHz mode 400 kHz mode 1.7 MHz mode 0 0 0 0 250 100 10 10 -- -- -- -- 3.4 MHz mode 110 TBUF Bus free time 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode Note 1: 2: -- 4700 1300 N.A. N.A. Max -- -- -- -- -- -- -- -- 3750 1200 150 310 150 -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cb = 100 pF, Note 1, Note 7, Note 8 Cb = 400 pF, Note 1, Note 5, Note 8 Cb = 100 pF, Note 1, Note 8 Time the bus must be free before a new transmission can start Note 1, Note 8 Conditions 2.7V-5.5V, Note 6 2.7V-5.5V, Note 6 4.5V-5.5V, Note 6 4.5V-5.5V, Note 6 Note 2 I2C AC Characteristics
Param. No. 106
Sym THD:DAT
Characteristic Data input hold time
3:
4: 5: 6:
7: 8:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).
DS22272A-page 12
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in Electrical characteristics Min 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode -- 50 (typ) 10 (typ) 10 (typ) Note 1: 2: -- -- -- -- -- -- -- -- Max 50 50 10 10 -- -- -- -- Units ns ns ns ns ns ns ns ns Spike suppression Spike suppression Standard Mode, (Not Applicable) Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Conditions NXP Spec states N.A. I2C AC Characteristics
Param. No. 111
Sym TSP
Characteristic Input filter spike suppression (SDA and SCL)
3:
4: 5: 6:
7: 8:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. This parameter ensured by characterization. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. Ensured by the TAA 3.4 MHz specification test. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).
(c) 2011 Microchip Technology Inc.
DS22272A-page 13
MCP4706/4716/4726
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 6L-SOT-23 Thermal Resistance, 6L-DFN (2 x 2) Note 1: JA JA -- -- 190 91 -- -- C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Note 1 Symbol Min Typical Max Units Conditions
The MCP47X6 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150C.
DS22272A-page 14
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
12 8 4 0 -4 -8 -12 0 1024 2048 3072 4096
-40C +25C +85C +125C
12 8 4 0 -4 -8 -12 0 1024 2048 3072 4096
-40C +25C +85C +125C
INL Error (LSb)
Volatile DAC Register Code
INL Error (LSb)
Volatile DAC Register Code
FIGURE 2-1: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `00'.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
-40C +25C +85C +125C
FIGURE 2-4: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `00'.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
-40C +25C +85C +125C
INL Error (LSb)
Volatile DAC Register Code
INL Error (LSb)
Volatile DAC Register Code
FIGURE 2-2: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `00'.
1.0
-40C +25C +85C +125C
FIGURE 2-5: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `00'.
1.0
-40C +25C +85C +125C
0.5
0.5
INL Error (LSb)
0.0
INL Error (LSb)
0 32 64 96 128 160 192 224 256
0.0
-0.5
-0.5
-1.0
-1.0 0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-3: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `00'.
FIGURE 2-6: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `00'.
(c) 2011 Microchip Technology Inc.
DS22272A-page 15
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
0.4 0.3 0.2 0.4 0.3 0.2
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 3072 4096
-40C +25C +85C +125C
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 3072 4096
-40C +25C +85C +125C
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-7: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `00'.
0.3
FIGURE 2-10: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `00'.
0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3
-40C +25C +85C +125C
0.2
DNL Error (LSb)
0.0
-0.1
-40C +25C +85C +125C
-0.2
-0.3 0 128 256 384 512 640 768 896 1024
DNL Error (LSb)
0.1
0
128
256
384
512
640
768
896
1024
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-8: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `00'.
0.20 0.15 0.10
FIGURE 2-11: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `00'.
0.20 0.15 0.10
DNL Error (LSb)
0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256
-40C +25C +85C +125C
DNL Error (LSb)
0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256
-40C +25C +85C +125C
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-9: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `00'.
FIGURE 2-12: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `00'.
DS22272A-page 16
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
2.0
2.7V 5.0V 5.5V
-18.0 -20.0
Zero Scale Error (LSb)
1.5
Full Scale Error (LSb)
-22.0 -24.0 -26.0 -28.0 -30.0
2.7V 5.0V 5.5V
1.0
0.5
0.0 -40 -20 0 20 40 60 80 100 120
-32.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-13: Zero Scale Error (ZSE) vs. Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `00'.
0.5
2.7V 5.0V 5.5V
FIGURE 2-16: Full Scale Error (FSE) vs. Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `00'.
-4.0
Zero Scale Error (LSb)
0.4
Full Scale Error (LSb)
-5.0
0.3
-6.0
0.2
-7.0 0.1
2.7V 5.0V 5.5V
0.0 -40 -20 0 20 40 60 80 100 120
-8.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-14: Zero Scale Error (ZSE) vs. Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `00'.
0.20
2.7V 5.0V 5.5V
FIGURE 2-17: Full Scale Error (FSE) vs. Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `00'.
0.0
Zero Scale Error (LSb)
0.15
Full Scale Error (LSb)
-0.5
0.10
-1.0
0.05
-1.5
2.7V 5.0V 5.5V
0.00 -40 -20 0 20 40 60 80 100 120
-2.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-15: Zero Scale Error (ZSE) vs. Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `00'.
FIGURE 2-18: Full Scale Error (FSE) vs. Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `00'.
(c) 2011 Microchip Technology Inc.
DS22272A-page 17
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
12 8 4 0 -4 -8 -12 0 1024 2048 3072 4096
-40C +25C +85C +125C
12 8 4 0 -4 -8 -12 0 1024 2048 3072 4096
-40C +25C +85C +125C
INL Error (LSb)
Volatile DAC Register Code
INL Error (LSb)
Volatile DAC Register Code
FIGURE 2-19: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
-40C +25C +85C +125C
FIGURE 2-22: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
-40C +25C +85C +125C
INL Error (LSb)
Volatile DAC Register Code
INL Error (LSb)
Volatile DAC Register Code
FIGURE 2-20: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
1.0
-40C +25C +85C +125C
FIGURE 2-23: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
1.0
-40C +25C +85C +125C
0.5
0.5
INL Error (LSb)
0.0
INL Error (LSb)
0 32 64 96 128 160 192 224 256
0.0
-0.5
-0.5
-1.0
-1.0 0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-21: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
FIGURE 2-24: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
DS22272A-page 18
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
0.4 0.3 0.2 0.4 0.3 0.2
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 3072 4096
-40C +25C +85C +125C
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 3072 4096
-40C +25C +85C +125C
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-25: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
0.3
FIGURE 2-28: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3
-40C +25C +85C +125C
0.2
DNL Error (LSb)
0.0
-0.1
-40C +25C +85C +125C
-0.2
-0.3 0 128 256 384 512 640 768 896 1024
DNL Error (LSb)
0.1
0
128
256
384
512
640
768
896
1024
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-26: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
0.20 0.15 0.10
FIGURE 2-29: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
0.20 0.15 0.10
DNL Error (LSb)
0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256
-40C +25C +85C +125C
DNL Error (LSb)
0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256
-40C +25C +85C +125C
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-27: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
FIGURE 2-30: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
(c) 2011 Microchip Technology Inc.
DS22272A-page 19
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
2.0
2.7V 5.0V 5.5V
-18.0 -20.0
Zero Scale Error (LSb)
1.5
Full Scale Error (LSb)
-22.0 -24.0 -26.0 -28.0 -30.0
2.7V 5.0V 5.5V
1.0
0.5
0.0 -40 -20 0 20 40 60 80 100 120
-32.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-31: Zero Scale Error (ZSE) vs. Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
0.5
2.7V 5.0V 5.5V
FIGURE 2-34: Full Scale Error (FSE) vs. Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
-4.0
Zero Scale Error (LSb)
0.4
Full Scale Error (LSb)
-5.0
0.3
-6.0
0.2
-7.0 0.1
2.7V 5.0V 5.5V
0.0 -40 -20 0 20 40 60 80 100 120
-8.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-32: Zero Scale Error (ZSE) vs. Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
0.20
2.7V 5.0V 5.5V
FIGURE 2-35: Full Scale Error (FSE) vs. Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
0.0
Zero Scale Error (LSb)
0.15
Full Scale Error (LSb)
-0.5
0.10
-1.0
0.05
-1.5
2.7V 5.0V 5.5V
0.00 -40 -20 0 20 40 60 80 100 120
-2.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-33: Zero Scale Error (ZSE) vs. Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
FIGURE 2-36: Full Scale Error (FSE) vs. Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
DS22272A-page 20
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
12 8 4 0 -4 -8 -12 0 1024 2048 3072 4096
-40C +25C +85C +125C
12 8 4 0 -4 -8 -12 0 1024 2048 3072 4096
-40C +25C +85C +125C
INL Error (LSb)
Volatile DAC Register Code
INL Error (LSb)
Volatile DAC Register Code
FIGURE 2-37: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
-40C +25C +85C +125C
FIGURE 2-40: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
-40C +25C +85C +125C
INL Error (LSb)
Volatile DAC Register Code
INL Error (LSb)
Volatile DAC Register Code
FIGURE 2-38: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
1.0
-40C +25C +85C +125C
FIGURE 2-41: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
1.0
-40C +25C +85C +125C
0.5
0.5
INL Error (LSb)
0.0
INL Error (LSb)
0 32 64 96 128 160 192 224 256
0.0
-0.5
-0.5
-1.0
-1.0 0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-39: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
FIGURE 2-42: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
(c) 2011 Microchip Technology Inc.
DS22272A-page 21
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
0.4 0.3 0.2 0.4 0.3 0.2
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 3072 4096
-40C +25C +85C +125C
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 3072 4096
-40C +25C +85C +125C
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-43: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
0.3
FIGURE 2-46: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3
-40C +25C +85C +125C
0.2
DNL Error (LSb)
0.0
-0.1
-40C +25C +85C +125C
-0.2
-0.3 0 128 256 384 512 640 768 896 1024
DNL Error (LSb)
0.1
0
128
256
384
512
640
768
896
1024
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-44: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
0.20 0.15 0.10
FIGURE 2-47: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
0.20 0.15 0.10
DNL Error (LSb)
0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256
-40C +25C +85C +125C
DNL Error (LSb)
0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256
-40C +25C +85C +125C
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-45: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
FIGURE 2-48: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
DS22272A-page 22
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
2.0
2.7V 5.0V 5.5V
-18.0 -20.0
Zero Scale Error (LSb)
1.5
Full Scale Error (LSb)
-22.0 -24.0 -26.0 -28.0 -30.0
2.7V 5.0V 5.5V
1.0
0.5
0.0 -40 -20 0 20 40 60 80 100 120
-32.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-49: Zero Scale Error (ZSE) vs. Temperature (MCP4726). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
0.5
2.7V 5.0V 5.5V
FIGURE 2-52: Full Scale Error (FSE) vs. Temperature (MCP4726). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
-4.0
Zero Scale Error (LSb)
0.4
Full Scale Error (LSb)
-5.0
0.3
-6.0
0.2
-7.0 0.1
2.7V 5.0V 5.5V
0.0 -40 -20 0 20 40 60 80 100 120
-8.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-50: Zero Scale Error (ZSE) vs. Temperature (MCP4716). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
0.20
2.7V 5.0V 5.5V
FIGURE 2-53: Full Scale Error (FSE) vs. Temperature (MCP4716). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
0.0
Zero Scale Error (LSb)
0.15
Full Scale Error (LSb)
-0.5
0.10
-1.0
0.05
-1.5
2.7V 5.0V 5.5V
0.00 -40 -20 0 20 40 60 80 100 120
-2.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-51: Zero Scale Error (ZSE) vs. Temperature (MCP4706). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
FIGURE 2-54: Full Scale Error (FSE) vs. Temperature (MCP4706). VDD = 2.7V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
(c) 2011 Microchip Technology Inc.
DS22272A-page 23
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
16 12 8 4 0 -4 -8 0 1024 2048 3072 4096
2.7V 5.0V 5.5V
0.5 0.4 0.3 0.2
INL Error (LSb)
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1024 2048 3072 4096
2.7V 5.0V 5.5V
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-55: INL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = `10', G = `1', VREF = VDD/2, Temp = +25C.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
2.7V 5.0V 5.5V
FIGURE 2-58: DNL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = `10', G = `1', VREF = VDD/2, Temp = +25C.
0.4 0.3 0.2
INL Error (LSb)
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024
2.7V 5.0V 5.5V
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-56: INL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = `10', G = `1', VREF = VDD/2, Temp = +25C.
1.0
2.7V 5.0V 5.5V
FIGURE 2-59: DNL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = `10', G = `1', VREF = VDD/2, Temp = +25C.
0.30 0.25 0.20 0.15
0.5
INL Error (LSb)
DNL Error (LSb)
0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25
2.7V 5.0V 5.5V
0.0
-0.5
-1.0 0 32 64 96 128 160 192 224 256
-0.30 0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-57: INL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = `10', G = `1', VREF = VDD/2, Temp = +25C.
FIGURE 2-60: DNL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = `10', G = `1', VREF = VDD/2, Temp = +25C.
DS22272A-page 24
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
16 12 8 4 0 -4 -8 0 1024 2048 3072 4096
2.7V 5.0V 5.5V
0.5 0.4 0.3 0.2
INL Error (LSb)
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1024 2048 3072 4096
2.7V 5.0V 5.5V
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-61: INL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = `11', G = `1', VREF = VDD/2, Temp = +25C.
3 2 1 0 -1 -2 -3 0 128 256 384 512 640 768 896 1024
2.7V 5.0V 5.5V
FIGURE 2-64: DNL vs. Code (code = 100 to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726). VREF1:VREF0 = `11', G = `1', VREF = VDD/2, Temp = +25C.
0.4 0.3 0.2
INL Error (LSb)
DNL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024
2.7V 5.0V 5.5V
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-62: INL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = `11', G = `1', VREF = VDD/2, Temp = +25C.
1.0
2.7V 5.0V 5.5V
FIGURE 2-65: DNL vs. Code (code = 25 to 1000) and VDD (2.7V, 5V, 5.5V) (MCP4716). VREF1:VREF0 = `11', G = `1', VREF = VDD/2, Temp = +25C.
0.30 0.25 0.20
0.5
0.15
INL Error (LSb)
DNL Error (LSb)
0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25
2.7V 5.0V 5.5V
0.0
-0.5
-1.0 0 32 64 96 128 160 192 224 256
-0.30 0 32 64 96 128 160 192 224 256
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-63: INL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = `11', G = `1', VREF = VDD/2, Temp = +25C.
FIGURE 2-66: DNL vs. Code (code = 6 to 250) and VDD (2.7V, 5V, 5.5V) (MCP4706). VREF1:VREF0 = `11', G = `1', VREF = VDD/2, Temp = +25C.
(c) 2011 Microchip Technology Inc.
DS22272A-page 25
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
16 12 8 4 0 -4 -8 0 1024 2048 3072 4096 -1.0 0 1024 2048 3072 4096
1V 2V 3V 4V 5V
1.0
1V 4V
2V 5V
3V
0.5
INL Error (LSb)
DNL Error (LSb) Volatile DAC Register Code
0.0
-0.5
Volatile DAC Register Code
FIGURE 2-67: INL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
4
1V 2V 3V 4V 5V
FIGURE 2-70: DNL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
0.5 0.4 0.3 0.2
1V 4V 2V 5V 3V
3
DNL Error (LSb)
INL Error (LSb)
2
0.1 0.0 -0.1 -0.2 -0.3 -0.4
1
0
-1
-2 0 128 256 384 512 640 768 896 1024
-0.5 0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-68: INL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
1.0
FIGURE 2-71: DNL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
0.5 0.4 0.3
1V 4V 2V 5V 3V
0.5
0.2
DNL Error (LSb)
1V 2V 3V 4V 5V
INL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5
0.0
-0.5
-1.0 0 32 64 96 128 160 192 224 256
0
32
64
96
128
160
192
224
256
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-69: INL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
FIGURE 2-72: DNL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = `10', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
DS22272A-page 26
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
16 12 8 4 0 -4 -8 0 1024 2048 3072 4096 -1.0 0 1024 2048 3072 4096
1V 2V 3V 4V 5V
1.0
1V 4V
2V 5V
3V
0.5
INL Error (LSb)
DNL Error (LSb) Volatile DAC Register Code
0.0
-0.5
Volatile DAC Register Code
FIGURE 2-73: INL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
4
1V 2V 3V 4V 5V
FIGURE 2-76: DNL vs. Code (code = 100 to 4000) and VREF (MCP4726). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
0.5 0.4 0.3 0.2
1V 4V 2V 5V 3V
3
DNL Error (LSb)
INL Error (LSb)
2
0.1 0.0 -0.1 -0.2 -0.3 -0.4
1
0
-1
-2 0 128 256 384 512 640 768 896 1024
-0.5 0 128 256 384 512 640 768 896 1024
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-74: INL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
1.0
FIGURE 2-77: DNL vs. Code (code = 25 to 1000) and VREF (MCP4716). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
0.5 0.4 0.3
1V 4V 2V 5V 3V
0.5
0.2
DNL Error (LSb)
1V 2V 3V 4V 5V
INL Error (LSb)
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5
0.0
-0.5
-1.0 0 32 64 96 128 160 192 224 256
0
32
64
96
128
160
192
224
256
Volatile DAC Register Code
Volatile DAC Register Code
FIGURE 2-75: INL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
FIGURE 2-78: DNL vs. Code (code = 6 to 250) and VREF (MCP4706). VDD = 5V, VREF1:VREF0 = `11', G = `0', VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25C.
(c) 2011 Microchip Technology Inc.
DS22272A-page 27
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
-20.0 -22.0
2.7V 5.0V 5.5V
-20.0 -22.0
2.7V 5.0V 5.5V
Output Error (LSb)
-24.0 -26.0 -28.0 -30.0 -32.0 -34.0 -36.0 -40 -20 0 20 40 60 80 100 120
Output Error (LSb)
-24.0 -26.0 -28.0 -30.0 -32.0 -34.0 -36.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-79: Output Error vs. Temperature (MCP4726). VDD = 2.7V and 5V, VREF1:VREF0 = `00', Code = 4000.
FIGURE 2-82: Output Error vs. Temperature (MCP4726). VDD = 2.7V and 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD, Code = 4000.
-4.0
2.7V 5.0V 5.5V
-4.0
2.7V 5.0V 5.5V
Output Error (LSb)
Output Error (LSb)
-5.0
-5.0
-6.0
-6.0
-7.0
-7.0
-8.0 -40 -20 0 20 40 60 80 100 120
-8.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-80: Output Error vs. Temperature (MCP4716). VDD = 2.7V and 5V, VREF1:VREF0 = `00', Code = 1000.
FIGURE 2-83: Output Error vs. Temperature (MCP4716). VDD = 2.7V and 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD, Code = 1000.
-0.4
2.7V 5.0V 5.5V
-0.4
2.7V 5.0V 5.5V
Output Error (LSb)
Output Error (LSb)
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
-1.2
-1.2
-1.4 -40 -20 0 20 40 60 80 100 120
-1.4 -40 -20 0 20 40 60 80 100 120
Temperature (C)
Temperature (C)
FIGURE 2-81: Output Error vs. Temperature (MCP4706). VDD = 2.7V and 5V, VREF1:VREF0 = `00', Code = 250.
FIGURE 2-84: Output Error vs. Temperature (MCP4706). VDD = 2.7V and 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD, Code = 250.
DS22272A-page 28
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
-20.0 -22.0
2.7V 5.0V 5.5V
Output Error (LSb)
-24.0 -26.0 -28.0 -30.0 -32.0 -34.0 -36.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
FIGURE 2-85: Output Error vs. Temperature (MCP4726). VDD = 2.7V and 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD, Code = 4000.
-4.0
2.7V 5.0V 5.5V
Output Error (LSb)
-5.0
-6.0
-7.0
-8.0 -40 -20 0 20 40 60 80 100 120
Temperature (C)
FIGURE 2-86: Output Error vs. Temperature (MCP4716). VDD = 2.7V and 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD, Code = 1000.
-0.4
2.7V 5.0V 5.5V
-0.6
Output Error (LSb)
-0.8
-1.0
-1.2
-1.4 -40 -20 0 20 40 60 80 100 120
Temperature (C)
FIGURE 2-87: Output Error vs. Temperature (MCP4706). VDD = 2.7V and 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD, Code = 250.
(c) 2011 Microchip Technology Inc.
DS22272A-page 29
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
250 225 200 IDD (uA) IPowerDown (nA) 300 175 150 125 100 -40 -20 0 20 40 60 80 100 120 Temperature (C)
2.7V 3.3V 4.5V 5.0V 5.5V
500
2.7V 3.3V 4.5V 5.0V 5.5V
400
200
100
0 -40 -20 0 20 40 60 80 100 120 Temperature (C)
FIGURE 2-88: IDD vs. Temperature. VDD = 2.7V and 5V, VREF1:VREF0 = `00'.
250 225 200 IDD (uA) 175 150 125 100 -40 -20 0 20 40 60 80 100 120 Temperature (C)
2.7V 3.3V 4.5V 5.0V 5.5V
FIGURE 2-91: Powerdown Current vs. Temperature. VDD = 2.7V, 3.3V, 4.5V, 5.0V and 5.5V, PD1:PD0 = `11'.
FIGURE 2-89: IDD vs. Temperature. VDD = 2.7V and 5V, VREF1:VREF0 = `10', G = `0', VREF = VDD.
250 225 200 IDD (uA) 175 150 125 100 -40 -20 0 20 40 60 80 100 120 Temperature (C)
2.7V 3.3V 4.5V 5.0V 5.5V
FIGURE 2-90: IDD vs. Temperature. VDD = 2.7V and 5V, VREF1:VREF0 = `11', G = `0', VREF = VDD.
DS22272A-page 30
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
70
2.7V 5.0V 5.5V
6
Code = FFFh
5 VOUT (V) 4 3 2 1
65 VIH (% VDD)
60
55
50 -40 -20 0 20 40 60 80 100 120 Temperature (C)
0 0 1000 2000 3000 4000 Load Resistance (RL) (:) 5000
FIGURE 2-92: VIH Threshold of SDA/SCL Inputs vs. Temperature and VDD.
50
2.7V 5.0V 5.5V
FIGURE 2-94: VDD = 5.0V.
6
VOUT vs. Resistive Load.
Code = FFFh
Code = 000h
5 4 VOUT (V)
45 VIL (% VDD)
40
3 2
35
1
30 -40 -20 0 20 40 60 80 100 120 Temperature (C)
0 0 3 6 9 ISOURCE/SINK (mA) 12 15
FIGURE 2-93: VIL Threshold of SDA/SCL Inputs vs. Temperature and VDD.
FIGURE 2-95: VOUT vs. Source / Sink Current. VDD = 5.0V.
(c) 2011 Microchip Technology Inc.
DS22272A-page 31
MCP4706/4716/4726
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V, VREF = Internal, Gain = x1, RL = 5 k, CL = 100 pF.
FIGURE 2-96: Full-Scale Settling Time (000h to FFFh) (MCP4726).
FIGURE 2-98: Half-Scale Settling Time (400h to C00h) (MCP4726).
FIGURE 2-97: Full-Scale Settling Time (FFFh to 000h) (MCP4726).
FIGURE 2-99: Half-Scale Settling Time (C00h to 400h) (MCP4726).
FIGURE 2-100: Exiting Power Down Mode (MCP4726, Volatile DAC Register = FFFh).
DS22272A-page 32
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
3.0 PIN DESCRIPTIONS
An overview of the pin functions are described in Section 3.1 through Section 3.7. The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP47X6 PINOUT DESCRIPTION
Pin
SOT-23 6L 1 2 3 4 5 6 -- Legend:
DFN Symbol 6L 6 5 4 3 2 1 7 VOUT VSS VDD SDA SCL VREF EP A = Analog pins O = Digital output P = Power A -- -- I/O I A -- I/O
Buffer Type Analog P P ST ST Analog --
Standard Function
Buffered analog voltage output pin Ground reference pin for all circuitries on the device Supply Voltage Pin I2C Serial Data Pin I2C Serial Clock Pin Voltage Reference Input Pin Exposed Pad Note 1 I = Digital input (high Z) I/O = Input / Output
Note 1:
The DFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device's VSS pin.
(c) 2011 Microchip Technology Inc.
DS22272A-page 33
MCP4706/4716/4726
3.1 Analog Output Voltage Pin (VOUT) 3.4 Serial Data Pin (SDA)
VOUT is the DAC analog output pin. The DAC output has an output amplifier. VOUT can swing from approximately 0V to approximately VDD. The full-scale range of the DAC output is from VSS to G * VRL, where G is the gain selection option (1x or 2x). In normal mode, the DC impedance of the output pin is about 1. In Power-Down mode, the output pin is internally connected to a known pull-down resistor of 1 k, 125 k, or 640 k. The Power-Down selection bits settings are shown Table 4-2. SDA is the serial data pin of the I2C interface. The SDA pin is used to write or read the DAC registers and configuration bits. The SDA pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Except for start and stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.0 "I2C Serial Interface" for more details of I2C Serial Interface communication.
3.2
Positive Power Supply Input (VDD)
3.5
Serial Clock Pin (SCL)
VDD is the positive supply voltage input pin. The input supply voltage is relative to VSS. The power supply at the VDD pin should be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 F (ceramic) to ground. An additional 10 F capacitor (tantalum) in parallel is also recommended to further attenuate high-frequency noise present in application boards.
SCL is the serial clock pin of the I2C interface. The MCP47X6 devices act only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the device occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL pin. Refer to Section 5.0 "I2C Serial Interface" for more details of I2C Serial Interface communication.
3.3
Ground (VSS) 3.6 Voltage Reference Pin (VREF)
This pin is used for the external voltage reference input. The user can select VDD voltage or the VREF pin voltage as the reference resistor ladder's voltage reference. When the VREF pin signal is selected, there is an option for this voltage to be buffered or unbuffered. This is offered in cases where the reference voltage does not have the current capability not to drop its voltage when connected to the internal resistor ladder circuit. When the VDD is selected as reference voltage, this pin is disconnected from the internal circuit. See Section 4.2 "DAC's (Resistor Ladder) Reference Voltage" and Table 4-4 for more details on the configuration bits.
The VSS pin is the device ground reference. The user must connect the VSS pin to a ground plane through a low-impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board.
3.7
Exposed Pad (EP)
This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink.
DS22272A-page 34
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
4.0 GENERAL DESCRIPTION
4.1
The MCP4706, MCP4716, and MCP4726 devices are single channel voltage output 8-bit, 10-bit, and 12-bit DAC devices with nonvolatile memory (EEPROM) and an I2C serial interface. This family will be referred to as MCP47X6. The devices use a resistor ladder architecture. The resistor ladder DAC is driven from a software selectable voltage reference source. The source can be either the device's internal VDD or the external VREF pin voltage. The DAC output is buffered with a low power and precision output amplifier (op amp). This output amplifier provides a rail-to-rail output with low offset voltage and low noise. The gain of the output buffer is software configurable. This device also has user programmable nonvolatile memory (EEPROM), which allows the user to save the desired POR/BOR value of the DAC register and device configuration bits. The devices use a two-wire I2C serial communication interface and operate with a single supply voltage from 2.7V to 5.5V.
Power-On-Reset / Brown Out Reset (POR/BOR)
The internal Power-On-Reset (POR) / Brown-Out Reset (BOR) circuit monitors the power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. VRAM is the RAM retention voltage and is always lower than the POR trip point voltage. POR occurs as the voltage is rising (typically from 0V), while BOR occurs as the voltage is falling (typically from VDD(MIN) or higher). When the rising VDD voltage crosses the VPOR trip point, the following occurs: * Nonvolatile DAC Register value latched into volatile DAC Register * Nonvolatile configuration bit values latched into volatile configuration bits * POR status bit is set ("1") * The reset delay timer starts; when timer times out (tPORD), the I2C interface is operational. The analog output (VOUT) state will be determined by the state of the volatile configuration bits and the DAC Register. This is called a POR reset (event). When the falling VDD voltage crosses the VPOR trip point, the following occurs: * Device is forced into a power down state (PD1:PD0 = `11'). Analog circuitry is turned off. * Volatile DAC Register is forced to 000h * Volatile configuration bits VREF1, VREF0 and G are forced to `0' Figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions.
Volatile memory POR starts Reset Delay Timer. retains data value When timer times out, I2C interface can operate (if VDD >= VDD(MIN)) VDD(MIN) VPOR VRAM TPORD (60 s max.) Normal Operation Device in unknown state Device in POR state EEPROM data latched into volatile configuration bits and DAC register. POR status bit is set ("1")
Volatile memory becomes corrupted
VBOR
Below minimum operating voltage
Device Device in in power unknown down state state
POR reset forced active
BOR reset, volatile DAC Register = 000h volatile VREF1:VREF0 = 00 volatile G = 0 volatile PD1:PD0 = 11
FIGURE 4-1:
Power-On-Reset Operation.
(c) 2011 Microchip Technology Inc.
DS22272A-page 35
MCP4706/4716/4726
4.2 DAC's (Resistor Ladder) Reference Voltage 4.3 Resistor Ladder
The resistor ladder is a digital potentiometer with the B Terminal internally grounded and the A terminal connected to the selected reference voltage (see Figure 4-3). The volatile DAC register controls the wiper position. The wiper voltage (VW) is proportional to the DAC register value divided by the number of resistor elements (RS) in the ladder (256, 1024, or 4096) related to the VRL voltage. Note: The maximum wiper position is 2n - 1, while the number of resistors in the resistor ladder is 2n. This means that when the DAC register is at full scale, there is one resistor element (RS) between the wiper and the VRL voltage.
The device can be configured to use one of three voltage sources for the resistor ladder's reference voltage (VRL) (see Figure 4-2). These are: 1. 2. 3. VDD pin voltage VREF pin voltage internally buffered VREF pin voltage unbuffered
The selection of the voltage is specified with the volatile VREF1:VREF0 configuration bits (see Table 4-4). There are nonvolatile and volatile VREF1:VREF0 configuration bits. On a POR/BOR event, the state of the nonvolatile VREF1:VREF0 configuration bits are latched into the volatile VREF1:VREF0 configuration bits. When the user selects the VDD as reference, the VREF pin voltage is not connected to the resistor ladder. If the VREF pin is selected, then one needs to select between the buffered or unbuffered mode. In unbuffered mode, the VREF pin voltage may be from VSS to VDD. Note: In unbuffered mode, the voltage source should have a low output impedance. If the voltage source has a high output impedance, then the voltage on the VREF's pin would be lower than expected. The resistor ladder has a typical impedance of 210 k and a typical capacitance of 29 pF.
The resistor ladder (RRL) has a typical impedance of approximately 210 k. This resistor ladder resistance (RRL) may vary from device to device up to 20%. Since this is a voltage divider configuration, the actual RRL resistance does not effect the output given a fixed voltage at VRL. If the unbuffered VREF pin is used as the VRL voltage source, this voltage source should have a low output impedance. When the DAC is powered down, the resistor ladder is disconnected from the selected reference voltage. VRL DAC Register
PD1:PD0 RS(2n)
In buffered mode, the VREF pin voltage may be from 0.01V to VDD-0.04V. The input buffer (amplifier) provides low offset voltage, low noise, and a very high input impedance, with only minor limitations on the input range and frequency response. Note: Any variation or noises on the reference source can directly affect the DAC output. The reference voltage needs to be as clean as possible for accurate DAC performance. VREF1:VREF0 VDD Reference Selection
2n - 1 RS(2n - 1) 2n - 2 RRL RS(2n - 2) VW 1 RS(1)
VREF
VRL
0
Buffer
FIGURE 4-2: Resistor Ladder Reference Voltage Selection Block Diagram.
VW =
DAC Register Value * VRL # Resistors in Resistor Ladder
Where: # Resistors in Resistor Ladder = 256 (MCP4706) 1024 (MCP4716) 4096 (MCP4726)
FIGURE 4-3:
Resistor Ladder.
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4.4 Output Buffer / VOUT Operation
4.4.2 OUTPUT VOLTAGE
The DAC output is buffered with a low power and precision output amplifier (op amp). Figure 4-4 shows a block diagram. This amplifier provides a rail-to-rail output with low offset voltage and low noise. The user can select the output gain of the output amplifier. Gain options are: a) b) Gain of 1, with either VDD or VREF pin used as reference voltage Gain of 2, only when VREF pin is used as reference voltage. The VREF pin voltage should be limited to VDD/2. The volatile DAC Register's value controls the analog VOUT voltage, along with the device's five configuration bits. The volatile DAC Register's value is unsigned binary. The formula for the output voltage is given in Equation 4-1. Table 4-1 shows examples of volatile DAC Register values and the corresponding theoretical VOUT voltage for the MCP47X6 devices. Note: When Gain = 2 (VRL = VREF), if VREF > VDD / 2, the VOUT voltage will be limited to VDD. So if VREF = VDD, then the VOUT voltage will not change for volatile DAC Register values mid-scale and greater, since the op amp at full scale output.
The amplifier's output can drive the resistive and high capacitive loads without oscillation. The amplifier provides a maximum load current which is enough for most programmable voltage reference applications. Refer to Section 1.0 "Electrical Characteristics" for the specifications of the output amplifier. Note: The load resistance must keep higher than 5 k for the stable and expected analog output (to meet electrical specifications).
EQUATION 4-1:
CALCULATING OUTPUT VOLTAGE (VOUT)
VOUT =
VRL * DAC Register Value * Gain # Resistors in Resistor Ladder
In any of the three Power-Down modes, the op amp is powered down and it's output becomes a high impedance to the VOUT pin. Gain (1x or 2x) (G = 0 or 1)
# Resistors in Resistor Ladder = 4096 (MCP4726) 1024 (MCP4716) 256 (MCP4706) The DAC register value will be latched on the falling edge of the acknowledge pulse of the write command's last byte. Then the VOUT voltage will start driving to the new value. The following events update the analog voltage output (VOUT):
VW
Op Amp
VOUT
FIGURE 4-4: Diagram. 4.4.1
Output Buffer Block
* Power-On-Reset or General Call Reset command: Output is updated with EEPROM data. * Falling edge of the acknowledge pulse of the last write command byte.
4.4.2.1
Resolution / Step Voltage
PROGRAMMABLE GAIN
The amplifier's gain is controlled by the Gain (G) configuration bit (See Table 4-4) and the VRL reference selection. When the VRL reference selection is the device's VDD voltage, the G bit is ignored and a gain of 1 is used. The volatile G bit value can be modified by: * * * * POR event BOR event I2C write commands I2C General Call Reset command
The Step voltage is dependent on the device resolution and the output voltage range. One LSb is defined as the ideal voltage difference between two successive codes. The step voltage can easily be calculated by using Equation 4-1 where the DAC Register Value is equal to 1.
4.4.3
DRIVING RESISTIVE AND CAPACITIVE LOADS
The VOUT pin can drive up to 100 pF of capacitive load in parallel with a 5 k resistive load (to meet electrical specifications). Figure 2-57 shows the VOUT vs. Resistive Load. VOUT drops slowly as the load resistance decreases after about 3.5 k. It is recommended to use a load with RL greater than 5 k.
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TABLE 4-1:
Device
DAC INPUT CODE VS. ANALOG OUTPUT (VOUT) (VDD = 5.0V)
Volatile DAC Register Value LSb VRL
(1)
Gain Selection uV 1,220.7 610.4 1,220.7 610.4 1,220.7 610.4 1,220.7 610.4 4,882.8 2,441.4 4,882.8 2,441.4 4,882.8 2,441.4 4,882.8 2,441.4 19,531.3 9,765.6 19,531.3 9,765.6 19,531.3 9,765.6 19,531.3 9,765.6
(2)
VOUT (4) Equation VRL * (4095/4096) * 1 VRL * (4095/4096) * 1 VRL * (4095/4096) * 2) VRL * (2047/4096) * 1) VRL * (2047/4096) * 1) VRL * (2047/4096) * 2) VRL * (1023/4096) * 1) VRL * (1023/4096) * 1) VRL * (1023/4096) * 2) VRL * (0/4096) * 1) VRL * (0/4096) * 1) VRL * (0/4096) * 2) VRL * (1023/1024) * 1 VRL * (1023/1024) * 1 VRL * (1023/1024) * 2 VRL * (511/1024) * 1 VRL * (511/1024) * 1 VRL * (511/1024) * 2 VRL * (255/1024) * 1 VRL * (255/1024) * 1 VRL * (255/1024) * 2 VRL * (0/1024) * 1 VRL * (0/1024) * 1 VRL * (0/1024) * 1 VRL * (255/256) * 1 VRL * (255/256) * 1 VRL * (255/256) * 2 VRL * (127/256) * 1 VRL * (127/256) * 1 VRL * (127/256) * 2 VRL * (63/256) * 1 VRL * (63/256) * 1 VRL * (63/256) * 2 VRL * (0/256) * 1 VRL * (0/256) * 1 VRL * (0/256) * 2 V 4.998779 2.499390 4.998779 2.498779 1.249390 2.498779 1.248779 0.624390 1.248779 0 0 0 4.995117 2.497559 4.995117 2.495117 1.247559 2.495117 1.245117 0.622559 1.245117 0 0 0 4.980469 2.490234 4.980469 2.480469 1.240234 2.480469 1.230469 0.615234 1.230469 0 0 0
Equation 5.0V/4096 2.5V/4096 5.0V/4096 2.5V/4096 5.0V/4096 2.5V/4096 5.0V/4096 2.5V/4096 5.0V/1024 2.5V/1024 5.0V/1024 2.5V/1024 5.0V/1024 2.5V/1024 5.0V/1024 2.5V/1024 5.0V/256 2.5V/256 5.0V/256 2.5V/256 5.0V/256 2.5V/256 5.0V/256 2.5V/256
5.0V 1111 1111 1111 2.5V 5.0V 0111 1111 1111 MCP4726 (12-bit) 0011 1111 1111 2.5V 5.0V 2.5V 5.0V 0000 0000 0000 2.5V 5.0V 11 1111 1111 2.5V 5.0V 01 1111 1111 MCP4716 (10-bit) 00 1111 1111 2.5V 5.0V 2.5V 5.0V 00 0000 0000 2.5V 5.0V 1111 1111 2.5V 5.0V 0111 1111 MCP4706 (8-bit) 0011 1111 2.5V 5.0V 2.5V 5.0V 0000 0000 Note 1: 2: 3: 4: 2.5V
1x 1x 2x
(3)
1x 1x 2x(3) 1x 1x 2x
(3)
1x 1x 2x(3) 1x 1x 2x(3) 1x 1x 2x(3) 1x 1x 2x(3) 1x 1x 2x(3) 1x 1x 2x(3) 1x 1x 2x(3) 1x 1x 2x(3) 1x 1x 2x(3)
VRL is the resistor ladder's reference voltage. It is independent of VREF1:VREF0 selection. Gain selection of 2x requires voltage reference source to come from VREF pin and requires VREF pin voltage VDD / 2. Requires G = `1', VREF1:VREF0 = `10' or `11', and VRL VDD / 2. These theoretical calculations do not take into account the offset and gain errors.
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4.5 Power-Down Operation
Gain (1x or 2x) (Gx = 0 or 1) VOUT To allow the application to conserve power when the DAC operation is not required, three power down modes are available. The Power-Down configuration bits (PD1:PD0) control the power down operation (Figure 4-5). All power down modes do the following: * Turning off most of its internal circuits (op amp, resistor ladder, ...) * Op amp output becomes high impedance to the VOUT pin * Disconnects resistor ladder from reference voltage (VRL) * Retains the value of the volatile DAC register and configuration bits, and the nonvolatile (EEPROM) DAC register and configuration bits Depending on the selected power down mode, the following will occur: * VOUT pin is switched to one of three resistive pull downs (See Table 4-2) - 640k (typical) - 125k (typical) - 1k (typical) There is a delay (TPDE) between the PD1:PD0 bits changing from `00' to either `01', `10', or `11' and the op amp no longer driving the VOUT output and the pull down resistors are sinking current. In any of the power down modes, where the VOUT pin is not externally connected (sinking or sourcing current), the power down current will typical be 60 nA (see Section 1.0 "Electrical Characteristics"). Section 6.0 "MCP47X6 I2C Commands" describes the I2C commands for writing the power-down bits. The commands that can update the volatile PD1:PD0 bits are: * * * * * * Write Volatile DAC Register Write Volatile Memory Write All Memory Write Volatile Configuration bits General Call Reset General Call Wake-up Note: The I2C serial interface circuit is not affected by the Power-Down mode. This circuit remains active in order to receive any command that might come from the I2C master device. VW
Op Amp
PD1:PD0 125 k 640 k
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FIGURE 4-5: Diagram. 4.5.1
Op Amp to VOUT Pin Block
EXITING POWER-DOWN
When the device exits the power down mode the following occurs: * Disabled circuits (op amp, resistor ladder, ...) are turned on * Resistor ladder is connected to selected reference voltage (VRL) * Selected pull down resistor is disconnected * The VOUT output will be driven to the voltage represented by the volatile DAC Register's value and configuration bits The VOUT output signal will require time as these circuits are powered up and the output voltage is driven to the specified value as determined by the volatile DAC register and configuration bits. Note: Since the op amp and resistor ladder were powered off (0V), the op amp's input voltage (VW) can be considered 0V. There is a delay (TPDD) between the PD1:PD0 bits updated to `00' and the op amp driving the VOUT output. The op amp's settling time (from 0V) needs to be taken into account to ensure the VOUT voltage reflects the selected value.
The following events will change the PD1:PD0 bits to `00' and therefore exit the Power-Down mode. These are: * Any I2C write command for where the PD1:PD0 bits are `00'. * I2C General Call Wake-up Command. * I2C General Call Reset Command. (if nonvolatile PD1:PD0 bits are `00').
TABLE 4-2:
PD1 0 0 1 1 PD0 0 1 0 1
POWER-DOWN BITS AND OUTPUT RESISTIVE LOAD
Function Normal operation 1 k resistor to ground 125 k resistor to ground 640 k resistor to ground
(c) 2011 Microchip Technology Inc.
1 k
MCP4706/4716/4726
4.6 Device Resets 4.7
Device Resets can be grouped into two types. Resets due to change in voltage (POR/BOR Reset), and resets caused by the system master (such as a microcontroller). After a device reset, and when VDD VDD(MIN), the device memory may be written or read.
DAC Registers, Configuration Bits, and Status Bits
The MCP47X6 devices have both volatile and nonvolatile (EEPROM) memory. Figure 4-6 shows the volatile and nonvolatile memory and their interaction due to a POR event. There are five configuration bits in both the volatile and nonvolatile memory, the DAC registers in both the volatile and nonvolatile memory, and two volatile status bits. The DAC registers (volatile and nonvolatile) will be either 12-bits (MCP4726), 10-bits (MCP4716), or 8-bits (MCP4706) wide. When the device is first powered up, it automatically uploads the EEPROM memory values to the volatile memory. The volatile memory determines the analog output (VOUT) pin voltage. After the device is powered up, the user can update the device memory. The I2C interface is how this memory is read and written. Refer to Section 5.0 "I2C Serial Interface" and Section 6.0 "MCP47X6 I2C Commands" for more details on the reading and writing the device's memory. When the nonvolatile memory is written (using the I2C Write All Memory command), the volatile memory is written with the same values. The device starts writing the EEPROM cell at the acknowledge pulse of the EEPROM write command. Table 4-3 shows the operation of the device status bits, Table 4-4 shows the operation of the device configuration bits, and Table 4-5 shows the factory default value of a POR/BOR event for the device configuration bits. There are two Status bits. These are only in volatile memory and give indication on the status of the device. The POR bit indicates if the device VDD is above or below the POR trip point. During normal operation, this bit should be `1'. The RDY/BSY bit indicates if an EEPROM write cycle is in progress. While the RDY/ BSY bit is low (during the EEPROM writing), all commands are ignored, except for the Read Command command. DAC Register Value (1)
4.6.1
POR/BOR RESET OPERATION
The POR and BOR trip points are at the same voltage, and is determined if the VDD voltage is rising or falling (see Figure 4-1). What occurs is different depending if the reset is a POR or BOR reset.
POR Reset (VDD Rising)
On a POR Reset, the nonvolatile memory values (DAC Register and Configuration bits) are latched into the volatile memory. This configures the analog output (VOUT) circuitry. Also a reset delay timer starts. During this delay time, the I2C interface will not accept commands.
BOR Reset (VDD Falling)
On a BOR Reset, the device is forced into a power down state. The volatile PD1:PD0 bits forced to `11' and all other volatile memory forced to `0'. The I2C interface will not accept commands.
4.6.2
RESET COMMANDS
When the MCP47X6 is in the valid operating voltage, the I2C General Call Reset command will force a reset event. This is similar to the POR reset, except that the reset delay timer is not started. In the case where the I Interface bus does not seem to be responsive, the technique shown in Section 8.9, Software I2C Interface Reset Sequence can be used to force the I2C interface to be reset.
2C
Config Bits VREF1 VREF0 PD1 PD0 G Status Bits (2) VREF1 VREF0 PD1 PD0 G RDY/BSY POR DMAX DMAX
D1
D0
N.V. Memory POR Event
D1
D0
Vol. Memory
Note 1: The DMAX value depends on the device. For the MCP4706: DMAX = D7, MCP4716: DMAX = D9, and the MCP4726: DMAX = D11. 2: Status bits are read only
FIGURE 4-6:
DAC Memory and POR Interaction.
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TABLE 4-3:
Name RDY/BSY
STATUS BITS OPERATION
Function This bit indicates the state of the EEPROM program memory 1 = EEPROM is not in a programming cycle 0 = EEPROM is in a programming cycle Power-On-Reset status indicator (flag) 1 = Device is powered on with VDD > VPOR. Ensure that VDD is above VDD(MIN) to ensure proper operation. 0 = Device is in powered off state. If this value is read, VDD < VDD(MIN) < VPOR. Unreliable device operation should be expected.
POR
TABLE 4-4:
Name VREF1:VREF0
CONFIGURATION BITS
Function Resistor Ladder Voltage Reference (VRL) selection bits 0x = VDD (Unbuffered) 10 = VREF pin (Unbuffered) 11 = VREF pin (Buffered) Power-Down selection bits When the DAC is powered down, most of the internal circuits are powered off and the op amp is disconnected from the VOUT pin. 00 = Not Powered Down (Normal operation) 01 = Powered Down - VOUT is loaded with 1 k resistor to ground. 10 = Powered Down - VOUT is loaded with 100 k resistor to ground. 11 = Powered Down - VOUT is loaded with 500 k resistor to ground. Note: See Table 4-2 and Figure 4-5 for more details. Gain selection bit 0 = 1x (gain of 1) 1 = 2x (gain of 2). Not applicable when VDD is used as VRL Note: If VREF = VDD, the device uses a gain of 1 only, regardless of the gain selection bit (G) setting.
PD1:PD0
G
TABLE 4-5:
CONFIGURATION BIT VALUES AFTER POR/BOR EVENT
R/W R/W VREF0 0
(1)
R/W PD1 0
(1)
R/W PD0 0
(1)
R/W G 0(1) 0
Comment
Bit Name POR Event BOR Event Note 1:
VREF1 0
(1)
When VDD transitions from VDD < VPOR to VDD > VPOR When VDD transitions from VDD > VBOR to VDD < VBOR
0
0
1
1
Default configuration when the device is shipped to customer. The POR/BOR value may be modified by writing the corresponding nonvolatile configuration bit.
REGISTER 4-1:
DAC REGISTER BITS
R/W --(2)
(2)
R/W --(2) --(2) D10 0(1)
R/W --(2) D9 D9 0(1)
R/W --(2) D8 D8 0(1)
R/W D7 D7 D7 0(1)
R/W D6 D6 D6 0(1)
R/W D5 D5 D5 0(1)
R/W D4 D4 D4 0(1)
R/W D3 D3 D3 0(1)
R/W D2 D2 D2 0(1)
R/W D1 D1 D1 0(1)
R/W Comment D0 D0 D0 0(1) MCP4706 MCP4716 MCP4726
Bit Name POR/BOR Event Note 1: 2:
-- 0
D11
(1)
Default configuration when the device is shipped to customer. The POR/BOR value may be modified by writing the corresponding nonvolatile configuration bit. This device does not implement this bit, so there is no corresponding POR/BOR value.
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NOTES:
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5.0 I2C SERIAL INTERFACE
5.2 Signal Descriptions
The MCP47X6 devices support the I2C serial protocol. The MCP47X6 I2C's module operates in Slave mode (does not generate the serial clock). The I2C interface uses up to two pins (signals). These are: * SDA (Serial Data) * SCL (Serial Clock)
5.1
2
Overview
5.2.1 SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the device. The value on this pin is latched on the rising edge of the SCL signal when the signal is an input. With the exception of the START and STOP conditions, the high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. During the high period of the clock, the SDA pin's value (high or low) must be stable. Changes in the SDA pin's value while the SCL pin is HIGH will be interpreted as a START or a STOP condition.
This I C interface is a two-wire interface. Figure 5-1 shows a typical I2C Interface connection. The I2C interface specifies different communication bit rates. These are referred to as standard, fast or high speed modes. The MCP47X6 supports these three modes. The bit rates of these modes are: * Standard Mode: bit rates up to 100 kbit/s * Fast Mode: bit rates up to 400 kbit/s * High Speed Mode (HS mode): bit rates up to 3.4 Mbit/s A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions. The MCP47X6 device works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Communication is initiated by the master (microcontroller) which sends the START bit, followed by the slave address byte. The first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the R/W bit. Typical I2C Interface Connections Host Controller SCL SDA MCP4XXX SCL SDA
5.2.2
SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the device. The rising edge of the SCL signal latches the value on the SDA pin. The MCP47X6 will not stretch the clock signal (SCL) since memory read access occurs fast enough. Depending on the clock rate mode, the interface will display different characteristics.
FIGURE 5-1:
Typical I2C Interface.
The I2C serial protocol only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. For details on the frame content (commands/data) refer to Section 6.0. Refer to the NXP I2C document for more details on the I2C specifications.
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5.3 I2C Operation
5.3.1.3 Acknowledge (A) Bit
The MCP47X6's I2C module is compatible with the NXP I2C specification. The following lists some of the module's features: * 7-bit slave addressing * Supports three clock rate modes: - Standard mode, clock rates up to 100 kHz - Fast mode, clock rates up to 400 kHz - High-speed mode (HS mode), clock rates up to 3.4 MHz * Support Multi-Master Applications * General call addressing (Reset and Wake-Up commands) The I2C 10-bit addressing mode is not supported. The NXP I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP47X6 is defined in Section 6.0. The A bit (see Figure 5-4) is typically a response from the receiving device to the transmitting device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave device will supply an A response after the Start bit and 8 "data" bits have been received. An A bit has the SDA signal low.
SDA SCL
D0 8
A 9
FIGURE 5-4:
Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal high. Table 5-1 shows some of the conditions where the Slave Device will issue a Not A (A). If an error condition occurs (such as an A instead of A), then a START bit must be issued to reset the command state machine.
5.3.1
I2C BIT STATES AND SEQUENCE
Figure 5-8 shows the I2C transfer sequence. The serial clock is generated by the master. The following definitions are used for the bit states: * Start bit (S) * Data bit * Acknowledge (A) bit (driven low) / No Acknowledge (A) bit (not driven low) * Repeated Start bit (Sr) * Stop bit (P)
TABLE 5-1:
Event General Call
MCP47X6 A / A RESPONSES
Acknowledge Bit Response A A A A After device has received address and command, and valid conditions for EEPROM write I2C Module Resets, or a "Don't Care" if the collision occurs on the Master's "Start bit" Comment
5.3.1.1
Start Bit
The Start bit (see Figure 5-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is "High".
Slave Address valid Slave Address not valid Communication during EEPROM write cycle
SDA SCL S
1st Bit
2nd Bit
FIGURE 5-2: 5.3.1.2 Data Bit
Start Bit.
Bus Collision
N.A.
The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 5-5).
SDA SCL
1st Bit
2nd Bit
Data Bit
FIGURE 5-3:
Data Bit.
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5.3.1.4 Repeated Start Bit 5.3.1.5 Stop Bit
The Repeated Start bit (see Figure 5-5) indicates the current Master Device wishes to continue communicating with the current Slave Device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is "High". Note 1: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". The Stop bit (see Figure 5-6) Indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is "High". A Stop bit resets the I2C interface of all MCP47X6 devices.
SDA A / A SCL P
FIGURE 5-6: Transmit Mode. 5.3.2
Stop Condition Receive or
CLOCK STRETCHING
"Clock Stretching" is something that the receiving Device can do, to allow additional time to "respond" to the "data" that has been received. The MCP47X6 will not stretch the clock signal (SCL) since memory read access occurs fast enough.
SDA
1st Bit
5.3.3
ABORTING A TRANSMISSION
SCL Sr = Repeated Start
If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they corrupt the device.
FIGURE 5-5: Waveform.
Repeat Start Condition
SDA
SCL S 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A/A P
FIGURE 5-7:
SDA
Typical 8-Bit I2C Waveform Format.
SCL START Condition Data allowed to change Data or A valid STOP Condition
FIGURE 5-8:
I2C Data States and Bit Sequence.
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5.3.4 SLOPE CONTROL TABLE 5-2:
7-bit I2C Address `1100000' `1100001' `1100010' `1100011' `1100100' `1100101' `1100110' `1100111' Note 1:
I2C ADDRESS / ORDER CODE
Device Order Code MCP47x6A0-E/xx MCP47x6A0T-E/xx MCP47x6A1-E/xx MCP47x6A1T-E/xx MCP47x6A2-E/xx MCP47x6A2T-E/xx MCP47x6A3-E/xx MCP47x6A3T-E/xx MCP47x6A4-E/xx MCP47x6A4T-E/xx MCP47x6A5-E/xx MCP47x6A5T-E/xx MCP47x6A6-E/xx MCP47x6A6T-E/xx MCP47x6A7-E/xx MCP47x6A7T-E/xx Tape and Reel Tape and Reel Tape and Reel Tape and Reel Tape and Reel Tape and Reel Tape and Reel Tape and Reel Comment
The MCP47X6 implements slope control on the SDA output. As the device transitions from HS mode to FS mode, the slope control parameter will change from the HS specification to the FS specification. For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmidt trigger at SDA and SCL inputs.
5.3.5
DEVICE ADDRESSING
The address byte is the first byte received following the START condition from the master device. The MCP47X6's slave address consists of a 4-bit fixed code (`1100') and a 3-bit code that is user specified when the device is ordered. This allows up to eight MCP47X6 devices on a single I2C bus. slave address byte format, Figure 5-9 shows the I which contains the seven address bits and a read/write (R/W) bit. Table 5-2 shows the eight I2C Slave address options and their respective device order code.
Acknowledge bit Start bit Read/Write bit Slave Address Address Byte Slave Address (7-bits) Fixed User Specified R/W ACK
2C
2:
The sample center will generally stock I2C address `1100000', other addresses may be available. `xx' in the order code is the device package code (CH for SOT-23 and MA for DFN)
1
1
0
0
A2
A1
A0
Note: Address Bits (A2:A0) specified at time of device order, see Table 5-2.
FIGURE 5-9: I2C Control Byte.
Slave Address Bits in the
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5.3.6
2
HS MODE
The I C specification requires that a high-speed mode device must be `activated' to operate in high-speed (3.4 Mbit/s) mode. This is done by the Master sending a special address byte following the START bit. This byte is referred to as the high-speed Master Mode Code (HSMMC). The MCP47X6 device does not acknowledge this byte. However, upon receiving this command, the device switches to HS mode. The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next STOP condition. The master code is sent as follows: 1. 2. START condition (S) High-Speed Master Mode Code (0000 1XXX), The XXX bits are unique to the high-speed (HS) mode Master. No Acknowledge (A)
After switching to the High-Speed mode, the next transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. The Master Device can then either issue a Repeated Start bit to address a different device (at High-Speed) or a Stop bit to return to Fast/Standard bus speed. After the Stop bit, any other Master Device (in a Multi-Master system) can arbitrate for the I2C bus. See Figure 5-10 for illustration of HS mode command sequence. For more information on the HS mode, or other I2C modes, please refer to the NXP I2C specification.
5.3.6.1
Slope Control
The slope control on the SDA output is different between the Fast/Standard Speed and the High-Speed clock modes of the interface.
3.
5.3.6.2
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10 ns during HS mode.
F/S-mode
HS-mode
P F/S-mode "Data" A/A
S `0 0 0 0 1 X X X'b
A Sr `Slave Address' R/W A
HS-mode continues Sr `Slave Address' R/W A Control Byte
HS Select Byte
Control Byte
Command/Data Byte(s)
S = Start bit Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS Mode)
FIGURE 5-10:
HS Mode Sequence.
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5.3.7 GENERAL CALL
The General Call is a method that the "Master" device can communicate with all other "Slave" devices. In a Multi-Master application, the other Master devices are operating in Slave mode. The General Call address has two documented formats. These are shown in Figure 5-11. The MCP47X6 has two General Call Commands. The function of these commands are: * Reset the device(s) (Software Reset) * Wake-Up the device(s) For details on the operation of the MCP47X6's General Call Commands, see Section 6.6. Note: Only one General Call command per issue of the General Call control byte. Any additional General Call commands are ignored and Not Acknowledged.
Second Byte S00 0 0 00 0 0 AXXXXXXX0 "7-bit Command" AP
General Call Address
Reserved 7-bit Commands (By I2C Specification - NXP specification # UM10204, Rev. 03 19 June 2007) `0000 011'b - Reset and write programmable part of slave address by hardware. `0000 010'b - Write programmable part of slave address by hardware. `0000 000'b - NOT Allowed The Following is a "Hardware General Call" Format Second Byte S0 00 0 0 0 00 AXXXXX XX1
n occurrences of (Data + A) AXXXXXXXXAP
General Call Address
"Master Address"
This indicates a "Hardware General Call"
FIGURE 5-11:
General Call Formats.
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6.0 MCP47X6 I2C COMMANDS
TABLE 6-1:
The I2C protocol does not specify how commands are formatted, so this section specifies the MCP47X6's I2C command formats and operation. The commands can be grouped into the following categories: * Write memory * Read memory * General Call commands The supported commands are shown in Table 6-2. Many of these commands allow for continuous operation. This means that the I2C Master does not generate a Stop bit but repeats the required data/ clocks. This allows faster updates since the overhead of the I2C control byte is removed. Table 6-1 shows the supported commands and the required number of bit clocks for both single and continuous commands. Write commands, determined by the R/W bit = `0', use up to three command codes bits (C2:C0) to determine the write's operation. The Read command is strictly determined by the R/W bit = `1'. There are two formats of the command. One for 12-bit and 10-bit devices and a second for 8-bit devices. The General Call commands utilize the I2C specification reserved General Call command address and command codes.
I2C COMMANDS - NUMBER OF CLOCKS
Command
# of Bit Clocks () Operation Mode 1 Single 29 Write Volatile DAC Register Command (2) Continuous 18n + 11 Write Volatile Memory Single 38 Command Continuous 27n + 11 Write All Memory Command Single 38 Continuous 27n + 11 Write Volatile Configuration Single 20 bits Command Continuous 9n + 11 Read Command (12 and 10-bit Single 65 DAC register) (2) Continuous 54n + 11 Read Command (8-bit DAC Single 47 register) (2) Continuous 36n + 11 Note 1: "n" indicates the number of times the command operation is to be repeated. 2: This command is useful to determine when an EEPROM programming cycle has completed (RDY/BSY status bit)
6.0.1
ABORTING A TRANSMISSION
A Restart or Stop condition in an expected data bit position will abort the current command sequence and data will not be written to the MCP47X6.
TABLE 6-2:
MCP47X6 SUPPORTED COMMANDS
Writes Volatile Memory? Command during Comment EEPROM Config. DAC Config. DAC Write Cycle? No No No Writes volatile Power Down bits so can also be used to exit a power down state. Writes EEPROM Memory?
Command Code (Note 1) Command Name C2 C1 C0 0 0 X Write Volatile DAC Register Command (Note 2)
PD1:PD Yes 0 only
0 0 1 1 1 1
1 1 0 0 1 1
0 Write Volatile Memory Command 1 Write All Memory Command 0 Write Volatile Configuration bits Command 1 0 Reserved 1 Read Command
Yes Yes Yes N.A. N.A. N.A.
Yes Yes No N.A. N.A. N.A.
No Yes No N.A. N.A. N.A.
No Yes No N.A. N.A. N.A.
No No No Reserved (Note 3)
N.A.
N.A.
Note 1: 2: 3:
Reserved (Note 3) Yes Determined by R/W bit in I2C Control byte General Call Reset N.A. N.A. N.A. N.A. No Determined by General Call command byte after General Call Wake-up N.A. N.A. N.A. N.A. No the I2C General Call address. These bits are the MSb of the 2nd byte in the I2C write command. See Figure 6-1 to Figure 6-4. X = Don't Care bit. This command format does not use C0 bit. Device operation is not specified.
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6.1 Write Volatile DAC Register (C2:C0 = `00x')
After this ACK bit, the I2C Master should generate a Stop bit or the I2C Master can repeat the 2nd (2 command bits + 2 power down bits + 4 data bits (b11:b08)) and the 3rd byte (8 data bits (b07:b00)). Repeating the 2nd and 3rd bytes allows a continuous command where the volatile DAC register can be updated without the communication overhead of the device addressing byte (1st byte). The device updates the VOUT at the falling edge of the Acknowledge pulse of the 3rd byte.
This command is used to update the volatile DAC Register value and the two Power-down configuration bits (PD1:PD0). This command is typically used for a quick update of the analog output by modifying the minimum parameters. The EEPROM values are not affected by this command. Figure 6-1 shows an example of the command format, where a stop bit completes the command. The volatile DAC register and Power-down configuration bits are updated with the written date at the completion of the ACK bit (falling edge of SCL).
Read/Write bit (Write) Start bit ACK bit (3)
ACK bit (3)
ACK bit (3)
Stop bit
S SDA SCL Device Addressing 1 1 0
R/W A 0 A2 A1 A0 0 0 0 0
PD1 PD0 b11 b10 b09 b08
A 0
b07 b06 b05 b04 b03 b02 b01 b00
A 0
P
Command Power Data bits (4 bits) bits Down bits Data bits (12 bits)
Data bits (8 bits)
Note 1 Note 2
b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 MCP4706 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X D07 D06 D05 D04 D03 D02 D01 D00
Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd - 3rd bytes can be repeated after the 3rd byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend:
X = don't care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device
FIGURE 6-1:
Write Volatile DAC Register Command.
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6.2 Write Volatile Memory (C2:C0 = `010')
After this ACK bit, the I2C Master should generate a Stop bit or the I2C Master can repeat the 2nd (3 command bits + 5 configuration bits), and the 3rd byte (8 data bits (b15:b08)), and the 4th byte (8 data bits (b07:b00)). Repeating the 2nd through 4th bytes allows a continuous command where the volatile DAC register and configuration bits can be updated without the communication overhead of the device addressing byte (1st byte).
This write command is used to update the volatile DAC Register value and configuration bits. The EEPROM is not affected by this command. Figure 6-2 shows an example of this write command. The volatile DAC register and configuration bits are updated with the written date at the completion of the ACK bit (falling edge of SCL).
Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) ACK bit (3)
S SDA SCL Device Addressing 1 1 0
R/W A 0 A2 A1 A0 0 0 0 1
VREF1
VREF0 PD1 PD0 G
A 0
b15 b14 b13 b12 b11 b10 b09 b08
A 0
0
Command Ref. Power Gain bits Voltage Down bit Select bits bits
Data bits (8 bits) (3rd byte) ACK bit (3)
Stop bit
A
b07 b06 b05 b04 b03 b02 b01 b00
P
0
Data bits (8 bits) (4th byte)
Data bits (16 bits) (3rd + 4th bytes) b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 MCP4706 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X X X X X X X X X
Note 1 Note 2
Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd - 4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend:
X = don't care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device
FIGURE 6-2:
Write Volatile Memory Command.
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6.3 Write All Memory (C2:C0 = `011')
Note: RDY/BSY bit toggles to "low" and back to "high" after the EEPROM write is completed. The state of the RDY/BSY bit can be monitored by a read command.
This write command is used to update the volatile and nonvolatile (EEPROM) DAC Register value and configuration bits. Figure 6-3 shows an example of this write command. * VOUT update: At the falling edge of the Acknowledge pulse of the 4th byte. * EEPROM update: At the falling edge of the Acknowledge pulse of the 4th byte. The DAC register and Power-down configuration bits (volatile and EEPROM) are updated with the written date at the completion of the ACK bit (falling edge of SCL). The EEPROM memory requires time (TWC) for the values to be written. Another Write All memory command should not be issued until the EEPROM write is complete.
Read/Write bit (Write) Start bit ACK bit (3)
Write commands which only update volatile memory (C2:C0 = `00x' or `010') can be issued. Read commands and the General Call commands may not be issued.
ACK bit (3)
ACK bit (3)
S SDA SCL Device Addressing 1 1 0
R/W A 0 A2 A1 A0 0 0 0 1
VREF1
VREF0 PD1 PD0 G
A 0
b15 b14 b13 b12 b11 b10 b09 b08
A 0
1
Command Ref. Power Gain bits Voltage Down bit Select bits bits
Data bits (8 bits) (3rd byte) ACK bit (3)
Stop bit
A
b07 b06 b05 b04 b03 b02 b01 b00
P
0
Data bits (8 bits) (4th byte)
Data bits (16 bits) (3rd + 4th bytes) b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 MCP4706 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X X X X X X X X X
Note 1 Note 2
Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd - 4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend:
X = don't care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device
FIGURE 6-3:
Write All Memory Command.
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6.4 Write Volatile Configuration bits (C2:C0 = `100')
This write command is used to update the volatile configuration register bits only. This command is a quick method to modify the configuration of the DAC, such as the selection of the resistor ladder reference voltage, the op amp gain, and the Power Down state. Figure 6-4 shows an example of this write command.
Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) Stop bit
S SDA SCL Device Addressing 1 1 0
R/W A 0 A2 A1 A0 0 0 1 0
VREF1
VREF0 PD1 PD0 G
A 0
P
0
Command bits
Configuration bits
Note 1 Note 2 Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse. 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6.
FIGURE 6-4:
Write Volatile Configuration Bits Command.
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6.5 READ COMMAND
This command reads all the device memory. This includes the volatile and nonvolatile (EEPROM) DAC Register values and configuration bits, and the volatile status bits. This command is executed when the I2C control byte's Read/Write bit is a `1' (read).
Read/Write bit (Read) Start bit ACK bit (3)
This command has two different formats based on the resolution of the device. The 12-bit and 10-bit devices use the format in Figure 6-5, while the 8-bit device uses the format in Figure 6-6. The 2nd byte (configuration bits) indicates the current condition of the device operation. The RDY/BSY bit indicates EEPROM writing status.
S SDA SCL Device Addressing 1 1 0
R/W A 0 A2 A1 A0 1 0
ACK bit (4)
ACK bit (4)
ACK bit (4)
VREF1 RDY POR
VREF0 PD1 PD0 G
A 0
b15 b14 b13 b12 b11 b10 b09 b08
A 0
b07 b06 b05 b04 b03 b02 b01 b00
A 0
0
Vol. Status bits
Vol. Configuration bits
Vol. Data bits (8 bits) (3rd byte) ACK bit (4)
Vol. Data bits (8 bits) (4th byte) ACK/NACK bit (5) Stop bit
ACK bit (4)
VREF1 RDY POR
VREF0 PD1 PD0 G
A 0
b15 b14 b13 b12 b11 b10 b09 b08
A 0
b07 b06 b05 b04 b03 b02 b01 b00
A/N 0/1
P
1
Vol. Status bits
NV Configuration bits
NV Data bits (8 bits) (6th byte)
NV Data bits (8 bits) (7th byte)
Data bits (16 bits) (3rd + 4th bytes, and 6th + 7th bytes) b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 MCP4716 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 0 0 0 0 0 0 0 0 0 0
Note 1
Note 1: The 2nd - 7th bytes can be repeated after the 7th byte by continued clocking before issuing Stop bit. 2: ACK bit generated by MCP47X6. 3: ACK bit generated by I2C Master. 4: ACK/NACK bit generated by I2C Master. Legend:
D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device
FIGURE 6-5:
Read Command Format for 12-bit DAC (MCP4726) and 10-bit DAC (MCP4716).
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Read/Write bit (Read) Start bit ACK bit (3) ACK bit (4) ACK bit (4)
S SDA SCL Device Addressing 1 1 0
R/W A 0 A2 A1 A0 1 0
RDY POR
VREF1
VREF0 PD1 PD0 G
A 0
b07 b06 b05 b04 b03 b02 b01 b00
A 0
0
Vol. Status bits
Vol. Configuration bits ACK bit (4)
Vol. Data bits (8 bits) (3rd byte) ACK/NACK bit (5) Stop bit
VREF1 RDY POR
VREF0 PD1 PD0 G
A 0
b07 b06 b05 b04 b03 b02 b01 b00
A/N 0/1
P
1
Vol. Status bits
NV Configuration bits
NV Data bits (8 bits) (5th byte)
Data bits (8 bits) (3rd and 5th bytes) b07 b06 b05 b04 b03 b02 b01 b00 MCP4706 D07 D06 D05 D04 D03 D02 D01 D00
Note 1 Note 2
Note 1: a 2: The 2nd - 5th bytes can be repeated after the 5th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend:
D07:D00 = 8-bit data for MCP4706 device
FIGURE 6-6:
Read Command Format for 8-bit DAC (MCP4706).
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6.6 I2C General Call Commands
6.6.1 GENERAL CALL RESET
The device acknowledges the general call address command (0x00 in the first byte). The meaning of the general call address is always specified in the second byte. The I2C specification does not allow "00000000" (00h) in the second byte. Please refer to the Phillips I2C document for more details on the General Call specifications. The MCP47X6 devices support the following I2C general calls: * General Call Reset * General Call Wake-Up The device performs General Call Reset if the second byte is "00000110" (06h). At the acknowledgement of this byte, the device will abort the current conversion and perform the following tasks: * Internal reset similar to a Power-On-Reset (POR). The contents of the EEPROM are loaded into the DAC registers and analog output is available immediately. * This is a similar event to the POR. The VOUT will be available immediately, but after a short time delay following the Acknowledgement pulse. The VOUT value is determined by the EEPROM contents. This command allows multiple MCP47X6 devices to be reset synchronously.
Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) Stop bit
S SDA SCL General Call Address 0 0 0 0 0 0 0
R/W A 0 0 0 0 0 0 0 1 1 0
A 0
P
General Call Reset Command
Note 1 Note 2 Note 1: At the falling edge of the SCL at the end of this ACK pulse a reset occurs (startup timer starts and DAC register latched). 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6.
FIGURE 6-7:
General Call Reset Command.
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6.6.2 GENERAL CALL WAKE-UP
If the second byte is "00001001" (09h), the device forces the volatile power-down bits to `00'. The nonvolatile (EEPROM) power-down bit values are not affected by this command. This command allows multiple MCP47X6 devices to wake-up synchronously.
Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) Stop bit
Note:
This command does not adhere to the I2C specification where if the LSb of the 2nd byte is a `1', it is a `Hardware General Call' (see the NXP I2C Specification).
S SDA SCL General Call Address 0 0 0 0 0 0 0
R/W A 0 0 0 0 0 0 1 0 0 1
A 0
P
General Call Wake-Up Command
Note 1 Note 2 Note 1: At the falling edge of the SCL, at the end of this ACK pulse, the volatile PD1:PD0 bits are forced to `00'. 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6.
FIGURE 6-8:
General Call Wake-Up Command.
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7.0
7.1
TERMINOLOGY
Resolution
7.5
Zero-Scale Error (ZSE)
The resolution is the number of DAC output states that divide the full-scale range. For the 12-bit DAC, the resolution is 212, meaning the DAC code ranges from 0 to 4095.
The Zero-Scale Error (see Figure 7-4) is the difference between the ideal and measured VOUT voltage with the volatile DAC Register equal to 000h. The Zero-Scale Error is the same as the Offset Error for this case (volatile DAC Register = 000h).
EQUATION 7-3:
ZSE =
ZERO SCALE ERROR
VLSb
7.2
Least Significant bit (LSb)
VOUT(@ZS)
Normally this is thought of as the ideal voltage difference between two successive codes. This bit has the smallest value or weight of all bits in the register. For a given output voltage range, which is typically the voltage between the Full-Scale voltage and the ZeroScale voltage (VOUT(FS) - VOUT(ZS)), it is divided by the resolution of the device (Equation 7-1).
Where: FSE is expressed in LSb VOUT(@ZS) is the VOUT voltage when the DAC register code is at Zero-scale. VLSb is the delta voltage of one DAC register code step (such as code 000h to code 001h).
EQUATION 7-1:
LSb VOLTAGE CALCULATION
VOUT(FS) - VOUT(ZS) 2N - 1
7.6
Offset Error
VLSb =
2N = 4096 (MCP4726) 1024 (MCP4716) 256 (MCP4706)
The Offset error (see Figure 7-1) is the deviation from zero voltage output when the volatile DAC Register value = 000h (zero scale voltage). This error affects all codes by the same amount. The offset error can be calibrated by software in application circuits.
Actual Transfer Function
7.3
Monotonicity
Analog Output
Normally this is thought of as the VOUT voltage never decreasing, as the DAC Register code is continuously incremented by 1 code step (LSb).
7.4
Full-Scale Error (FSE)
The Full-scale error (see Figure 7-4) is the sum of offset error plus gain error. It is the difference between the ideal and measured DAC output voltage with all bits set to one (DAC input code = FFFh for 12-bit DAC).
Offset Error (ZSE) 0
Ideal Transfer Function
DAC Input Code
FIGURE 7-1:
Offset Error Example.
EQUATION 7-2:
FSE =
FULL SCALE ERROR
VLSb
VOUT(@FS) - VIDEAL(@FS)
Where: FSE is expressed in LSb VOUT(@FS) is the VOUT voltage when the DAC register code is at Full-scale. VIDEAL(@FS) is the ideal output voltage when the DAC register code is at Full-scale. VLSb is the delta voltage of one DAC register code step (such as code 000h to code 001h).
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7.7 Integral Nonlinearity (INL) 7.8 Differential Nonlinearity (DNL)
The Integral nonlinearity (INL) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line). In the MCP47X6, INL is calculated using two end points (zero and full scale). INL can be expressed as a percentage of full scale range (FSR) or in a fraction of an LSb. INL is also called relative accuracy. Equation 7-4 shows how to calculate the INL error in LSb and Figure 7-2 shows an example of INL accuracy. The Differential nonlinearity (DNL) error (see Figure 73) is the measure of step size between codes in actual transfer function. The ideal step size between codes is 1 LSb. A DNL error of zero would imply that every code is exactly 1 LSb wide. If the DNL error is less than 1 LSb, the DAC guarantees monotonic output and no missing codes. The DNL error between any two adjacent codes is calculated as follows:
EQUATION 7-5:
DNL ERROR
EQUATION 7-4:
INL ERROR
Where:
( VOUT - VIdeal ) INL = -------------------------------------LSb Where: INL is expressed in LSb. = Code*LSb VIdeal
V OUT - LSb DNL = --------------------------------LSb DNL is expressed in LSb. VOUT = The measured DAC output voltage difference between two adjacent input codes.
VOUT
=
The output voltage measured with a given DAC input code
7 7 INL = < -1 LSb 6 5 Analog 4 Output (LSb) 3 2 1 0 000 001 010 011 100 101 110 111 DAC Input Code INL = - 1 LSb Analog 4 Output (LSb) 3 INL = 0.5 LSb 2 1 0 000 001 010 6 5
DNL = 0.5 LSb
DNL = 2 LSb
011 100 101 110 111
DAC Input Code Ideal Transfer Function Actual Transfer Function
Ideal Transfer Function Actual Transfer Function
FIGURE 7-3:
DNL Accuracy Example.
FIGURE 7-2:
INL Accuracy Example.
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7.9 Gain Error 7.10 Gain Error Drift
The Gain error (see Figure 7-4) is the difference between the actual full-scale output voltage from the ideal output voltage of the DAC transfer curve. The gain error is calculated after nullifying the offset error, or full scale error minus the offset error. The gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The gain error is usually expressed as percent of full-scale range (% of FSR) or in LSb. In the MCP4706/4716/4726, the gain error is not calibrated at the factory and most of the gain error is contributed by the output buffer (op amp) saturation near the code range beyond 4000d. For the applications that need the gain error specification less than 1% maximum, the user may consider using the DAC code range between 100d and 4000d instead of using full code range (code 0 to 4095d). The DAC output of the code range between 100d and 4000d is much more linear than full-scale range (0 to 4095d). The gain error can be calibrated out by software in the application. The Gain error drift is the variation in gain error due to a change in ambient temperature. The gain error drift is typically expressed in ppm/oC.
7.11
Offset Error Drift
The Offset error drift is the variation in offset error due to a change in ambient temperature. The offset error drift is typically expressed in ppm/oC.
7.12
Settling Time
The Settling time is the time delay required for the VOUT voltage to settle into its new output value. This time is measured from the start of code transition, to when the VOUT voltage is within the specified accuracy. In the MCP47X6, the settling time is a measure of the time delay until the VOUT voltage reaches within 0.5 LSb of its final value, when the volatile DAC Register changes from 400h to C00h.
7.13
Major-Code Transition Glitch
Actual Transfer Function Full-Scale Error
Analog Output
Gain Error
Major-code transition glitch is the impulse energy injected into the DAC analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-Sec, and is measured when the digital code is changed by 1 LSb at the major carry transition (Example: 011...111 to 100... 000, or 100... 000 to 011 ... 111).
7.14
Actual Transfer Function after Offset Error is removed Zero-Scale Error 0 Ideal Transfer Function
Digital Feedthrough
DAC Input Code
The Digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. The area of the glitch is expressed in nV-Sec, and is measured with a full scale change (Example: all 0s to all 1s and vice versa) on the digital input pins. The digital feedthrough is measured when the DAC is not being written to the output register.
FIGURE 7-4: Error Example.
Gain Error and Full-Scale
7.15
Power-Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. The VOUT is measured while the VDD is varied +/- 10%, and expressed in dB or V/V.
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8.0 TYPICAL APPLICATIONS
8.1.1 DEVICE CONNECTION TEST
The MCP47X6 family of devices are general purpose, single channel voltage output DACs for various applications where a precision operation with low-power and nonvolatile EEPROM memory is needed. Since the devices include a nonvolatile EEPROM memory, the user can utilize these devices for applications that require the output to return to the previous set-up value on subsequent power-ups. Applications generally suited for the devices are: * * * * Set Point or Offset Trimming Sensor Calibration Portable Instrumentation (Battery Powered) Motor Control c) The user can test the presence of the device on the I2C bus line using a simple I2C command. This test can be achieved by checking an acknowledge response from the device after sending a read or write command. Figure 8-1 shows an example with a read command. The steps are: a) b) Set the R/W bit "High" in the device's address byte. Check the ACK bit of the address byte. If the device acknowledges (ACK = 0) the command, then the device is connected, otherwise it is not connected. Send Stop bit.
Address Byte
8.1
Connecting to I2C BUS using Pull-Up Resistors
SCL
1
2
3
4
5
6
7
8
9
The SCL and SDA pins of the MCP47X6 devices are open-drain configurations. These pins require a pull-up resistor as shown in Figure 8-2. The pull-up resistor values (R1 and R2) for SCL and SDA pins depend on the operating speed (standard, fast, and high speed) and loading capacitance of the I2C bus line. A higher value of the pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus line. Therefore, it can limit the bus operating speed. The lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 k and 10 k ranges for standard and fast modes, and less than 1 k for high speed mode.
SDA Start Bit
1
1
0
1 A2 A1 A0 1
ACK Stop Bit
Device Code Address bits R/W
Device Response
FIGURE 8-1:
I2C Bus Connection Test.
(c) 2011 Microchip Technology Inc.
DS22272A-page 63
MCP4706/4716/4726
8.2 Power Supply Considerations
VDD Optional Analog C3 Output
The power source should be as clean as possible. The power supply to the device is also used for the DAC voltage reference internally if the internal VDD is selected as the resistor ladders reference voltage (VREF1:VREF0 = 00 or 01). Any noise induced on the VDD line can affect the DAC performance. Typical applications will require a bypass capacitor in order to filter out high frequency noise on the VDD line. The noise can be induced onto the power supply's traces or as a result of changes on the DAC output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-2 shows an example of using two bypass capacitors (a 10 F tantalum capacitor and a 0.1 F ceramic capacitor) in parallel on the VDD line. These capacitors should be placed as close to the VDD pin as possible (within 4 mm). If the application circuit has separate digital and analog power supplies, the VDD and VSS pins of the device should reside on the analog plane.
MCP47X6
VOUT 1 VSS 2 VDD
C1 C2
6 VREF 5 4 SDA SCL
R1 R2 To MCU
3
(a) Circuit when VDD is selected as reference
(Note: VDD is connected to the reference circuit internally.)
VDD Optional Analog C3 Output Optional
VREF
C4 C5
MCP47X6
VOUT 1 VSS 2 VDD
C1 C2
6 VREF 5 4 SDA SCL
R1 R2 To MCU
3
(b) Circuit when external reference is used.
R1 and R2 are I2C pull-up resistors: R1 and R2: 5 k - 10 k for fSCL = 100 kHz to 400 kHz ~700 for fSCL = 3.4 MHz C1: C2: C3: C4: C5: 0.1 F capacitor 10 F capacitor ~ 0.1 F 0.1 F capacitor 10 F capacitor Ceramic Tantalum Optional to reduce noise in VOUT pin. Ceramic Tantalum
Note: Pin assignment is opposite in DFN-6 package.
FIGURE 8-2: Example MCP47X6 Circuit with SOT-23 package.
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8.3 Application Examples
8.3.1 DC SET POINT OR CALIBRATION
The MCP47X6 devices are rail-to-rail output DACs designed to operate with a VDD range of 2.7V to 5.5V. The internal output op amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. The user can use gain of 1 or 2 of the output op amplifier by setting the configuration register bits. Also, the user can use internal VDD as the reference or use external reference. Various user options and easy-to-use features make the devices suitable for various modern DAC applications. Application examples include: * * * * * * * * * * Decreasing Output Step Size Building a "Window" DAC Bipolar Operation Selectable Gain and Offset Bipolar Voltage Output Designing a Double-Precision DAC Building Programmable Current Source Serial Interface Communication Times Software I2C Interface Reset Sequence Power Supply Considerations Layout Considerations A common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. For example, the MCP4726 provides 4096 output steps. If voltage reference is 4.096V, the LSb size is 1 mV. If a smaller output step size is desired, a lower external voltage reference is needed.
8.3.1.1
Decreasing Output Step Size
If the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8V may be desired with about 200 V resolution per step. Two common methods to achieve small step size are using lower VREF pin voltage or using a voltage divider on the DAC's output. Using an external voltage reference (VREF) is an option, if the external reference is available with the desired output voltage range. However, occasionally, when using a low-voltage reference voltage, the noise floor causes a SNR error that is intolerable. Using a voltage divider method is another option, and provides some advantages when external voltage reference needs to be very low, or when the desired output voltage is not available. In this case, a larger value reference voltage is used, while two resistors scale the output range down to the precise desired level. Figure 8-3 illustrates this concept. A bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. VDD
Optional
VREF VDD
RSENSE VCC+ R1 VO R2 VTRIP Comp. C1 VOUT
MCP47X6 I2CTM 2-wire
VCC-
FIGURE 8-3: Example Circuit Of Set Point or Threshold Calibration. EQUATION 8-1: VOUT AND VTRIP CALCULATIONS
DAC Register Value 2N
VOUT = VREF * G *
R2 V trip = VOUT -------------------- R1 + R2
(c) 2011 Microchip Technology Inc.
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8.3.1.2 Building a "Window" DAC
8.4
Bipolar Operation
When calibrating a set point or threshold of a sensor, typically only a small portion of the DAC output range is utilized. If the LSb size is adequate enough to meet the application's accuracy needs, the unused range is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF, 2 * VREF, or VSS then creating a "window" around the threshold has several advantages. One simple method to create this "window" is to use a voltage divider network with a pull-up and pull-down resistor. Figure 8-4 and Figure 86 illustrate this concept.
Bipolar operation is achievable by utilizing an external operational amplifier. This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. Figure 8-5 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VDD, instead of VSS, if a higher offset is desired.
Optional
VREF VDD VCC+
Optional
VREF VDD
RSENSE R3
VCC+ VCC+
MCP47X6 VO I2CTM 2-wire
R3 VOUT R4
VOA+ C1 VCC- R2 VIN R1
VO
MCP47X6 I2CTM 2-wire
R1 VOUT
VTRIP Comp. C1 VCC-
R2 VCC-
FIGURE 8-4: DAC. EQUATION 8-2:
Single-Supply "Window"
FIGURE 8-5: Digitally-Controlled Bipolar Voltage Source Example Circuit. EQUATION 8-3: VOUT, VOA+, AND VO CALCULATIONS
DAC Register Value 2N
VOUT AND VTRIP CALCULATIONS
DAC Register Value 2N
VOUT = VREF * G *
VOUT = VREF * G * VOA+ = VOUT * R4 R3 + R4
V OUT R23 + V 23 R1 V TRIP = -------------------------------------------R 1 + R23 R2R3 R23 = -----------------R2 + R3 ( VCC+ R2 ) + ( V CC- R 3 ) V23 = -----------------------------------------------------R 2 + R3 R1 VOUT VTRIP R23 V23
VO = VOA+ * ( 1 +
R2 R1
) - VDD * (
R2 R1
)
Thevenin Equivalent
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MCP4706/4716/4726
8.5 Selectable Gain and Offset Bipolar Voltage Output
Optional Optional
In some applications, precision digital control of the output range is desirable. Example 8-6 illustrates how to use the DAC devices to achieve this in a bipolar or single-supply application. This circuit is typically used for linearizing a sensor whose slope and offset varies. The equation to design a bipolar "window" DAC would be utilized if R3, R4 and R5 are populated.
VCC+ VREF VDD R3 VO R4 I CTM 2-wire
2
R5 VCC+ VOA+ C1 VCC- R2 VIN R1
MCP4726
VOUT
VCC-
8.5.1
BIPOLAR DAC EXAMPLE USING MCP4726
An output step size of 1 mV, with an output range of 2.05V, is desired for a particular application. Step 1: Calculate the range: +2.05V - (-2.05V) = 4.1V. Step 2: Calculate the resolution needed: 4.1V/1 mV = 4100 Since 2
12
FIGURE 8-6: Bipolar Voltage Source with Selectable Gain and Offset. EQUATION 8-4: VOUT, VOA+, AND VO CALCULATIONS
DAC Register Value 2N
= 4096, 12-bit resolution is desired. VOUT = VREF * G * VOA+ =
Step 3: The amplifier gain (R2/R1), multiplied by full-scale VOUT (4.096V), must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1+R2), the VREF value must be selected first. If a VREF of 4.096V is used, solve for the amplifier's gain by setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: - R2 - 2.05 -------- = ---------------4.096V R1 R2 1 ----- = -2 R1
VOUT * R4 + VCC- * R5 R3 + R4 R2 R1 ) - VIN * ( R2 R1 )
VO = VOA+ * ( 1 +
Offset Adjust
Gain Adjust
EQUATION 8-5:
BIPOLAR "WINDOW" DAC USING R4 AND R5
If R1 = 20 k and R2 = 10 k, the gain will be 0.5. Step 4: Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. R4 2 2.05V + ( 0.5 4.096V ) ----------------------- = ------------------------------------------------------- = -1.5 4.096V 3 ( R3 + R 4 ) If R4 = 20 k, then R3 = 10 k Figure 8-6 (C1 = 0.1uF) Thevenin Equivalent VCC+ R4 + V CC- R 5 V45 = -------------------------------------------R4 + R 5 V OUT R 45 + V45 R 3 V IN+ = -------------------------------------------R 3 + R 45 R4 R 5 R 45 = -----------------R 4 + R5 R2 R2 VO = VIN+ 1 + ----- - VA ----- R1 R 1 Offset Adjust Gain Adjust
(c) 2011 Microchip Technology Inc.
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8.6 Designing a Double-Precision DAC 8.7 Building Programmable Current Source
Figure 8-7 shows an example design of a single-supply voltage output capable of up to 24-bit resolution. This requires two 12-bit DACs. This design is simply a voltage divider with a buffered output. As an example, if a similar application to the one developed in Section 8.5.1 "Bipolar DAC Example Using MCP4726" required a resolution of 1 V instead of 1 mV, and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. Step 1: Calculate the resolution needed: 4.1V/1 V = 4.1 x 106. Since 222 = 4.2 x 106, 22-bit resolution is desired. Since DNL = 0.75 LSb, this design can be attempted with the 12-bit DAC. Step 2: Since DACB`s VOUTB has a resolution of 1 mV, its output only needs to be "pulled" 1/1000 to meet the 1 V target. Dividing VOUTA by 1000 would allow the application to compensate for DACB`s DNL error. Step 3: If R2 is 100, then R1 needs to be 100 k. Step 4: The resulting transfer function is shown in the equation of Example 8-6.
Optional
Example 8-8 shows an example of building programmable current source using a voltage follower. The current sensor resistor is used to convert the DAC voltage output into a digitally-selectable current source. The smaller RSENSE is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled. VDD (or VREF) VDD VCC+ VOUT MCP47X6 Ib I2CTM 2-wire IL I b = ---VCC- Load IL
Optional
VREF
RSENSE
V OUT I L = -------------- x -----------R sense + 1 where = Common-Emitter Current Gain.
VREF
VDD VOA R1 VCC+ VOUT VDD R2 0.1 F VCC-
FIGURE 8-8: Source.
Digitally-Controlled Current
MCP4726 (A) I2CTM 2-wire
Optional
VREF
MCP4726 (B) I CTM 2-wire
2
VOB
FIGURE 8-7: Simple Double Precision DAC using MCP4726. EQUATION 8-6:
VOUT =
VOUT CALCULATION
VOA * R2 + VOB * R1 R1 + R2
Where: VOA = (VREF * G * DAC A Register Value)/4096 VOB = (VREF * G * DAC B Register Value)/4096 G = Selected Op Amp Gain
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8.8 Serial Interface Communication Times
Table 8-1 shows time/frequency of the supported operations of the I2C serial interface for the different serial interface operational frequencies. This, along with the VOUT output performance (such as slew rate), would be used to determine your applications volatile DAC register update rate.
TABLE 8-1:
SERIAL INTERFACE TIMES / FREQUENCIES
Writes Volatile Writes EEPROM Memory? Memory? Config. DAC Yes
(1)
Command Code C2 C1 C0 Function 0 0 0 1 0 1 1 0 X Write Volatile DAC 0 Write Volatile Memory 1 Write All Memory 0 Write NV Configuration Bits Read
Config. No No Yes No
# of Command Frequency Serial Command Time (uS) (kHz) Interface DAC bits (2) 100kHz400kHz3.4MHz100kHz400kHz 3.4MHz No No Yes No 29 38 38 20 290 380 380 200 72.5 95 95 50 8.5 11.2 11.2 5.9 3.4 2.6 2.6 5.0 13.8 10.5 10.5 20.0 117.2 89.5 89.5 170.0
Yes Yes Yes No
Yes Yes Yes
N.A. Note 1: 2:
N.A.
N.A.
N.A.
N.A.
77
750
187.5
22.1
1.3
5.3
45.3
Only the volatile PD1:PD0 bits of the Configuration bits are written. Includes the Start or Stop bits.
(c) 2011 Microchip Technology Inc.
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8.9 Software I2C Interface Reset Sequence
This technique is documented in AN1028. The nine bits of `1' are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP47X6 is driving an A bit on the I2C bus, or is in output mode (from a Read command) and is driving a data bit of `0' onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP47X6 holding the bus low. By sending out nine `1' bits, it is ensured that the device will see an A bit (the Master Device does not drive the I2C bus low to acknowledge the data sent by the MCP47X6), which also forces the MCP47X6 to reset. The 2nd Start bit is sent to address the rare possibility of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP47X6, AND then as the Master Device returns to normal operation and issues a Start condition, while the MCP47X6 is issuing an Acknowledge. In this case, if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP47X6 could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the Master Device is reset while sending a Write command to the MCP47X6.
Note:
At times, it may become necessary to perform a Software Reset Sequence to ensure the MCP47X6 device is in a correct and known I2C Interface state. This technique only resets the I2C state machine. This is useful if the MCP47X6 device powers up in an incorrect state (due to excessive bus noise, etc), or if the Master Device is reset during communication. Figure 8-9 shows the communication sequence to software reset the device. S `1' `1' `1' `1' `1' `1' `1' `1' Nine bits of `1' Start bit Stop bit S P
Start bit
FIGURE 8-9: Format.
Software Reset Sequence
The 1st Start bit will cause the device to reset from a state in which it is expecting to receive data from the Master Device. In this mode, the device is monitoring the data bus in Receive mode and can detect if the Start bit forces an internal Reset.
The Stop bit terminates the current I2C bus activity. The MCP47X6 waits to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command.
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MCP4706/4716/4726
8.10 Design Considerations
8.10.2 LAYOUT CONSIDERATIONS
In the design of a system with the MCP4706/4716/4726 devices, the following considerations should be taken into account: * Power Supply Considerations * Layout Considerations Several layout considerations may be applicable to your application. These may include: * Noise * PCB Area Requirements
8.10.2.1
Noise
8.10.1
POWER SUPPLY CONSIDERATIONS
The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-10 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD 0.1 F VDD
Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP47X6's performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. Separate digital and analog ground planes are recommended. In this case, the VSS pin and the ground pins of the VDD capacitors should be terminated to the analog ground plane. Note: Breadboards and wire-wrapped boards are not recommended.
8.10.2.2
PCB Area Requirements
In some applications, PCB area is a criteria for device selection. Table 8-2 shows the typical package dimensions and area for the different package options. The table also shows the relative area factor compared to the smallest area. For space critical applications, the DFN package would be the suggested package.
PICTM Microcontroller
0.1 F
TABLE 8-2:
Package
PACKAGE FOOTPRINT (1)
Package Footprint Area (mm2) Dimensions (mm) Relative Area
Pins
MCP47X6
VREF VOUT
SCL SDA
Type
Code Length Width
6 6
SOT-23 CH 2.90 2.70 7.83 1.96 DFN MA 2.00 2.00 4.00 1 Note 1: Does not include recommended land pattern dimensions. Dimensions are typical values.
VSS
VSS
FIGURE 8-10: Connections.
Typical Microcontroller
(c) 2011 Microchip Technology Inc.
DS22272A-page 71
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NOTES:
DS22272A-page 72
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MCP4706/4716/4726
9.0 DEVELOPMENT SUPPORT
Development support can be classified into two groups. These are: * Development Tools * Technical Documentation
9.1
Development Tools
Several development tools are available to assist in your design and evaluation of the MCP47X6 devices. The currently available tools are shown in Table 9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com.
9.1.1
MCP47X6 PICTAIL PLUS DAUGHTER BOARD
MCP47X6 PICtail Plus Explore 16 Daughter Board inserted into PICtail Connector Development Board
The MCP47X6 PICtail Plus Daughter Board (Order Number: ADM00317) is available from Microchip Technology Inc. This board works with Microchip's PICkitTM Serial Analyzer and PIC Explorer 16 Development Board. The firmware example is also available for the Explore 16 Development Board with PIC24FJ128. Figure 9-1 shows the MCP47X6 PICtail Plus Daughter Board being used with a PIC Explorer 16 Development Board (order #: ADM00317), while Figure 9-2 shows the MCP47X6 PICtail Plus Daughter Board being used with a PICkitTM Serial Analyzer. The PICkitTM Serial Analyzer allows the user to quickly evaluate the DAC operation. Refer to the MCP47X6 PICtail Plus Daughter Board User's Guide for detailed descriptions on operating the daughter board. Refer to www.microchip.com for further information on this product and related material for the users.
FIGURE 9-1: MCP47X6 PICtail Plus Daughter Board with PIC Explorer 16 Development Board.
MCP47X6 PICtail Plus Daughter Board
FIGURE 9-2: MCP47X6 PICtail Plus Daughter Board with PICkitTM Serial Analyzer. TABLE 9-1:
Board Name 6-pin SC70 Evaluation Board MCP4706/4716/4726 Evaluation Board(1, 2)
DEVELOPMENT TOOLS
Part # SC70EV ADM00317(3) Supported Devices MCP4706, MCP4716, MCP4726 MCP4726
Note 1: Requires a PICDEM Demo board. See the User's Guide for additional information and requirements. 2: Requires a PICkit Serial Analyzer. See the User's Guide for additional information and requirements. 3: This board is currently in the manufacturing cycle, and should be available by end of March 2011.
(c) 2011 Microchip Technology Inc.
DS22272A-page 73
MCP4706/4716/4726
9.2 Technical Documentation
Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents.
TABLE 9-2:
Application Note Number AN1326 -- --
TECHNICAL DOCUMENTATION
Title Using DAC for LDMOS Amplifier Bias Control Applications Signal Chain Design Guide Analog Solutions for Automotive Applications Design Guide Literature # DS01326 DS21825 DS01005
DS22272A-page 74
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
10.0
10.1
PACKAGING INFORMATION
Package Marking Information
6-Lead SOT-23 Example
XXNN
DC25
Address Option A0 (00) A1 (01) A2 (10) A3 (11)
Code MCP4706A0T-E/CH MCP4716A0T-E/CH MCP4726A0T-E/CH DBNN DCNN DDNN DENN DFNN DGNN DHNN DJNN DKNN DLNN DMNN DPNN
6-Lead DFN (2x2)
Example
XXX NNN
AAB 425
Address Option A0 (00) A1 (01) A2 (10) A3 (11)
Code MCP4706A0T-E/MA MCP4716A0T-E/MA MCP4726A0T-E/MA AAA AAB AAC AAD AAE AAF AAG AAH AAP AAQ AAR AAS
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2011 Microchip Technology Inc.
DS22272A-page 75
MCP4706/4716/4726
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DS22272A-page 76
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(c) 2011 Microchip Technology Inc.
DS22272A-page 77
MCP4706/4716/4726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS22272A-page 78
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(c) 2011 Microchip Technology Inc.
DS22272A-page 79
MCP4706/4716/4726
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS22272A-page 80
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
APPENDIX A: REVISION HISTORY
Revision A (February 2011)
* Original Release of this Document.
(c) 2011 Microchip Technology Inc.
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NOTES:
DS22272A-page 82
(c) 2011 Microchip Technology Inc.
MCP4706/4716/4726
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX Address Options X X /XX Package
Examples:
a) MCP4706A0T-E/CH: 8-bit VOUT resolution, I2C Address "1100000", Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b) MCP4706A6T-E/CH: 8-bit VOUT resolution, I2C Address "1100110", Tape and Reel, Extended Temp., 6LD SOT-23 pkg. c) MCP4706A0T-E/MA: 8-bit VOUT resolution, I2C Address "1100000", Tape and Reel, Extended Temp., 6LD DFN pkg. d) MCP4706A6T-E/MA: 8-bit VOUT resolution, I2C Address "1100110", Tape and Reel, Extended Temp., 6LD DFN pkg.
Tape and Temperature Reel Range
Device:
MCP4706: MCP4716: MCP4726:
Single Channel 8-Bit DAC with EEPROM Memory Single Channel 10-Bit DAC with EEPROM Memory Single Channel 12-Bit DAC with EEPROM Memory
Address Options:
A0 =
"1100000" I2C Address. Devices ordered from the Microchip Sample center will have this address. "1100001" I2C Address. "1100010" I2C Address. "1100011" I2C Address. "1100100" I2C Address. "1100101" I2C Address. "1100110" I2C Address. "1100111" I2C Address. Tape and Reel
A1 = A2 = A3 = A4 = A5 = A6 = A7 = Tape and Reel: T =
Temperature Range: E Package:
=
-40C to +125C Plastic Small Outline Transistor (SOT-23-6), 6-lead Plastic Dual Flat, No Lead Package (2x2 DFN), 6-lead
CH = MA =
a) MCP4716A0T-E/CH: 10-bit VOUT resolution, I2C Address "1100000", Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b) MCP4716A6T-E/CH: 10-bit VOUT resolution, I2C Address "1100110", Tape and Reel, Extended Temp., 6LD SOT-23 pkg. c) MCP4716A0T-E/MA: 10-bit VOUT resolution, I2C Address "1100000", Tape and Reel, Extended Temp., 6LD DFN pkg. d) MCP4716A6T-E/MA: 10-bit VOUT resolution, I2C Address "1100110", Tape and Reel, Extended Temp., 6LD DFN pkg.
a) MCP4726A0T-E/CH: 12-bit VOUT resolution, I2C Address "1100000", Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b) MCP4726A6T-E/CH: 12-bit VOUT resolution, I2C Address "1100110", Tape and Reel, Extended Temp., 6LD SOT-23 pkg. c) MCP4726A0T-E/MA: 12-bit VOUT resolution, I2C Address "1100000", Tape and Reel, Extended Temp., 6LD DFN pkg. d) MCP4726A6T-E/MA: 12-bit VOUT resolution, I2C Address "1100110", Tape and Reel, Extended Temp., 6LD DFN pkg.
(c) 2011 Microchip Technology Inc.
DS22272A-page 83
MCP4706/4716/4726
NOTES:
DS22272A-page 84
(c) 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
ISBN: 978-1-60932-896-2
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2011 Microchip Technology Inc.
DS22272A-page 85
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08/04/10
DS22272A-page 86
(c) 2011 Microchip Technology Inc.

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