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ISL98002
Data Sheet March 26, 2008 FN6535.0
Triple Video Digitizer with Digital PLL
The ISL98002 3-Channel, 8-bit Analog Front End (AFE) contains all the functions necessary to digitize analog YPbPr video signals and RGB graphics signals from DVD players, digital VCRs, video set-top boxes, and personal computers. This product family's conversion rates support HDTV resolutions up to 1080p and PC monitor resolutions up to UXGA, while the front end's programmable input bandwidth ensures sharp, clear images at all resolutions. To maximize performance with the widest variety of video sources, the ISL98002 features a fast-responding digital PLL (DPLL), providing extremely low jitter with PC graphics signals and quick recovery from VCR head switching with video signals. Integrated HSYNC and SOG processing eliminate the need for external slicers, sync separators, Schmitt triggers, and filters. Glitchless, automatic Macrovision(R)- compliance is obtained by a digital Macrovision(R) detection function that detects and automatically removes Macrovision(R) from the HSYNC signal. Ease of use is also emphasized with features such as the elimination of PLL charge pump current/VCO range programming and single-bit switching between RGB and YPbPr signals. Automatic Black Level Compensation (ABLCTM) eliminates part-to-part offset variation, ensuring perfect black level performance in every application.
Features
* 140MSPS and 170MSPS maximum conversion rates * Glitchless Macrovision(R)-compliant sync separator * Extremely fast recovery from VCR head switching * Low PLL clock jitter (250ps peak-to-peak @ 170MSPS) * 64 interpixel sampling positions * 0.35VP-P to 1.4VP-P video input range * Programmable bandwidth (100MHz to 780MHz) * RGB 4:4:4 and YUV 4:2:2 output formats * Low power (535mW @ 170MSPS) * Small 10mmx10mm 72 Ld QFN package * Completely independent 8-bit gain/10-bit offset control * Pb-free (RoHS Compliant)
Applications
* Digital TVs * Projectors * Multifunction Monitors * Digital KVM * RGB Graphics Processing
Simplified Block Diagram
OFFSET DAC VOLTAGE CLAMP ABLCTM
RGB/YPBPRIN
3
8
PGA
+
8-BIT ADC
RGB/YUVOUT
X3
HSYNCOUT VSYNCOUT SOGIN HSYNCIN VSYNCIN SYNC PROCESSING DIGITAL PLL PIXELCLKOUT HSOUT
AFE CONFIGURATION AND CONTROL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL98002 Ordering Information
PART NUMBER (Note) ISL98002CRZ-140 ISL98002CRZ-170 PART MARKING ISL98002CRZ -140 ISL98002CRZ -170 MAXIMUM PIXEL RATE 140MHz 170MHz TEMP RANGE (C) 0C to +70C 0C to +70C PACKAGE (Pb-free) 72 Ld QFN 72 Ld QFN PKG. DWG. # L72.10x10B L72.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
Block Diagram
VCLAMP
VCLAMP
OFFSET DAC
10
10
ABLCTM
ABLCTM
RIN1
RIN1
VIN+
VIN+
Offset DAC
8 PGA + 8-BIT ADC 8
8 8
R[7:0]
RP[7:0]
RIN2
RIN2
VINVIN-
PGA
VCLAMP
+
8 bit ADC
10
10
VCLAMP
OFFSET Offset DAC
ABLCTM
ABLCTM
DAC
GIN1
GIN1
Output Data Formatter
VIN+ VIN-
PGA
GIN2
GIN2
VIN-
PGA
+
+
8 bit ADC
10 10
8-BIT ADC
8
8
OUTPUT DATA FORMATTER
VIN+
8
8
GP[7:0]
G[7:0]
VCLAMP V
CLAMP
Offset OFFSET DAC DAC
ABLCTM ABLCTM
BIN1 BIN1
VIN+ IN+ V VIN-VINPGA PGA +
88
BIN2 BIN2
+
8 8-BITADC bit ADC
88
BP[7:0] B[7:0]
DATACLK
DATACLK DATACLK
SOGIN1 SOGIN2 HSYNCIN1 VSYNCIN1
SOGIN1
DATACLK
SOGIN2
HSYNCIN1 VSYNCIN1
Sync
SYNC Processing PROCESSING
AFE Configuration
AFE CONFIGURATION AND and Control CONTROL
HSOUT
HSOUT
HSYNCOUT CLOCKINV
HSYNC VSYNCOUT OUT
CLOCKINV XTAL
IN
Digital PLL
DIGITAL PLL
VSYNCOUT
XCLKOUT
XTAL XTALIN OUT
XCLKOUT
XTALOUT SCL SCL SDA SADDR
SDA SADDR
Serial Interface SERIAL
INTERFACE
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ISL98002
Absolute Maximum Ratings
Voltage on VA, VD, or VX (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V Voltage on VADC, VCOREADC, VPLL, or VCORE (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Voltage on any analog input pin (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VA Voltage on any digital input pin (referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Current into any output pin. . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance JA (C/W) QFN Package (Note 1). . . . . . . . . . . . . . . . . . . . . . . 27 Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . 3.3V 10%, 1.8V 10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, VCORE = VCOREADC = VADC = VPLL = 1.8V, pixel rate = 140MHz for
ISL98002-140, 170MHz for ISL98002-170, fXTAL = 25MHz, TA = +25C, unless otherwise noted.
SYMBOL
PARAMETER
COMMENT
MIN
TYP
MAX
UNIT
FULL CHANNEL CHARACTERISTICS
Conversion Rate ISL98002-140 ISL98002-170 ADC Resolution Missing Codes DNL Differential Non-Linearity (Full-Channel) ISL98002-140 ISL98002-170 INL Integral Non-Linearity (Full-Channel) ISL98002-140 ISL98002-170 Gain Adjustment Range Gain Adjustment Resolution Gain Matching Between Channels Full Channel Offset Error, ABLCTM Enabled Offset Adjustment Range (ABLCTM Enabled or Disabled) Percent of full-scale ADC LSBs, over time and temperature ADC LSBs (See "Automatic Black Level Compensation (ABLCTM) and Gain Control" on page 16) (Note 3) 1.1 1.1 6 8 1 0.125 127 0.5 2.75 3.25 LSB LSB dB Bits % LSB LSB Guaranteed monotonic (Note 3) 0.5 0.5 +1.0/-0.9 +1.0/-0.9 LSB LSB Per Channel 10 10 8 None 140 170 MHz MHz MHz Bits
ANALOG VIDEO INPUT CHARACTERISTICS (RIN, GIN, BIN)
Input Range Input Bias Current Input Capacitance Full Power Bandwidth Programmable DC restore clamp off 0.35 0.7 0.01 5 780 1.4 1 VP-P A pF MHz
INPUT CHARACTERISTICS (SOGIN)
VIH/VIL Input Threshold Voltage Hysteresis Input Capacitance Programmable - see "Register Listing" on page 10 Centered around threshold 0 to 0.3 40 5 V mV pF
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ISL98002
Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, VCORE = VCOREADC = VADC = VPLL = 1.8V, pixel rate = 140MHz for
ISL98002-140, 170MHz for ISL98002-170, fXTAL = 25MHz, TA = +25C, unless otherwise noted. (Continued)
SYMBOL
PARAMETER
COMMENT
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS (HSYNCIN)
VIH/VIL Input Threshold Voltage Hysteresis RIN CIN VIH VIL I Input Impedance Input Capacitance Programmable - see "Register Listing" on page 10 Centered around threshold voltage 0.4 to 3.2 240 1.2 5 V mV k pF
DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINVIN, RESET)
Input HIGH Voltage Input LOW Voltage Input Leakage Current Input Capacitance RESET has a 70k pull-up to VD 10 5 2.0 0.8 V V nA pF
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNCIN)
VT+ VTI Low to High Threshold Voltage High to Low Threshold Voltage Input Leakage Current Input Capacitance 10 5 1.45 0.95 V V nA pF
DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK)
VOH VOL VOH VOL RTRI VOH VOL VA VD VX IA ID IX VADC VCORE VCOREADC VPLL IADC ICORE ICOREADC IPLL Output HIGH Voltage, IO = 16mA Output LOW Voltage, IO = -16mA Output HIGH Voltage, IO = 8mA Output LOW Voltage, IO = -8mA Pull-down to GNDD When Three-state Output HIGH Voltage, IO = 4mA Output LOW Voltage, IO = -4mA Analog 3.3V Supply Voltage Digital 3.3V Supply Voltage Crystal Oscillator 3.3V Supply Voltage Analog 3.3V Supply Current Digital 3.3V Supply Current Crystal Oscillator 3.3V Supply Current ADC Analog 1.8V Supply Voltage Digital 1.8V Supply Voltage ADC Digital 1.8V Supply Voltage PLL 1.8V Supply Voltage ADC Analog 1.8V Supply Current Digital 1.8V Supply Current ADC Digital 1.8V Supply Current PLL 1.8V Supply Current 1.65 1.65 1.65 1.65 With grayscale ramp input 3 3 3 3.3 3.3 3.3 45 5 0.8 1.8 1.8 1.8 1.8 110 70 11 2.25 RP, GP, BP, RS, GS, BS only XCLKOUT only; SDA is open-drain 2.4 0.4 56 2.4 0.4 2.4 0.4 V V
DIGITAL OUTPUT CHARACTERISTICS (R, G, B, HSOUT, HSYNCOUT, VSYNCOUT)
V V k
DIGITAL OUTPUT CHARACTERISTICS (SDA)
V V
POWER SUPPLY REQUIREMENTS
3.6 3.6 3.6 55 22 1.2 2.0 2.0 2.0 2.0 120 80 20 3 V V V mA mA mA V V V V mA mA mA mA
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ISL98002
Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, VCORE = VCOREADC = VADC = VPLL = 1.8V, pixel rate = 140MHz for
ISL98002-140, 170MHz for ISL98002-170, fXTAL = 25MHz, TA = +25C, unless otherwise noted. (Continued)
SYMBOL
PD
PARAMETER
Total Power Dissipation ISL98002-140 ISL98002-170 Standby Mode
COMMENT
With grayscale ramp input With grayscale ramp input ADCs, PLL powered down
MIN
TYP
525 535 35
MAX
575 600 80
UNIT
mW mW mW
AC TIMING CHARACTERISTICS
PLL Jitter Sampling Phase Steps Sampling Phase Tempco Sampling Phase Differential Nonlinearity HSYNC Frequency Range fXTAL fXTALIN tSETUP tHOLD Crystal Frequency Range Frequency Range with External 3.3V Clock Signal Driving XTALIN DATA Valid Before Rising Edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 2) DATA Valid After Rising Edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 2) Degrees out-of-phase 360 10 23 23 1.3 2.0 25 25 (Note 4) 5.6 per step 250 64 1 3 150 27 33.5 ps/C kHz MHz MHz ns ns 450 ps p-p
AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)
fSCL SCL Clock Frequency Maximum Width of a Glitch on SCL That Will 2 XTAL periods min Be Suppressed tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH NOTES: 2. Setup and hold times are specified for a 170MHz DATACLK rate. 3. Linearity tested at room temperature and guaranteed across commercial temperature range by correlation to characterization. 4. Jitter tested at rated frequencies (170MHz, 140MHz) and at minimum frequency (10MHz). SCL LOW to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Clock LOW Time Clock HIGH Time Start Condition Set-up Time Start Condition Hold Time Data In Set-up Time Data In Hold Time Stop Condition Set-up Time Data Output Hold Time 4 XTAL periods min 5 XTAL periods plus SDA's RC time constant 1.3 1.3 0.6 0.6 0.6 100 0 0.6 160 0 80 See comment 400 kHz ns s s s s s s ns ns s ns
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FN6535.0 March 26, 2008
ISL98002
tF
tHIGH
tLOW
tR
SCL tSU:STA tHD:STA SDA IN
tSU:DAT tHD:DAT tSU:STO
tAA SDA OUT
tDH
tBUF
FIGURE 1. 2-WIRE INTERFACE TIMING
DATACLK
DATACLK tSETUP Pixel Data tHOLD
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
HSYNCIN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE's output signals tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
Analog Video In
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
DATACLK 8 DATACLK Pipeline Latency RP/GP/BP[7:0] D0 D1 D2 D3
RS/GS/BS[7:0]
HSOUT
Programmable Width and Polarity
FIGURE 3. OUTPUT MODE
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FN6535.0 March 26, 2008
ISL98002
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE's output signals tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL Analog Video In P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
HSYNCIN
DATACLK 8.5 DATACLK Pipeline Latency GP[7:0] G0 (Yo) G1 (Y1) G2 (Y2)
RP[7:0]
B0 (Uo)
R1 (V1)
B2 (U2)
BP[7:0]
HSOUT
Programmable Width and Polarity
FIGURE 4. 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
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ISL98002 Pinout
ISL98002 (72 LD QFN) TOP VIEW
HSYNCOUT
DATACLK
DATACLK
VSYNCOUT
HSOUT
VCORE
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
NC
R0
R1
R2
R3
R4
R5
R6
R7
VD
VD
VD
V ADC NC VA R IN 1 V ADC VA G IN 1 SOG IN 1 V ADC VA B IN 1 VA R IN 2 G IN 2 SOG IN 2 B IN 2 V COREADC HSYNC IN 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
G0 NC G1 G2 G3 G4 G5 G6 G7 VD VD B0 B1 B2 B3 B4 B5 B6
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 VD
GND
VSYNCIN1
XTALOUT
SADDR
VX
VPLL
RESET
SCL
CLOCKINVIN
XTALIN
VCORE
GND
SDA
NC
NC
VA
8
B7
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FN6535.0 March 26, 2008
ISL98002 Pin Descriptions
SYMBOL
RIN1 GIN1 BIN1 SOGIN1 HSYNCIN1 VSYNCIN1 RIN2 GIN2 BIN2 SOGIN2 CLOCKINVIN RESET XTALIN
QFN PIN #(s)
4 7 11 8 18 27 13 14 16 15 25 28 22
DESCRIPTION
Analog input. Red channel. DC couple or AC couple through 0.1F. Analog input. Green channel. DC couple or AC couple through 0.1F. Analog input. Blue channel. DC couple or AC couple through 0.1F. Analog input. Sync on Green. Connect to GIN through a 0.01F capacitor in series with a 500 resistor. Digital input, 5V tolerant, 240mV hysteresis, 1.2k impedance to GND. Connect to HSYNC signal through a 680 series resistor. Digital input, 5V tolerant, 500mV hysteresis. Connect to VSYNC signal. Analog input. Red channel. DC couple or AC couple through 0.1F. Analog input. Green channel. DC couple or AC couple through 0.1F. Analog input. Blue channel. DC couple or AC couple through 0.1F. Analog input. Sync on Green. Connect to GIN through a 0.01F capacitor in series with a 500 resistor. Digital input, 5V tolerant. When high, inverts the pixel sampling phase by 180. Tie to GND if unused. Digital input, 5V tolerant, active low, 70k pull-up to VD. Take low for at least 1s and then high again to reset the ISL98002. This pin is not necessary for normal use and may be tied directly to the VD supply. Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see "Electrical Specifications" table on page 5 for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see "Electrical Specifications" table on page 5 for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high. Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface. Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface. 3.3V digital output. Red channel, primary pixel data. 56k pull-down when three-stated. 3.3V digital output. Green channel, primary pixel data. 56k pull-down when three-stated. 3.3V digital output. Blue channel, primary pixel data. 56k pull-down when three-stated. 3.3V digital output. Data clock output. Equal to pixel clock rate. 3.3V digital output. Inverse of DATACLK. 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is always purely horizontal sync (without any composite sync signals). 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This output will pass composite sync signals and Macrovision signals if present on HSYNCIN or SOGIN. 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period. Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GNDA with 0.1F. Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GNDD with 0.1F. Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GNDX with 0.1F. Ground return. Internal power for the ADC's analog. Connect to a 1.8V supply and bypass to GND with 0.1F. Internal power for the ADC's digital logic. Connect to a 1.8V supply and bypass to GND with 0.1F. Internal power for core logic. Connect to a 1.8V supply and bypass each pin to GND with 0.1F. Internal power for the PLL's digital logic. Connect to a 1.8V supply and bypass to GND with 0.1F.
XTALOUT
24
SADDR SCL SDA R7 thru R0 G7 thru G0 B7 thru B0 DATACLK DATACLK HSOUT HSYNCOUT
29 31 30 59 thru 66 46 thru 52, 54 36 thru 43 67 68 70 71
VSYNCOUT VA VD VX GND VADC VCOREADC VCORE VPLL NC
72 3, 6, 10, 12, 19 35, 44, 45, 56, 58, 69 21 PAD, 23, 34 1, 5, 9 17 32, 57 26
2, 20, 33, 53, 55 Reserved. Do not connect anything to these pins.
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FN6535.0 March 26, 2008
ISL98002 Register Listing
ADDRESS
0x00
REGISTER (DEFAULT VALUE)
Device ID (read only) SYNC Status (read only)
BIT(S)
3:0 7:4 0 1 2 3 4 5 6 7
FUNCTION NAME
Device Revision Device ID HSYNC1 Active N/A VSYNC1 Active N/A SOG1 Active SOG2 Active PLL Locked CSYNC Detect at Sync Splitter HSYNC Polarity N/A VSYNC Polarity N/A SOG1 TriLevel SOG2 TriLevel N/A HSYNC Threshold
DESCRIPTION
1 = initial silicon, 2 = second revision, etc. 1 = ISL98002 0: HSYNC is Inactive 1: HSYNC is Active Returns 0 0: VSYNC is Inactive 1: VSYNC is Active Returns 0 0: SOG is Inactive 1: SOG is Active 0: SOG is Inactive 1: SOG is Active 0: PLL is unlocked 1: PLL is locked to incoming HSYNC 0: Composite Sync signal not detected 1: Composite Sync signal is detected 0: HSYNC is Active High 1: HSYNC is Active Low Returns 0 0: VSYNC is Active High 1: VSYNC is Active Low Returns 0 0: SOG is BiLevel Sync 1: SOG is TriLevel Sync 0: SOG is BiLevel Sync 1: SOG is TriLevel Sync Returns 0 000 = lowest (0.4V) 011 = default (1.6V) 111 = highest (3.2V) Note: All values referred to voltage at HSYNC input pin, 240mV hysteresis Set to 0 0: HSYNC/VSYNC Glitch Filter Enabled (default) 1: HSYNC/VSYNC Glitch Filter Disabled 0x0 = lowest (0mV) 0x6 = default (120mV) 20mV step size 0xF = highest (300mV) 0: SOG low pass filter disabled 1: SOG low pass filter enabled, 14MHz corner (default) 0: 40mV SOG hysteresis enabled (default) 1: 40mV SOG hysteresis disabled Set to 00.
0x01
0x02
SYNC Polarity (read only)
0 1 2 3 4 5 7:6
0x03
HSYNC Slicer (0x33)
2:0
6:3 7 0x04 SOG Slicer (0x16) 3:0
Reserved Disable Glitch Filter SOG Threshold SOG Filter Enable SOG Hysteresis Disable Reserved
4
5 7:6
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FN6535.0 March 26, 2008
ISL98002 Register Listing (Continued)
ADDRESS
0x05
REGISTER (DEFAULT VALUE)
Input configuration (0x00)
BIT(S)
0 1
FUNCTION NAME
Reserved Input Coupling Set to 0.
DESCRIPTION
0: AC coupled (positive input connected to clamp DAC during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp DAC) 1: DC coupled (+ and - inputs are brought to pads and never connected to clamp DACs). Analog clamp signal is turned off in this mode.
2
RGB/YPbPr
0: RGB inputs Base ABLC target code = 0x00 for R, G, and B) 1: YPbPr inputs Base ABLC target code = 0x00 for G (Y) Base ABLC target code = 0x80 for R (Pr) and B (Pb)
3 4
Sync Type Composite Sync Source
0: Separate HSYNC/VSYNC 1: Composite (from SOG or CSYNC on HSYNC) 0: SOGIN 1: HSYNCIN Note: If Sync Type = 0, the multiplexer will pass HSYNCIN regardless of the state of this bit. 0: DC restore clamping and ABLCTM suspended during COAST 1: DC restore clamping and ABLCTM continue during COAST 0: Interval between HSYNC pulses masked (preventing PLL from seeing Macrovision and any spurious glitches) 1: Interval between HSYNC pulses not masked (Macrovision will cause PLL to lose lock) 0: HSYNCOUT signal is masked (any Macrovision, sync glitches on incoming SYNC are stripped from HSYNCOUT) 1: HSYNCOUT signal is not masked (any Macrovision, sync glitches on incoming SYNC appear on HSYNCOUT) If Sync Mask Disable = 1, HSYNCOUT is not masked. Channel gain, where: gain (V/V) = 0.5 + [7:0]/170 0x00: gain = 0.5V/V (1.4VP-P input = full range of ADC) 0x55: gain = 1.0V/V (0.7VP-P input = full range of ADC) 0xFF: gain = 2.0V/V (0.35VP-P input = full range of ADC)
5
COAST CLAMP enable
6
Sync Mask Disable
7
HSYNCOUT Mask Disable
0x06 0x07 0x08
Red Gain (0x55) Green Gain (0x55) Blue Gain (0x55)
7:0 7:0 7:0
Red Gain Green Gain Blue Gain
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ISL98002 Register Listing (Continued)
ADDRESS
0x09 0x0A 0x0B
REGISTER (DEFAULT VALUE)
Red Offset (0x80) Green Offset (0x80) Blue Offset (0x80)
BIT(S)
7:0 7:0 7:0
FUNCTION NAME
Red Offset Green Offset Blue Offset
DESCRIPTION
ABLCTM enabled: digital offset control. A 1 LSB change in this register will shift the ADC output by 1 LSB. ABLCTM disabled: analog offset control. These bits go to the upper 8-bits of the 10-bit offset DAC. A 1 LSB change in this register will shift the ADC output approximately 1 LSB (Offset DAC range = 0) or 0.5LSBs (Offset DAC range = 1). 0x00 = min DAC value or -0x80 digital offset, 0x80 = mid DAC value or 0x00 digital offset, 0xFF = max DAC value or +0x7F digital offset 0: 1/2 ADC full-scale (1 DAC LSB ~ 1 ADC LSB) 1: 1/4 ADC full-scale (1 DAC LSB ~ 1/2 ADC LSB) Set to 0. These bits are the LSBs necessary for 10-bit manual offset DAC control. Combine with their respective MSBs in registers 0x09, 0x0A, and 0x0B to achieve 10-bit offset DAC control.
0x0C
Offset DAC Configuration (0x00)
0 1 3:2 5:4 7:6
Offset DAC Range Reserved Red Offset DAC LSBs Green Offset DAC LSBs Blue Offset DAC LSBs Unused AFE BW
0x0D
AFE Bandwidth (0x2E)
0 3:1
Value doesn't matter 3dB point for AFE lowpass filter 000b: 100MHz 111b: 780MHz (default) 0x0: Peaking off 0x1: Moderate peaking 0x2: Maximum recommended peaking (default) Values above 2 are not recommended. 14-bit HTOTAL (number of active pixels) value The minimum HTOTAL value supported is 0x200. HTOTAL to PLL is updated on LSB write only.
7:4
Peaking
0x0E 0x0F 0x10
PLL Htotal MSB (0x03) PLL Htotal LSB (0x20) PLL Sampling Phase (0x00)
5:0 7:0 5:0
PLL Htotal MSB PLL Htotal LSB
PLL Sampling Phase Used to control the phase of the ADC's sample point relative to the period of a pixel. Adjust to obtain optimum image quality. One step = 5.625 (1.56% of pixel period). Pre-coast Post-coast Number of lines the PLL will coast prior to the start of VSYNC. Number of lines the PLL will coast after the end of VSYNC.
0x11 0x12
PLL Pre-coast (0x04) PLL Post-coast (0x04)
7:0 7:0
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ADDRESS
0x13
REGISTER (DEFAULT VALUE)
PLL Misc (0x04)
BIT(S)
0 1 2 3 5:4
FUNCTION NAME
PLL Lock Edge HSYNC Reserved Reserved CLKINVIN Pin Disable CLKINVIN Pin Function
DESCRIPTION
0: Lock on trailing edge of HSYNC (default) 1: Lock on leading edge of HSYNC Set to 0 Set to 0 0: CLKINVIN pin enabled (default) 1: CLKINVIN pin disabled (internally forced low) 00: CLKINV (default) 01: External CLAMP (See Note) 10: External COAST 11: External PIXCLK Note: the CLAMP pulse is used to - perform a DC restore (if enabled) - start the ABLCTM function (if enabled), and - update the data to the Offset DACs (always). In the default internal CLAMP mode, the ISL98002 automatically generates the CLAMP pulse. If External CLAMP is selected, the Offset DAC values only change on the leading edge of CLAMP. If there is no internal clamp signal, there will be up to a 100ms delay between when the PGA gain or offset DAC register is written to, and when the PGA or offset DAC is actually updated. Set to 0 Set to 1 Pixel after HSYNCIN trailing edge to begin DC restore and ABLCTM functions. 13-bits. Set this register to the first stable black pixel following the trailing edge of HSYNCIN.
6 7 0x14 DC Restore and ABLCTM starting pixel MSB (0x00) DC Restore and ABLCTM starting pixel LSB (0x03) DC Restore Clamp Width (0x10) 4:0
Reserved Reserved DC Restore and ABLCTM starting pixel (MSB) DC Restore and ABLCTM starting pixel (LSB) DC Restore clamp width (pixels)
0x15
7:0
0x16
7:0
Width of DC restore clamp used in AC-coupled configurations. Has no effect on ABLCTM. Minimum value is 0x02 (a setting of 0x01 or 0x00 will not generate a clamp pulse). 0: ABLCTM enabled (default) 1: ABLCTM disabled Set to 0. Number of black pixels averaged every line for ABLCTM function 00: 16 pixels [default] 01: 32 pixels 10: 64 pixels 11: 128 pixels ABLCTM Time constant (lines) = 2(5+[6:4]) 000 = 32 lines 100 = 256 lines (default) 111 = 4096 lines Set to 0.
0x17
ABLCTM Configuration (0x40)
0 1 3:2
ABLCTM disable Reserved ABLCTM pixel width
6:4
ABLCTM bandwidth
7
Reserved
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ADDRESS
0x18
REGISTER (DEFAULT VALUE)
Output Format (0x00)
BIT(S)
0 1 2 3 4
FUNCTION NAME
Reserved Reserved Reserved UV order (422 mode only) 422 mode Set to 0 Set to 0 Set to 0
DESCRIPTION
0: U0 V0 U2 V2 U4 V4 U6 V6... (default) 1: U0 V1 U2 V3 U4 V5 U6 V7... (X980xx) 0: Data is formatted as 4:4:4 (RGB, default) 1: Data is decimated to 4:2:2 (YUV), blue channel is driven low 0: HSOUT and Pixel Data changes on falling edge of DATACLK (default) 1: HSOUT and Pixel Data changes on rising edge of DATACLK Set to 0 0: Active High (default) 1: Active Low HSOUT width, in pixels. Minimum value is 0x01 0 = Output byte enabled 1 = Output byte three-stated These bits override all other I/O settings Output data pins have 56k pull-down resistors to GND. Set to 1
5
DATACLK Polarity
6 7 0x19 0x1A HSOUT Width (0x10) Output Signal Disable (0x00) 7:0 0
Reserved HSOUT Polarity HSOUT Width Three-state R[7:0]
1 2 3 4 5 6 7 0x1B Power Control (0x00) 0 1 2 3 7:4 0x1C PLL Tuning (0x49) 7:0
Reserved Three-state G[7:0] Reserved Three-state B[7:0] Reserved Three-state DATACLK Three-state DATACLK Red Power-down Green Power-down Blue Power-down PLL Power-down Reserved Reserved
Set to 1
Set to 1 0 = DATACLK enabled 1 = DATACLK three-stated 0 = DATACLK enabled 1 = DATACLK three-stated 0 = Red ADC operational (default) 1 = Red ADC powered down 0 = Green ADC operational (default) 1 = Green ADC powered down 0 = Blue ADC operational (default) 1 = Blue ADC powered down 0 = PLL operational (default) 1 = PLL powered down Set to 0 Use default setting of 0x49 for all PC and video modes except signals coming from an analog VCR. Set to 0x4C for analog videotape compatibility.
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ADDRESS
0x1D
REGISTER (DEFAULT VALUE)
Red ABLC Target (0x00)
BIT(S)
7:0
FUNCTION NAME
Reserved
DESCRIPTION
This is a 2's complement number controlling the target code of the Red ADC output when ABLC is enabled. In RGB mode, the Red ADC output will be servoed to 0x00 + the number in this register (-0x00 to +0x7F). In YPbPr mode, the Red ADC output will be servoed to 0x80 + the number in this register (-0x80 to +0x7F). Note: This register does NOT disable the digital offset adder. Both functions can be used simultaneously. This is a 2's complement number controlling the target code of the Green ADC output when ABLC is enabled. In RGB and YPbPr modes, the Green ADC output will be servoed to 0x00 + the number in this register (-0x00 to +0x7F). Note: This register does NOT disable the digital offset adder. Both functions can be used simultaneously. This is a 2's complement number controlling the target code of the Blue ADC output when ABLC is enabled. In RGB mode, the Blue ADC output will be servoed to 0x00 + the number in this register (-0x00 to +0x7F). In YPbPr mode, the Blue ADC output will be servoed to 0x80 + the number in this register (-0x80 to +0x7F). Note: This register does NOT disable the digital offset adder. Both functions can be used simultaneously. Set to 1000 DC Restore clamp's ON-resistance. Shared for all three channels 0: Infinite (clamp disconnected) (default) 1: 1600 2: 800 3: 533 4: 400 5: 320 6: 267 7: 228 Set to 0
0x1E
Green ABLC Target (0x00)
7:0
Reserved
0x1F
Blue ABLC Target (0x00)
7:0
Reserved
0x23
DC Restore Clamp (0x18)
3:0 6:4
Reserved DC Restore Clamp Impedance
7
Reserved
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ADDRESS
0x25
REGISTER (DEFAULT VALUE)
Sync Separator Control (0x00)
BIT(S)
0
FUNCTION NAME
Three-state Sync Outputs COAST Polarity
DESCRIPTION
0: VSYNCOUT, HSYNCOUT, HSOUT are active (default) 1: VSYNCOUT, HSYNCOUT, HSOUT are in three-state 0: Coast active high (default) 1: Coast active low Set to 0 for internal VSYNC extracted from CSYNC. Set to 0 or 1 as appropriate to match external VSYNC or external COAST. 0: HSOUT's trailing edge is locked to selected HSYNCIN's lock edge. Leading edge moves backward in time as HSOUT width is increased (X980xx default) 1: HSOUT's leading edge is locked to selected HSYNCIN's lock edge. Trailing edge moves forward in time as HSOUT width is increased Set to 0 0: VSYNCOUT is aligned to HSYNCOUT edge, providing "perfect" VSYNC signal (default) 1: VSYNCOUT is "raw" integrator output Set to 0 Set to 0 Set to 0
1
2
HSOUT Lock Edge
3 4
Reserved VSYNCOUT Mode
5 6 7
Reserved Reserved Reserved
Technical Highlights
The ISL98002 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels.
DPLL
All video AFEs must phase lock to an HSYNC signal, supplied either directly or embedded in the video stream (Sync On Green). Historically, this has been implemented as a traditional analog PLL. At SXGA and lower resolutions, an analog PLL solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, VCO ranges and other parameters to find the optimum trade-off for a wide range of pixel rates). As display resolutions and refresh rates have increased, however, the pixel period has shrunk. An XGA pixel at a 60Hz refresh rate has 15.4ns to change and settle to its new value. But at UXGA 75Hz, the pixel period is 4.9ns. Most consumer graphics cards (even the ones with "350MHz" DACs) spend most of that time slewing to the new pixel value. The pixel may settle to its final value with 1ns or less before it begins slewing to the next pixel. In many cases, it rings and never settles at all. Thus precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The ISL98002's DPLL has less than 250ps of jitter, peak-to-peak, and independent of the pixel rate. The DPLL generates 64 phase steps per pixel (vs the industry standard 16
32), for fine, accurate positioning of the sampling point. The crystal-locked NCO inside the DPLL completely eliminates drift due to charge pump leakage, so there is inherently no frequency or phase change across a line. An intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (except for the number of pixels) to lock over a range from interlaced video (10MHz or higher) to UXGA 60Hz (170MHz, with the ISL98002-170). The DPLL eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals.
Automatic Black Level Compensation (ABLCTM) and Gain Control
Traditional video AFEs have an offset DAC prior to the ADC, to both correct for offsets on the incoming video signals and add/subtract an offset for user "brightness control" without sacrificing the 8-bit dynamic range of the ADC. This solution is adequate, but it places significant requirements on the system's firmware, which must execute a loop that detects the black portion of the signal and then serves the offset DACs until that offset is nulled (or produces the desired ADC output code). Once this has been accomplished, the offset (both the offset in the AFE and the offset of the video card generating the signal) is subject to drift (the temperature inside a monitor or projector can easily change +50C) between power-on/offset calibration on a cold morning and the temperature reached once the monitor and the monitor's environment has reached a steady state. Offset can drift significantly over +50C, reducing image quality and
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requiring that the user do a manual calibration once the monitor has warmed up. In addition to drift, many AFEs exhibit interaction between the offset and gain controls. When the gain is changed, the magnitude of the offset is changed as well. This again increases the complexity of the firmware as it tries to optimize gain and offset settings for a given video input signal. Instead of adjusting just the offset then the gain, both have to be adjusted interactively until the desired ADC output is reached. The ISL98002 simplifies offset and gain adjustment and completely eliminates offset drift using its Automatic Black Level Compensation (ABLCTM) function. ABLCTM monitors the black level and continuously adjusts the ISL98002's 10-bit offset DACs to null out the offset. Any offset, whether due to the video source or the ISL98002's analog amplifiers, is eliminated with 10-bit (1/4 of an ADC LSB) accuracy. Any drift is compensated for well before it can have a visible effect. Manual offset adjustment control is still available (an 8-bit register allows the firmware to adjust the offset 64 codes) in exactly 1 ADC LSB increments. Gain is now completely independent of offset (adjusting the gain no longer affects the offset) so there is no longer a need to program the firmware to cope with interactive offset and gain controls. Finally, there should be no concerns over ABLCTM itself introducing visible artifacts; it doesn't. ABLCTM functions at a very low frequency, changing the offset in 1/4 LSB increments, so it can't cause visible brightness fluctuations. Once ABLCTM is locked, if the offset doesn't drift, the DACs won't change. If desired, ABLCTM can be disabled, allowing the firmware to work in the traditional way, with 10-bit offset DACs under the firmware's control.
Functional Description
Inputs
The ISL98002 digitizes analog video inputs in both RGB and Component (YPbPr) formats, with or without embedded sync (SOG).
RGB Inputs
For RGB inputs, the black/blank levels are identical and equal to 0V. The range for each color is typically 0V to 0.7V from black to white. HSYNC and VSYNC are separate signals.
Component YPbPr Inputs
In addition to RGB and RGB with SOG, the ISL98002 has an option that is compatible with the component YPbPr video inputs typically generated by DVD players. While the ISL98002 digitizes signals in these color spaces, it does not perform color space conversion; if it digitizes an RGB signal, it outputs digital RGB, while if it digitizes a YPbPr signal, it outputs digital YCbCr, also called YUV. The Luminance (Y) signal is applied to the Green Channel and is processed in a manner identical to the Green input with SOG described previously. The color difference signals Pb and Pr are bipolar and swing both above and below the black level. When the YPbPr mode is enabled, the black level output for the color difference channels shifts to a mid scale value of 0x80. Setting configuration register 0x05[2] = 1 enables the YPbPr signal processing mode of operation as shown in Table 1.
TABLE 1. YUV MAPPING (4:4:4) INPUT SIGNAL
Y Pb Pr
ISL98002 INPUT CHANNEL
Green Blue Red
ISL98002 OUTPUT ASSIGNMENT
Green Blue Red
OUTPUT SIGNAL
Y0Y1Y2Y3 U0U1U2U3 V0V1V2V3
Gain and Offset Control
To simplify image optimization algorithms, the ISL98002 features fully-independent gain and offset adjustment. Changing the gain does not affect the DC offset, and the weight of an offset DAC LSB does not vary depending on the gain setting. The full-scale gain is set in the three 8-bit registers (0x06-0x08). The ISL98002 can accept input signals with amplitudes ranging from 0.35VP-P to 1.4VP-P. The offset controls shift the entire RGB input range, changing the input image brightness. Three separate registers provide independent control of the R, G, and B channels. Their nominal setting is 0x80, which forces the ADC to output code 0x00 (or 0x80 for the R (Pr) and B (Pb) channels in YPbPr mode) during the back porch period when ABLCTM is enabled.
The ISL98002 can optionally decimate the incoming data to provide a 4:2:2 output stream (configuration register 0x18[4] = 1), as shown in Table 2.
TABLE 2. YUV MAPPING (4:2:2) INPUT SIGNAL
Y Pb Pr
ISL98002 INPUT CHANNEL
Green Blue Red
ISL98002 OUTPUT ASSIGNMENT
Green Blue Red
OUTPUT SIGNAL
Y0Y1Y2Y3 driven low U0V0U2V2
There is also a "compatibility mode" (enabled by setting bit 3 of register 0x18 to a 1) that outputs the U and V data with the format used by the previous generation ("X980xx") series of AFEs, shown in Table 3.
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TABLE 3. YUV MAPPING (4:2:2) INPUT SIGNAL
Y Pb Pr
ISL98002 INPUT CHANNEL
Green Blue Red
ISL98002 OUTPUT ASSIGNMENT
Green Blue Red
OUTPUT SIGNAL
Y0Y1Y2Y3 driven low U0V1U2V3
of HSYNC. If register 0x05[5] = 0 (the default), the clamp will not be applied while the DPLL is coasting, preventing any clamp voltage errors from composite sync edges, equalization pulses, or Macrovision signals. After the trailing edge of HSYNC, the DC restore clamp is turned on after the number of pixels specified in the DC Restore and ABLCTM Starting Pixel registers (0x14 and 0x15) has been reached. The clamp is applied for the number of pixels specified by the DC Restore Clamp Width Register (0x16). The clamp can be applied to the back porch of the video, or to the front porch (by increasing the DC Restore and ABLCTM Starting Pixel registers so all the active video pixels are skipped). If DC-coupled operation is desired, the input to the ADC will be the difference between the input signal (RIN, for example) and that channel's ground reference (RGBGND in that example).
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled (see register 0x05[1]). AC coupling is usually preferred since it allows video signals with substantial DC offsets to be accurately digitized. The ISL98002 provides a complete internal DC-restore function, including the DC restore clamp (see Figure 5) and programmable clamp timing (registers 0x14, 0x15, 0x16, and 0x23). When AC-coupled, the DC restore clamp is applied at every line, a programmable number of pixels after the trailing edge
DC RESTORATION
AUTOMATIC BLACK LEVEL COMPENSATION (ABLCTM) LOOP
FIXED OFFSET CLAMP GENERATION DC RESTORE CLAMP DAC VCLAMP ABLCTM TO ABLC BLOCK OFFSET DAC 10
10
OFFSET CONTROL REGISTERS 0X00
10
8 ABLCTM ABLCTM
8 FIXED OFFSET 8
VIN+ R(GB)IN R(GB)GND VINPGA INPUT BANDWIDTH 8-BIT ADC 8
8
TO OUTPUT FORMATTER
BANDWIDTH CONTROL
FIGURE 5. VIDEO FLOW (INCLUDING ABLCTM)
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SOG
For component YPbPr signals, the sync signal is embedded on the Y-Channel's video, which is connected to the green input, hence the name SOG (Sync on Green). The horizontal sync information is encoded onto the video input by adding the sync tip during the blanking interval. The sync tip level is typically 0.3V below the video black level. To minimize the loading on the Green channel, the SOG input for each of the Green channels should be AC-coupled to the ISL98002 through a series combination of a 10nF capacitor and a 500 resistor. Inside the ISL98002, a window comparator compares the SOG signal with an internal 4-bit programmable threshold level reference ranging from 0mV to 300mV below the minimum sync level. The SOG threshold level, hysteresis, and low-pass filter is programmed via register 0x04. If the Sync On Green function is not needed, the SOGIN pin(s) may be left unconnected. The ISL98002 has SYNC activity detect functions to help the firmware determine which sync source is available.
Macrovision
The ISL98002 automatically detects the presence of Macrovision-encoded video. When Macrovision is detected, it generates a mask signal that is ANDed with the incoming SOG CSYNC signal to remove the Macrovision before the HSYNC goes to the PLL. No additional programming is required to support Macrovision. If desired (it is never necessary in normal operation), this function can be disabled by setting the Sync Mask Disable (register 0x05 bit 6) to a 1. The mask signal is also applied to the HSYNCOUT signal. When Sync Mask Disable = 0, any Macrovision present on the incoming sync will not be visible on HSYNCOUT. If the application requires the Macrovision pulses to be visible on HSYNCOUT, set the HSYNCOUT Mask Disable bit (register 0x05 bit 7).
SYNC Processing
The ISL98002 can process sync signals from 3 different sources: discrete HSYNC and VSYNC, composite sync on the HSYNC input, or composite sync from a Sync On Green (SOG) signal embedded on the Green video input. Due to the reduced number of pins in the 72 Ld QFN package, Channel-2 on the ISL98002 only accepts sync input on SOG.
Headswitching from Analog Videotape Signals
Occasionally this AFE may be used to digitize signals coming from analog videotape sources. The most common example of this is a Digital VCR (which for best signal quality would be connected to this AFE with a component YPbPr
ACTIVITY 0X01[6:0] AND POLARITY 0X02[5:0] DETECT
CSYNC SOURCE HSYNC1 SLICER 0X03[2:0] SOG SLICER 0X1C HSYNCIN 00, 10, 11: HSYNCIN 0X05[4:3 ] 01: SOGIN VSYNCIN VSYNC IN 0: VSYNCIN COAST GENERATION 0X11, 0X12, 0X13[2] SYNC SPLITTER VSYNC SYNC TYPE 1: SYNC SPLTR
HSYNCOUT
HSYNCIN
SOGIN
SOGIN
VSYNC OUT 0X05[3]
R[7:0] PIXEL DATA FROM AFE 24 G[7:0] OUTPUT FORMATTER 0X18, 0X19, 0X1A
CLOCKINVIN PLL XTALIN 0X0E THROUGH 0X13 PIXCLK XTALOUT 0: /1 0X13 [6] /2 1: /2 XTALCLOCKOUT HS B[7:0]
DATACLK DATACLK HSOUT
FIGURE 6. SYNC FLOW
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connection). If the digital VCR is playing an older analog VHS tape, the sync signals from the VCR may contain the worst of the traditional analog tape artifacts: headswitching. Headswitching is traditionally the enemy of PLLs with large capture ranges, because a headswitch can cause the HSYNC period to change by as much as 90%. To the PLL, this can look like a frequency change of -50% to greater than +900%, causing errors in the output frequency (and obviously the phase) to change. Subsequent HSYNCs have the correct, original period, but most analog PLLs will take dozens of lines to settle back to the correct frequency and phase after a headswitch disturbance. This causes the top of the image to "tear" during normal playback. In "trick modes" (fast forward and rewind), the HSYNC signal has multiple headswitch-like discontinuities, and many PLLs never settle to the correct value before the next headswitch, rendering the image completely unintelligible. Intersil's DPLL has the capability to correct large phase changes almost instantly by maximizing the phase error gain while keeping the frequency gain relatively low. This is done by changing the contents of register 0x1C to 0x4C. This increases the phase error gain to 100%. Because a phase setting this high will slightly increase jitter, the default setting (0x49) for register 0x1C is recommended for all other sync sources. change in that channel's actual PGA gain. If there is no regular HSYNC/SOG source, or if the external clamp option is enabled (register 0x13[5:4]) but there is no external clamp signal being generated, it may take up to 100ms for a write to the Gain register to update the PGA. This is not an issue in normal operation with RGB and YPbPr signals.
Offset DAC
The ISL98002 features a 10-bit Digital-to-Analog Converter (DAC) per channel to provide extremely fine control over the full channel offset. The DAC is placed after the PGA to eliminate interaction between the PGA (controlling "contrast") and the Offset DAC (controlling "brightness"). In normal operation, the Offset DAC is controlled by the ABLCTM circuit, ensuring that the offset is always reduced to sub-LSB levels (see "ABLCTM" for more information). When ABLCTM is enabled, the Offset registers (0x09, 0x0A, 0x0B) control a digital offset added to or subtracted from the output of the ADC. This mode provides the best image quality and eliminates the need for any offset calibration. If desired, ABLCTM can be disabled (0x17[0] = 1) and the Offset DAC programmed manually, with the 8 most significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least significant bits in register 0x0C[7:2]. The default Offset DAC range is 127 ADC LSBs. Setting 0x0C[0] = 1 reduces the swing of the Offset DAC by 50%, making 1 Offset DAC LSB the weight of 1/8th of an ADC LSB. This provides the finest offset control and applies to both ABLCTM and manual modes.
PGA
The ISL98002's Programmable Gain Amplifier (PGA) has a nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). The transfer function is calculated in Equation 1: V GainCode Gain --- = 0.5 + --------------------------- V 170
(EQ. 1)
Automatic Black Level Compensation (ABLCTM)
ABLCTM is a function that continuously removes all offset errors from the incoming video signal by monitoring the offset at the output of the ADC and servoing the 10-bit analog DAC to force those errors to zero. When ABLCTM is enabled, the user offset control is a digital adder, with 8-bit resolution (see Table 4). When the ABLCTM function is enabled (0x17[0] = 0), the ABLC function is executed every line after the trailing edge of HSYNC. If register 0x05[5] = 0 (the default), the ABLCTM function will be not be triggered while the DPLL is coasting,
where GainCode is the value in the Gain register for that particular color. Note that for a gain of 1V/V, the GainCode should be 85 (0x55). This is a different center value than the 128 (0x80) value used by some other AFEs, so the firmware should take this into account when adjusting gains. The PGAs are updated by the internal clamp signal once per line. In normal operation, this means that there is a maximum delay of one HSYNC period between a write to a Gain register for a particular color and the corresponding
TABLE 4. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT OFFSET DAC RANGE 0X0C[0]
0 1 0 1
10-BIT OFFSET DAC RESOLUTION
0.25 ADC LSBs (0.68mV) 0.125 ADC LSBs (0.34mV) 0.25 ADC LSBs (0.68mV) 0.125 ADC LSBs (0.34mV)
ABLCTM 0x17[0]
0 (ABLC on) 0 (ABLC on) 1 (ABLC off) 1 (ABLC off)
USER OFFSET CONTROL RESOLUTION USING REGISTERS 0x09 - 0X0B ONLY (8-BIT OFFSET CONTROL)
1.0 ADC LSB (digital offset control) 1.0 ADC LSB (digital offset control) 1.0 ADC LSB (analog offset control) 0.5 ADC LSB (analog offset control)
USER OFFSET CONTROL RESOLUTION USING REGISTERS 0X09 - 0x0B AND 0X0C[7:2](10-BIT OFFSET CONTROL)
N/A N/A 0.25 ADC LSB (analog offset control) 0.125 ADC LSB (analog offset control)
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preventing any composite sync edges, equalization pulses, or Macrovision signals from corrupting the black data and potentially adding a small error in the ABLCTM accumulator. After the trailing edge of HSYNC, the start of ABLCTM is delayed by the number of pixels specified in registers 0x14 and 0x15. After that delay, the number of pixels specified by register 0x17[3:2] are averaged together and added to the ABLCTM's accumulator. The accumulator stores the average black levels for the number of lines specified by register 0x17[6:4], which is then used to generate a 10-bit DAC value. The default values provide excellent results with offset stability and absolute accuracy better than 1 ADC LSB for most input signals. Relative to a 5V input, the hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer step size will be 400mV*5V/3.3V = 600mV per step.
SOG Slicer
The SOG input has programmable threshold, 40mV of hysteresis, and an optional low pass filter that can be used to remove high frequency video spikes (generated by overzealous video peaking in a DVD player, for example) that can cause false SOG triggers. The SOG threshold sets the comparator threshold relative to the sync tip (the bottom of the SOG pulse).
SYNC Status and Polarity Detection
The SYNC Status register (0x01) and the SYNC Polarity register (0x02) continuously monitor all 3 sync inputs (VSYNCIN, HSYNCIN, and SOGIN) and report their status. However, accurate sync activity detection is always a challenge. Noise and repetitive video patterns on the Green channel may look like SOG activity when there actually is no SOG signal, while non-standard SOG signals and trilevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected. As a consequence, not all of the activity detect bits in the ISL98002 are correct under all conditions. Table 5 on page 22 shows how to use the SYNC Status register (0x01) to identify the presence and type of sync source. The firmware should go through the table in the order shown, stopping at the first entry that matches the activity indicators in the SYNC Status register. Final validation of composite sync sources (SOG or Composite sync on HSYNC) should be done by setting the Input Configuration register (0x05) to the composite sync source determined by Table 5, and confirming that the CSYNC detect bit is set. The accuracy of the Trilevel Sync Detect bit can be increased by multiple reads of the Trilevel Sync detect bit. See "TriLevel Sync Detect" on page 22 for more details. For best SOG operation, the SOG low pass filter (register 0x04[4] should always be enabled to reject the high frequency peaking often seen on video signals.
ADC
The ISL98002 features 3 fully differential, high-speed 8-bit ADCs.
Clock Generation
A Digital Phase Lock Loop (DPLL) is employed to generate the pixel clock frequency. The HSYNC input and the external XTAL provide a reference frequency to the PLL. The PLL then generates the pixel clock frequency that is equal to the incoming HSYNC frequency times the HTOTAL value programmed into registers 0x0E and 0x0F. The stability of the clock is very important and correlates directly with the quality of the image. During each pixel time transition, there is a small window where the signal is slewing from the old pixel amplitude and settling to the new pixel value. At higher frequencies, the pixel signal transitions at a faster rate, which makes the stable pixel time even smaller. Any jitter in the pixel clock reduces the effective stable pixel time and thus the sample window in which pixel sampling can be made accurately.
Sampling Phase
The ISL98002 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. The sampling phase register is 0x10.
HSYNC Slicer
To further minimize jitter, the HSYNC inputs are treated as analog signals, and brought into a precision slicer block with thresholds programmable in 400mV steps with 240mV of hysteresis, and a subsequent digital glitch filter that ignores any HSYNC transitions within 100ns of the initial transition. This processing greatly increases the AFE's rejection of ringing and reflections on the HSYNC line and allows the AFE to perform well, even with pathological HSYNC signals. Voltages given previously and in the "HSYNC Slicer" on page 21 (register description), are with respect to a 3.3V sync signal at the HSYNCIN input pin. To achieve 5V compatibility, a 680 series resistor should be placed between the HSYNC source and the HSYNCIN input pin. 21
HSYNC and VSYNC Activity Detect
Activity on these bits always indicates valid sync pulses, so they should have the highest priority and be used even if the SOG activity bit is also set.
SOG Activity Detect
The SOG Activity Detect bit monitors the output of the SOG slicer, looking for 64 consecutive pulses with the same period and duty cycle. If there is no signal on the Green (or Y) channel, the SOG slicer will clamp the video to a DC level and will reject any sporadic noise. There should be no false positive SOG detects if there is no video on Green (or Y-Channel).
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If there is video on Green (or Y-Channel) with no valid SOG signal, the SOG activity detect bit may sometimes report false positives (it will detect SOG when no SOG is actually present). This is due to the presence of video with a repetitive pattern that creates a waveform similar to SOG. For example, the desktop of a PC operating system is black during the front porch, horizontal sync, and back porch, then increases to a larger value for the video portion of the screen. This creates a repetitive video waveform very similar to SOG that may falsely trigger the SOG Activity detect bit. However, in these cases where there is active video without SOG, the SYNC information will be provided either as separate H and V sync on HSYNCIN and VSYNCIN, or composite sync on HSYNCIN. HSYNCIN and VSYNCIN should therefore be used to qualify SOG. The SOG Active bit should only be considered valid if HSYNC Activity Detect = 0. Note: Some pattern generators can output HSYNC and SOG simultaneously, in which case both the HSYNC and the SOG activity bits will be set, and valid. Even in this case, however, the monitor should still choose HSYNC over SOG.
TriLevel Sync Detect
Unlike SOG detect, the TriLevel Sync Detect function does not check for 64 consecutive trilevel pulses in a row, and is therefore less robust than the SOG detect function. It will report false positives for SOG-less video for the same reasons the SOG activity detect does, and should therefore be qualified with both HSYNC and SOG. TriLevel Sync Detect should only be considered valid if HSYNC Activity Detect = 0 and SOG Activity Detect = 1. If there is a SOG signal, the TriLevel Detect bit will operate correctly for standard trilevel sync levels (600mVP-P). In some real-world situations, the peak-to-peak sync amplitude may be significantly smaller, sometimes 300mVp-p or less. In these cases the sync slicer will continue to operate correctly, but the TriLevel Detect bit may not be set. Trilevel detection accuracy can be enhanced by polling the trilevel bit multiple times. If HSYNC is inactive, SOG is present, and the TriLevel Sync Detect bit is read as a 1, there is a high likelihood there is trilevel sync.
TABLE 5. SYNC SOURCE DETECTION TABLE HSYNC DETECT
1 1 0
VSYNC DETECT
1 0 0
SOG DETECT
X X 1
TRILEVEL DETECT
X X 0 Sync is on HSYNC and VSYNC
RESULT
Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on HSYNC and confirm that CSYNC detect bit is set. Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude is too low to set TriLevel Detect bit. Use video mode table to determine if this video mode is likely to have TriLevel sync, and set clamp start, width values appropriately if it is. Sync is composite sync on SOG. Sync is likely to be trilevel. No valid sync sources on any input.
0 0
0 0
1 0
1 X
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CSYNC Present
If a composite sync source (either CSYNC on HSYNC or SOG) is selected through bits 3 and 4 of register 0x05, the CSYNC Present bit in register 0x01 should be set. CSYNC Present detects the presence of a low frequency, repetitive signal inside HSYNC, which indicates a VSYNC signal. The CSYNC Present bit should be used to confirm that the signal being received is a reliable composite sync source.
HSOUT
HSOUT is generated by the ISL98002's control logic and is synchronized to the output DATACLK and the digital pixel data on the output databus. Its trailing edge is aligned with pixel 0. Its width, in units of pixels, is determined by register 0x19, and its polarity is determined by register 0x18[7]. As the width is increased, the trailing edge stays aligned with pixel 0, while the leading edge is moved backwards in time relative to pixel 0. HSOUT is used by the scaler to signal the start of a new line of pixels. The HSOUT Width register (0x19) controls the width of the HSOUT pulse. The pulse width is nominally 1 pixel clock period times the value in this register.
SYNC Output Signals
The ISL98002 has 2 types of SYNC signals, HSYNCOUT and VSYNCOUT, and HSOUT. HSYNCOUT and VSYNCOUT are buffered versions of the incoming sync signals; no synchronization is done. These signals are used for mode detection. HSOUT is generated by the ISL98002's logic and is synchronized to the output DATACLK and the digital pixel data on the output databus. HSOUT is used to signal the start of a new line of digital data. Both HSYNCOUT and VSYNCOUT (including the sync separator function) remain active in power-down mode. This allows them to be used in conjunction with the Sync Status registers to detect valid video without powering up the ISL98002.
Crystal Oscillator
An external 22MHz to 27MHz crystal supplies the low-jitter reference clock to the DPLL. The absolute frequency of this crystal within this range is unimportant, as is the crystal's temperature coefficient, allowing use of less expensive, lower-grade crystals. As an alternative to a crystal, the XTALIN pin can be driven with a 3.3V CMOS-level external clock source at any frequency between 22MHz and 33.5MHz. The ISL98002's jitter specification assumes a low-jitter crystal source. If the external clock source has increased jitter, the sample clock generated by the DPLL may exhibit increased jitter as well.
HSYNCOUT
HSYNCOUT is an unmodified, buffered version of the incoming HSYNCIN or SOGIN signal of the selected channel, with the incoming signal's period, polarity, and width to aid in mode detection. HSYNCOUT will be the same format as the incoming sync signal: either horizontal or composite sync. If a SOG input is selected, HSYNCOUT will output the entire SOG signal, including the VSYNC portion, pre- and post-equalization pulses if present, and Macrovision pulses if present. HSYNCOUT remains active when the ISL98002 is in power-down mode. HSYNCOUT is generally used for mode detection.
EMI Considerations
There are two possible sources of EMI on the ISL98002 as explained in the following:: Crystal Oscillator - The EMI from the crystal oscillator is negligible. This is due to an amplitude-regulated, low voltage sine wave oscillator circuit, instead of the typical high-gain square wave inverter-type oscillator, so there are no harmonics. Note: The crystal oscillator is not a significant source of EMI. Digital Output Switching - This is the largest potential source of EMI. However, the EMI is determined by the PCB layout and the loading on the databus. The way to control this is to put series resistors on the output of all the digital pins (as our demo board and reference circuits show). These resistors should be as large as possible, while still meeting the setup and hold timing requirements of the scaler. We recommend starting with 22. If the databus is heavily loaded (long traces, many other part on the same bus), this value may need to be reduced. If the databus is lightly loaded, it may be increased. Intersil's recommendations to minimize EMI are: * Minimize the databus trace length * Minimize the databus capacitive loading. If EMI is a problem in the final design, increase the value of the digital output series resistors to reduce slew rates on the bus. This can only be done as long as the scaler's setup and hold timing requirements continue to be met.
VSYNCOUT
VSYNCOUT is an unmodified, buffered version of the incoming VSYNCIN signal of the selected channel, with the original VSYNC period, polarity, and width to aid in mode detection. If a SOG input is selected, this signal will output the VSYNC signal extracted by the ISL98002's sync slicer. Extracted VSYNC will be the width of the embedded VSYNC pulse plus pre- and post-equalization pulses (if present). Macrovision pulses from an NTSC DVD source will lengthen the width of the VSYNC pulse. Macrovision pulses from other sources (PAL DVD or videotape) may appear as a second VSYNC pulse encompassing the width of the Macrovision. See the "Macrovision" on page 19 for more information. VSYNCOUT (including the sync separator function) remains active in power-down mode. VSYNCOUT is generally used for mode detection, start of field detection, and even/odd field detection.
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Reducing Power Dissipation
It is possible to reduce the total power consumption of the ISL98002 in applications where power is a concern. There are several techniques that can be used to reduce power consumption: * Buffering Digital Outputs. Switching data output pins into a capacitive bus can consume significant current. The higher the capacitance on the external databus, the higher the switching current. To minimize current consumption inside the ISL98002, minimize bus capacitance and/or insert data buffers such as the SN64AVC16827 between the ISL98002's data outputs and the external databus. * Internal Reference Frequency. The crystal frequency is multiplied by the value in register 0x2B to generate an internal high frequency reference clock. This internal frequency should be set to 400MHz 10% for minimum power consumption. For example, for a 33MHz frequency at XTALIN, register 0x2B should be set to a value of 0x0C to minimize power. Communication is accomplished in three steps: 1. The Host selects the ISL98002 it wishes to communicate with. 2. The Host writes the initial ISL98002 Configuration Register address it wishes to write to or read from. 3. The Host writes to or reads from the ISL98002's Configuration Register. The ISL98002's internal address pointer auto increments, so to read registers 0x00 through 0x1B, for example, one would write 0x00 in Step 2, then repeat Step 3 28x, with each read returning the next register value. The ISL98002 has a 7-bit address on the serial bus. The upper 6-bits are permanently set to 100110, with the lower bit determined by the state of pin 29. This allows two ISL98002s to be independently controlled while sharing the same bus. The bus is nominally inactive, with SDA and SCL high. Communication begins when the host issues a START command by taking SDA low while SCL is high (see Figure 7). The ISL98002 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. The host then transmits the 7-bit serial address plus a R/W bit, indicating if the next transaction will be a Read (R/W = 1) or a Write (R/W = 0). If the address transmitted matches that of any device on the bus, that device must respond with an ACKNOWLEDGE (see Figure 8). Once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. Communication with the selected device in the selected direction (read or write) is ended by a STOP command, where SDA rises while SCL is high (see Figure 7), or a second START command, which is commonly used to reverse data direction without relinquishing the bus. Data on the serial bus must be valid for the entire time SCL is high (see Figure 9). To achieve this, data being written to the ISL98002 is latched on a delayed version of the rising edge of SCL. SCL is delayed and deglitched inside the ISL98002 for three crystal clock periods (120ns for a 25MHz crystal) to eliminate spurious clock pulses that could disrupt serial communication. When the contents of the ISL98002 are being read, the SDA line is updated after the falling edge of SCL, delayed and deglitched in the same manner.
Standby Mode
The ISL98002 can be placed into a low power standby mode by writing a 0x0F to register 0x1B, powering down the triple ADCs, the DPLL, and most of the internal clocks. To allow input monitoring and mode detection during power-down, the following blocks remain active: * Serial interface (including the crystal oscillator) to enable register read/write activity * Activity and polarity detect functions (registers 0x01 and 0x02) * The HSYNCOUT and VSYNCOUT pins (for mode detection)
Initialization
The ISL98002 initializes with default register settings for an AC-coupled, RGB input.
Reset
The ISL98002 has a Power-On Reset (POR) function that resets the chip to its default state when power is initially applied, including resetting all the registers to their default settings as described in the "Register Listing" beginning on page 10. The external RESET pin duplicates the reset function of the POR without having to cycle the power supplies. The RESET pin does not need to be used in normal operation and can be tied high.
ISL98002 Serial Communication
Overview
The ISL98002 uses a 2-wire serial bus for communication with its host. SCL is the Serial Clock line, driven by the host, and SDA is the Serial Data line, which can be driven by all devices on the bus. SDA is open drain to allow multiple devices to share the same bus simultaneously.
Configuration Register Write
Figure 10 shows two views of the steps necessary to write one or more words to the Configuration Register.
Configuration Register Read
Figure 11 shows two views of the steps necessary to read one or more words from the Configuration Register.
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ISL98002
SCL
SDA START STOP
FIGURE 7. VALID START AND STOP CONDITIONS
SCL FROM HOST DATA OUTPUT FROM TRANSMITTER
1
8
9
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
SCL
SDA DATA STABLE DATA CHANGE DATA STABLE
FIGURE 9. VALID DATA CHANGES ON THE SDA BUS
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START Command
ISL98002 Serial Bus 1 0 0 1 1 0 A (pin 29) R/W
Signals the beginning of serial I/O ISL98002 Serial Bus Address Write
This is the 7-bit address of the ISL98002 on the 2-wire bus. The address is 0x4C if pin 29 is low, 0x4D if pin 29 is high. Shift this value left to when adding the R/W bit.
0
ISL98002 Register Address Write A7 A6 A5 A4 A3 A2 A1 A0
This is the address of the ISL98002's configuration register that the following byte will be written to.
D7
D6
D5
D4
D3
D2
D1
D0
ISL98002 Register Data Write(s)
This is the data to be written to the ISL98002's configuration register. Note: The ISL98002's Configuration Register's address pointer auto increments after each data write: repeat this step to write multiple sequential bytes of data to the Configuration Register.
(Repeat if desired)
STOP Command
S T Serial Bus A R Address T 1 0 0 1 1 0A0 A C K Register Address aaaaaaaa A C K Data Write* dddddddd A C K S T O P
Signals the ending of serial I/O
Signals from the Host SDA Bus Signals from the ISL98002
* The data write step may be repeated to write to the ISL98002's Configuration Register sequentially, beginning at the Register Address written in the previous step.
FIGURE 10. CONFIGURATION REGISTER WRITE
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START Command
ISL98002 Serial Bus 1 0 0 1 1 0 A (pin 29) R/W
Signals the beginning of serial I/O ISL98002 Serial Bus Address Write
This is the 7-bit address of the ISL98002 on the 2-wire bus. The address is 0x4C if pin 29 is low, 0x4D if pin 29 is high. R/W = 0, indicating next transaction will be a write.
0
ISL98002 Register Address Write A7 A6 A5 A4 A3 A2 A1 A0
This sets the initial address of the ISL98002's configuration register for subsequent reading. Ends the previous transaction and starts a new one
START Command
ISL98002 Serial Bus 1 0 0 1 1 0 A (pin 29) R/W
ISL98002 Serial Bus Address Write
This is the 7-bit address of the ISL98002 on the 2-wire bus. The address is 0x4C if pin 29 is low, 0x4D if pin 29 is high. R/W = 1, indicating next transaction(s) will be a read.
1
D7
D6
D5
D4
D3
D2
D1
D0
ISL98002 Register Data Read(s)
This is the data read from the ISL98002's configuration register. Note: The ISL98002's Configuration Register's address pointer auto increments after each data read: repeat this step to read multiple sequential bytes of data from the Configuration Register.
(Repeat if desired)
STOP Command
S T Serial Bus A R Address T 1 0 0 1 1 0A0 A C K R E S T Serial Bus A Address R T 1 0 0 1 1 0A1 A C K
Signals the ending of serial I/O
Signals from the Host
Register Address aaaaaaaa
Data Read*
SDA Bus Signals from the ISL98002
S T O AP C K
* The data read step may be repeated to read from the ISL98002's Configuration Register sequentially, beginning at the Register Address written in the previous two steps.
Adddddddd C K
FIGURE 11. CONFIGURATION REGISTER READ
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ISL98002 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L72.10x10
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 0.20 0.30 5.85 5.85 0.18 MIN 0.80 NOMINAL 0.90 0.02 0.65 0.20 REF 0.25 10.00 BSC 9.75 BSC 6.00 10.00 BSC 9.75 BSC 6.00 0.50 BSC 0.40 72 18 18 0.60 12 0.50 6.15 6.15 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8, 10 2 3 3 9 9 Rev. 1 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VNND-3 except for the "L" min dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 28
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