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| SSM2761P-A N-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY Lower On-resistance Fast Switching Characteristic Simple Drive Requirement RoHS Compliant D BVDSS RDS(ON) ID 650V 1 10A G S DESCRIPTION The TO-220 package is universally preferred for all commercialindustrial applications. The device is suited for DC-DC ,AC-DC converters for power applications. G Pb-free; RoHS-compliant D TO-220 S ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TC=25 ID@TC=100 IDM PD@TC=25 IAR TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, V GS @ 10V Continuous Drain Current, V GS @ 10V Pulsed Drain Current 1 Rating 650 30 10 4.4 18 104 0.8 10 -55 to 150 -55 to 150 Units V V A A A W W/ A Total Power Dissipation Linear Derating Factor Avalanche Current Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 1.2 62 Units /W /W 05/25/2007 Rev.1.00 www.SiliconStandard.com 1 SSM2761P-A ELECTRICAL CHARACTERISTICS @Tj=25oC(unless otherwise specified) Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=1mA Min. 650 2 - Typ. 0.6 4.5 53 10 15 16 20 82 36 320 8 Max. Units 1 4 10 100 100 85 V V/ V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C) o o VGS=10V, ID=3.5A VDS=VGS, ID=250uA VDS=10V, ID=3.5A VDS=600V, VGS=0V VDS=480V, VGS=0V VGS=30V ID=10A VDS=520V VGS=10V VDD=320V ID=10A RG=10,VGS=10V RD=32 VGS=0V VDS=15V f=1.0MHz Gate-Source Leakage Total Gate Charge 3 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 3 2770 4430 Source-Drain Diode Symbol VSD trr Qrr Notes: 1.Pulse width limited by safe operating area. o 2.Starting Tj=25 C , VDD=50V , L=1.2mH , RG=25 , IAS=10A. Parameter Forward On Voltage 3 3 Test Conditions IS=10A, VGS=0V IS=10A, VGS=0V, dI/dt=100A/s Min. - Typ. 610 8.64 Max. Units 1.5 V ns C Reverse Recovery Time Reverse Recovery Charge 3.Pulse width <300us , duty cycle <2%. 05/25/2007 Rev.1.00 www.SiliconStandard.com 2 SSM2761P-A 12 9 T C =25 C ID , Drain Current (A) 9 o 10V 6.0V 5.5V ID , Drain Current (A) 6 T C =150 C o 10V 6.0V 5.5V 5.0V 6 5.0V 3 3 V G =4.0V V G =4.0V 0 0 5 10 15 20 25 0 0 10 20 30 40 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1.2 2.4 I D =3.5A V G =10V 1.1 1.8 Normalized BVDSS (V) Normalized RDS(ON) 1 1.2 0.9 0.6 0.8 -50 0 50 100 150 0 -50 0 50 100 150 T j , Junction Temperature ( o C) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 5 100 10 4 1 T j = 150 o C T j = 25 o C VGS(th) (V) 1.1 1.3 IS (A) 3 0.1 2 0.01 0.1 0.3 0.5 0.7 0.9 1 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 05/25/2007 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 3 www.SiliconStandard.com SSM2761P-A f=1.0MHz 16 10000 VGS , Gate to Source Voltage (V) I D =10A 12 C iss V DS =330V V DS =410V V DS =520V C (pF) 8 100 C oss 4 C rss 0 0 20 40 60 80 1 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthjc) 10 0.2 ID (A) 10us 100us 1 0.1 0.1 0.05 0.02 PDM 0.01 1ms T C =25 C Single Pulse o t T Single Pulse 10ms 100ms Duty factor = t/T Peak Tj = PDM x Rthjc + T C 0 0.01 1 10 100 1000 10000 0.00001 0.0001 0.001 0.01 0.1 1 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 10V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 05/25/2007 Rev.1.00 Fig 12. Gate Charge Waveform 4 www.SiliconStandard.com SSM2761P-A Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 05/25/2007 Rev.1.00 www.SiliconStandard.com 5 |
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