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| MLX71122 300 to 930MHz FSK/FM/ASK Receiver Features ! ! ! ! ! ! ! ! ! ! ! ! ! ! Programmable PLL synthesizer 8-channel preconfigured or fully programmable SPI mode Double super-heterodyne receiver architecture with 2nd mixer as image rejection mixer Reception of FSK, FM and ASK modulated signals Low shut-down and operating currents AFC - automatic frequency correction AGC - automatic gain control On-chip IF filter Fully integrated FSK/FM demodulator RSSI for level indication and ASK detection 2nd order low-pass data filter Positive and negative peak detectors Data slicer (with averaging or peak-detector adaptive threshold) 32-pin Quad Flat No-Lead Package (QFN) Ordering Information Part Number MLX71122 Application Examples General Description The MLX71122 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architecture. It is designed to receive FSK and ASK modulated RF signals either in 8 predefined frequency channels or frequency programmable via a 3-wire serial programming interface (SPI). The IC is designed for a variety of applications, for example in the European bands at 433MHz and 868MHz or for the use in North America or Asia, e.g. at 315MHz, 447MHz or 915MHz. 39010 71122 Rev. 007 Page 1 of 44 MODSEL RBIAS VEEVCO TNK1 TNK2 VCCVCO LF ! General digital and analog RF receivers at 300 to 930MHz ! Tire pressure monitoring systems (TPMS) ! Remote keyless entry (RKE) ! Low power telemetry systems ! Alarm and security systems ! Active RFID tags ! Remote controls ! Garage door openers ! Home and building automation Y R A IN IM L E R P Temperature Code Package Code R (-40 C to 105 C) LQ (32 L QFN 5x5 Quad) Delivery Form 73 pc/tube 5000 pc/T&R Pin Description top bottom VEELNA VCC LNAO VEEIF MIXN MIXP SPISEL RSSI SLC LNAI VEE DF2 DF1 DFO PDN PDP ROI MFO DTAO MLX71122 A/SCLK B/SDTA C/SDEN Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver Document Content 1 Theory of Operation ...................................................................................................4 1.1 1.2 1.3 1.4 1.5 1.6 1.7 General............................................................................................................................. 4 Technical Data Overview.................................................................................................. 4 Block Diagram .................................................................................................................. 5 Enable/Disable in ABC Mode ........................................................................................... 6 Demodulation Selection in ABC Mode.............................................................................. 6 Programming Modes ........................................................................................................ 6 Preconfigured Frequencies in ABC Mode ........................................................................ 6 2 3 Pin Definitions and Descriptions ..............................................................................7 Functional Description ............................................................................................11 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 Frequency Planning........................................................................................................ 11 Calculation of Counter Settings ...................................................................................... 12 Calculation of LO1 and IF1 frequency for Low Frequency Bands............................................. 12 Calculation of LO1 and IF1 frequency for High Frequency Bands............................................ 13 Counter Setting Examples for SPI Mode ................................................................................... 13 Counter Settings in ABC Mode - 8 Preconfigured Channels.................................................... 14 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 PLL Frequency Synthesizer ........................................................................................... 14 Pulse Swallow Counter .............................................................................................................. 15 PLL Counter Ranges ................................................................................................................. 16 Reference Oscillator (RO) ......................................................................................................... 16 Phase-Frequency Detector (PFD) ............................................................................................. 17 Charge Pump (CP) .................................................................................................................... 17 Loop Filter (LF) .......................................................................................................................... 17 Lock Detector (LD)..................................................................................................................... 18 Voltage Controlled Oscillator (VCO) .......................................................................................... 18 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 Receiver Front End......................................................................................................... 19 Low Noise Amplifier (LNA) and Mixer 1 (MIX1)......................................................................... 19 Mixer 2 (MIX2) ........................................................................................................................... 19 IF Filter (IFF) .............................................................................................................................. 20 IF Amplifier (IFA)........................................................................................................................ 21 Automatic Gain Control (AGC) .................................................................................................. 21 FSK Demodulator ...................................................................................................................... 21 Y R A IN IM L E R P 3.5 3.5.1 3.5.2 3.5.3 3.5.4 Data Path........................................................................................................................ 22 Data Filter (DF) .......................................................................................................................... 22 Averaging Data Slicer Mode ...................................................................................................... 22 Peak Detectors (PKDET)........................................................................................................... 23 Output Comparator .................................................................................................................... 23 3.6 3.7 3.8 Frequency Acceptance Range ....................................................................................... 23 Biasing System............................................................................................................... 24 Operating Modes ............................................................................................................ 24 Page 2 of 44 Data Sheet Oct/07 39010 71122 Rev. 007 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.9 3.10 Multi Functional Output................................................................................................... 24 SPI Description............................................................................................................... 25 General................................................................................................................................... 25 Read / Write Sequences ........................................................................................................ 26 Serial Programming Interface Timing..................................................................................... 26 3.10.1 3.10.2 3.10.3 4 Register Description ................................................................................................27 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Register Overview .......................................................................................................... 27 Control Word R0 ........................................................................................................................ 29 Control Word R1 ........................................................................................................................ 30 Control Word R2 ........................................................................................................................ 31 Control Word R3 ........................................................................................................................ 31 Control Word R4 ........................................................................................................................ 32 Control Word R5 ........................................................................................................................ 32 Control Word R6 ........................................................................................................................ 32 Control Word R7 (Read-only Register)...................................................................................... 33 5 Technical Data..........................................................................................................34 5.1 5.2 5.3 5.4 5.5 5.6 Absolute Maximum Ratings ............................................................................................ 34 Normal Operating Conditions ......................................................................................... 34 Crystal Parameters ......................................................................................................... 35 Serial Programming Interface (SPI)................................................................................ 35 DC Characteristics.......................................................................................................... 36 AC System Characteristics ............................................................................................. 37 6 Test Circuits .............................................................................................................38 6.1 6.1.1 Standard FSK & ASK Reception in 8-Channel Preconfigured (ABC) Mode................... 38 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 38 6.2 6.2.1 6.2.2 Standard FSK & ASK Reception in SPI Mode................................................................ 39 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 39 Peak Detector Data Slicer Configured for NRZ Codes ............................................................. 40 6.3 Test Circuit Component List ........................................................................................... 41 Y R A IN IM L E R P 7 Package Description ................................................................................................42 7.1 Soldering Information ..................................................................................................... 42 8 9 10 Reliability Information .............................................................................................43 ESD Precautions ......................................................................................................43 Disclaimer .................................................................................................................44 39010 71122 Rev. 007 Page 3 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 1 1.1 Theory of Operation General The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency is derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator with external inductor, a programmable feedback divider chain, a programmable reference divider, a phasefrequency detector with a charge pump and an external loop filter. In the receiver's down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local oscillator signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first intermediate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image rejection is provided even without using an RF front-end filter. At applications asking for very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA. The receiver signal chain is set up by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by means of the positive and negative peak detectors (PKDET+/-). In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely turned off, and to several other operating modes. There are two global operating modes that are selectable via the logic level at pin SPISEL: * * 8-channel preconfigured mode (ABC mode) fully programmable mode (SPI mode). In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is required. In this case the three lines of the serial programming interface (SPI) are used to select one of the eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are used to enable/disable the receiver and to select FSK or ASK demodulation, respectively. SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are configured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types, data slicer settings and more. The pin MODSEL has no effect in this mode. Y R A IN IM L E R P 1.2 ! ! ! ! ! ! ! ! ! Technical Data Overview Input frequency ranges: 300 to 930MHz Power supply range: 3.0 to 5.5V Temperature range: -40 to +105C Shutdown current: 50nA Operating current: 12.5mA (typ.) FSK input sensitivity: -107dBm (typ.) ASK input sensitivity: -112dBm (typ.) Internal IF2: 2MHz with 230kHz 3dB bandwidth Maximum data rate: 100kbps NRZ code, 50kbps bi-phase code ! Minimum frequency resolution: 10kHz ! Total image rejection: > 65dB (with external RF front-end filter) ! FSK/FM deviation range: 10 to 50kHz ! Spurious emission: < -70dBm ! Linear RSSI range: > 50dB ! FSK input frequency acceptance range: 180kHz (3dB sensitivity loss) ! Crystal reference frequency: 10MHz 39010 71122 Rev. 007 Page 4 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 1.3 Block Diagram LNAO VEELNA MIXN VEEIF MIXP VCCANA RSSI MODSEL 200k 200k DF2 8 9 DF1 1 2 3 4 5 6 28 29 ASK OA1 DFO 27 MIX1 LNAI 31 200k 1M LNA LO1 IF1 MIX2 IF2 IFF IFA FSK SW1 PKDET+ 25 LO2 FSK DEMOD 1M PDP LO2DIV N/A counter VCO LF VCCVCO VEEVCO MFO PKDET_ PDN 26 PFD R counter Control Logic C/SDEN B/SDTA SPISEL A/SCLK SLCSEL SW2 CP RO BIAS VEEANA VCCDIG VEEDIG OA2 DTAO 22 SLC RBIAS 32 11 14 TNK1 12 13 TNK2 15 ENRX ROI LF 23 24 7 17 18 19 10 16 20 21 30 Fig. 1: MLX71122 block diagram The MLX71122 receiver IC consists of the following building blocks: * * * * * * * * * * * * PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2, parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R, the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator (RO) Low-noise amplifier (LNA) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency) Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output FSK demodulator (FSK DEMOD) Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively Positive (PKDET+) and negative (PKDET-) peak detectors Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak detector data slicer Control logic with 3-wire bus serial programming interface (SPI) Biasing circuit with modes control Y R A IN IM L E R P 39010 71122 Rev. 007 Page 5 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 1.4 Enable/Disable in ABC Mode ENRX 0 1 Description Shutdown mode Receive mode Pin ENRX is pulled down internally. Device is in shutdown by default, after power supply on. If ENRX = 0 and SPISEL = 1 then operating modes according to OPMODE bit (refer to control word R0). If ENRX = 1 then OPMODE bit has no effect (hardwired receive mode). 1.5 Demodulation Selection in ABC Mode MODSEL 0 1 Description FSK demodulation ASK demodulation Pin MODSEL has no effect in SPI mode (SPISEL = 1). We recommend connecting it to ground to avoid a floating CMOS gate. 1.6 Programming Modes SPISEL 0 1 1.7 Preconfigured Frequencies in ABC Mode A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 C 0 0 0 0 1 1 1 1 Y R A IN IM L E R P Description ABC mode (8 channels preconfigured) SPI mode (programming via 3-wire bus) Receive Frequency FSK1: 369.5 MHz FSK5: 388.3 MHz FSK2: 371.1 MHz FSK4: 376.9 MHz FSK3: 375.3 MHz FSK7: 394.3 MHz FSK6: 391.5 MHz FSK8: 395.9 MHz As all pins, pins A, B, and C are equipped with ESD protection diodes that are tied to VCC and to VEE. Therefore these pins should not be directly connected to positive supply (a logic "1") before the supply voltage is applied to the IC. Otherwise the IC will be supplied through these control lines and it may enter into an unpredictable mode. In case the user wants to apply a positive supply voltage to these pins before the supply voltage is applied to the IC, a protection resistor should be inserted in each control line. 39010 71122 Rev. 007 Page 6 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 2 1 31 Pin Definitions and Descriptions Name VEELNA LNAI I/O Type ground analog input analog output LNAI 2k Pin No. Functional Schematic VCC Description ground of LNA core VEELNA 1 VEE LNA input, approx. 27 single-ended LNA open-collector output, to be connected to external LC tank that resonates at RF positive supply of LNA, MIX1 MIX2, IFF, IFA, FSK DEMOD, OA1, OA2, PKDET+, PKDET- and BIAS negative supply of LNA, MIX1 MIX2, IFF, IFA, and FSK DEMOD 31 3 LNAO LNAO bias VEE 3 2 VCCANA supply 4 VEEIF ground 5 MIXN 6 MIXP 7 SPISEL 8 RSSI Y R A IN IM L E R P 2k 2k analog input analog input VCC bias VCC mixer 1 negative input MIXN 5 MIXP 6 mixer 1 positive input 390A VEE VEE CMOS input VCC SPI select input SPISEL 7 120 VEE analog output VCC RSSI output, approx. 25k RSSI 120 I (Pi) ASK FSK 8 120 25k VEE SW1 9 MODSEL CMOS input MODSEL 9 VCC demodulation select input (FSK or ASK demodulation) 120 VEE 39010 71122 Rev. 007 Page 7 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver Pin No. 10 Name RBIAS I/O Type analog I/O Functional Schematic VCC VCC I ref Description external resistor for voltage and current biasing, 30k by default, to provide stable parameters over temperature and supply variations ground of VCO RBIAS 50 10 VEE 11 12 VEEVCO TNK1 ground analog I/O TNK1 12 5k VCC VCC 5k TNK2 13 VEE VCO collector output, connection 1 to external LC tank VD VD 13 TNK2 analog I/O VEE 15 LF 14 16 VCCVCO ENRX Y R A IN IM L E R P LF VCOCUR VCO collector output, connection 2 to external LC tank VEE analog I/O VCC VCC VCO LF 50 2.5k 15 VEE supply 10k charge pump output, connection to external loop filter positive supply of VCO CMOS input VCC enable/disable control input (with internal pull-down) ENRX 120 1M VEE 16 17 C/SDEN CMOS input C/SDEN 17 VCC frequency control line C or SPI control line SDEN 120 VEE 39010 71122 Rev. 007 Page 8 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver Pin No. 18 Name B/SDTA I/O Type CMOS input Functional Schematic VCC Description frequency control line B or SPI control line SDTA B/SDTA 120 18 VEE 19 A/SCLK CMOS input A/SCLK 19 VCC frequency control line A or SPI control line SCLK 120 VEE 20 VEEDIG ground ground of PLL SYNT (except of VCO), Control Logic, and OA2 out stage positive supply of PLL SYNT (except of VCO), Control Logic, RO and OA2 out stage 21 VCCDIG 22 DTAO 23 MFO Y R A IN IM L E R P CMOS output VCC supply data output, 2mA sink or source capability DTAO 22 OA2 VEE VCC multifunctional output, reference oscillator output by default MFO 23 150 150 ROI VEE 24 ROI analog input ROI 24 VCC 2A 30p 30p 60k reference oscillator input for connecting an external crystal, Colpitts type oscillator with internal feedback capacitors VEE 39010 71122 Rev. 007 Page 9 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver Pin No. 25 Name PDP I/O Type analog I/O Functional Schematic VCC Description peak detector positive output for connecting an external capacitor PDP 120 1M VEE VCC 25 26 PDN analog I/O PDN 120 26 VEE 27 DFO analog output DFO 27 VEE 1M SW2 peak detector positive output for connecting an external capacitor VCC data filter output 510 200K SW2 OA1 28 DF1 29 DF2 30 32 VEEANA SLC Y R A IN IM L E R P analog I/O VCC VEE DF1 28 SW1 ASK data filter connection 1 for connecting an external capacitor 200K FSK 200K analog I/O VEE VCC + DF2 29 OA1 data filter connection 2 for connecting an external capacitor VEE ground 120 ground of RO, OA1, OA2, PKD+, PKD- and BIAS analog I/O VCC SW2 SLC 32 VEE 120 120 + slicer reference input for connecting an external capacitor OA2 39010 71122 Rev. 007 Page 10 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3 3.1 Functional Description Frequency Planning Because of the double conversion architecture that employs two mixers and two IF signals, there are four different combinations for injecting the LO1 and LO2 signals: * * * * LO1 high side and LO2 high side: LO1 high side and LO2 low side: LO1 low side and LO2 high side: LO1 low side and LO2 low side: receiving at fRF(high-high) receiving at fRF(high-low) receiving at fRF(low-high) receiving at fRF(low-low) As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 2 shows this for the case of receiving at fRF(high-high). In the example of Fig. 2, the image signals at fRF(lowhigh) and fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the high value of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low). The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means either the upper or lower sideband of IF1 can be selected. In the example of Fig. 2, LO2 high-side injection has been chosen to select the IF2 signal resulting from fRF(high-high). f RF Fig. 2: Y R A IN IM L E R P f LO2 f LO2 f RF f LO1 f RF f RF The four receiving frequencies in a double conversion superhet receiver It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO1 signal frequency fLO1 and the LO2 signal frequency fLO2. LO2DIV = N LO2 = f LO1 f LO2 (1) The LO1 signal frequency fLO1 is directly synthesized from the crystal reference oscillator frequency fRO by means of an integer-N PLL synthesizer. The PLL consists of a dual-modulus prescaler (P/P+1), a program counter N and a swallow counter A. f LO1 = f RO (N P + A) = f PFD (N P + A) = f PFD N tot R (2) 39010 71122 Rev. 007 Page 11 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver Due to the double superhet receiver architecture, the channel frequency step size fCH is not equal to the phase-frequency detector (PFD) frequency fPFD. For high-side injection, the channel step size fCH is given by: f CH = f RO N LO2 - 1 N -1 = f PFD LO2 R N LO2 N LO2 (3) While the following equation is valid for low-side injection: f CH = f RO N LO2 + 1 N +1 = f PFD LO2 R N LO2 N LO2 (4) 3.2 Calculation of Counter Settings Frequency planning and the selection of the MLX71122's PLL counter settings are straightforward and can be laid out on the following procedure. Usually the receive frequency fRF and the channel step size fCH are given by system requirements. The N and A counter settings can be derived from Ntot or fLO1 and fPFD by using the following equations. N = floor( 3.2.1 Calculation of LO1 and IF1 frequency for Low Frequency Bands High-high injection must be used for the low frequency bands. First of all choose a PFD frequency fPFD according to below table. The R counter values are valid for a 10MHz crystal reference frequency fRO. The PFD frequency is given by fPFD = fRO /R. Injection Type h-h h-h h-h h-h h-h h-h h-h fCH [kHz] 10 20 25 50 12.5 fPFD [kHz] 13.3 26.7 33.3 66.7 16.7 R Y R A IN IM L E R P 750 600 375 300 150 75 30 100 250 133.3 333.3 N tot N ) = floor( tot ) ; A = N tot - N P = N tot - N 32 P 32 (5) The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLO2 = 4 (or 8) and P =32. f LO1 = N LO2 (f RF - f IF2 ) N LO2 - 1 f LO1 = 4 (f RF - 2MHz) 3 (6) f IF1 = f RF - N LO2 f IF2 N LO2 - 1 f IF1 = f RF - 8MHz 3 (7) Finally N and A can be calculated with formula (5). 39010 71122 Rev. 007 Page 12 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.2.2 Calculation of LO1 and IF1 frequency for High Frequency Bands Typical ISM band operating frequencies like 868.3 and 915MHz can be covered without changing the crystal nor the VCO inductor. Low-low injection should be used for the high frequency bands. First of all choose a PFD frequency fPFD according to below table. The R counter values are valid for a 10MHz crystal reference. The PFD frequency is given by fPFD = fRO /R. Injection Type l-l l-l l-l l-l l-l l-l fCH [kHz] 20 25 50 100 250 500 fPFD [kHz] 16 20 40 80 200 400 R 625 500 250 125 50 25 The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLo2 = 4 (or 8) and P =32. f LO1 = f IF1 = Finally N and A can be calculated with formula (5). 3.2.3 Counter Setting Examples for SPI Mode To provide some examples, the following table shows some counter settings for the reception of the wellknown ISM and SRD frequency bands. The channel spacing is assumed to be fCH = 100kHz. In below table all frequency units are in MHz. Inj h-h h-h h-h h-h l-l l-l l-l l-l fRF 300 315 434 470 850 868 915 930 fIF1 fLO1 Ntot N P A 4 26 0 8 0 20 10 0 fPFD R fREF 10 10 10 10 10 10 10 10 fLO2 fIF2 2 2 2 2 2 2 2 2 Y R A IN IM L E R P f RF + N LO2f IF2 N LO2 + 1 f IF1 = f RF + 8MHz 5 (9) 397.3 417.3 576 624 678.4 692.8 730.4 742.4 2980 3130 4320 4680 8480 8660 9130 9280 93 97 135 146 256 270 285 290 32 32 32 32 32 32 32 32 0.133 0.133 0.133 0.133 0.08 0.08 0.08 0.08 75 75 75 75 125 125 125 125 99.3 104.3 144 156 169.6 173.2 182.6 185.6 N LO2 (f RF - f IF2 ) N LO2 + 1 4 f LO1 = (f RF - 2MHz) 5 (8) 97.3 102.3 142 154 171.6 175.2 184.6 187.6 39010 71122 Rev. 007 Page 13 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.2.4 Counter Settings in ABC Mode - 8 Preconfigured Channels In ABC mode (SPISEL=0), the counter settings are hard-wired. In below table all frequency units are in MHz. FSK 1 2 3 4 5 6 7 8 fRF 369.5 371.1 375.3 376.9 388.3 391.5 394.3 395.9 fIF1 120.5 121.0 122.4 123.0 126.8 127.8 128.8 129.3 fLO1 490.0 492.0 497.7 499.9 515.1 519.3 523.1 525.2 Ntot 3675 3691 3733 3749 3863 3895 3923 3939 N 114 115 116 117 120 121 122 123 P 32 32 32 32 32 32 32 32 A 27 11 21 5 23 23 19 3 fPFD 0.133 0.133 0.133 0.133 0.133 0.133 0.133 0.133 R 75 75 75 75 75 75 75 75 fREF 10 10 10 10 10 10 10 10 fLO2 122.5 123.0 124.4 125.0 128.8 129.8 130.8 131.3 fIF2 2 2 2 2 2 2 2 2 3.3 PLL Frequency Synthesizer The MLX71122 contains an integer-N PLL frequency synthesizer. The reference frequency fR is derived from a stable crystal reference oscillator. f RO Reference Oscillator Reference Divider Y R A IN IM L E R P VCC External Loop Filter Phase-Frequency Detector fR LF f VCO f FB Charge Pump Feedback Divider Voltage Controlled Oscillator Fig. 3: Integer-N PLL Frequency Synthesizer Topology The locked state of the PLL is defined by the following relations: f RO f f VCO = f R = f PFD = f FB = VCO = . R N tot N P + A (10) In this formula the total PLL feedback divider ratio is called Ntot. The synthesized output frequency fVCO can be changed by reprogramming the reference divider or the feedback divider according to f VCO = N tot f RO f = (N P + A ) RO . R R (11) The R counter is used to set the channel spacing. Different channels can be selected by changing the total feedback divider ratio. 39010 71122 Rev. 007 Page 14 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver List of Mathematical Acronyms A f FB floor (x) f PFD f RO = fR R f RO divider ratio of the swallow counter (part of feedback divider) frequency at the feedback divider output The floor function gives the largest integer less than or equal to x. For example, floor(5.4) gives 5, floor(-6.3) gives -7. PFD frequency in locked state reference frequency of the PLL frequency of the crystal reference oscillator frequency of the VCO (equals the LO1 signal of the first mixer) total divider ratio of the PLL feedback path divider ratio of the program counter (part of feedback divider) LO2DIV divider ratio, to derive the LO2 signal from LO1 (N1 = 4 or 8) divider ratio of the prescaler (part of feedback divider) divider ratio of the reference divider R f VCO N tot = N P + A N N LO2 P R 3.3.1 Pulse Swallow Counter The programmable feedback divider of the PLL is based on a pulse-swallow topology. Fig. 4 depicts its implementation, consisting of a dual-modulus prescaler, an RS latch and two programmable counters. VCO Y R A IN IM L E R P Dual Modulus Prescaler Program Counter f VCO P / P+1 fP N f FB PFD Q R f FB = f VCO N P+A Modulus Control Signal (MC) RS LATCH S MC 0 1 Mode P+1 P A Swallow Counter Fig. 4 Pulse Swallow Counter Topology During one cycle of fFB the prescaler begins the operation by dividing by P+1 until the swallow counter A is full. The RS latch is then set and changes the prescaler modulus to P (via the modulus control signal MC) and disables the swallow counter. The division process continues until the program counter N is full and the RS latch is reset. 39010 71122 Rev. 007 Page 15 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver period of f P A cycles of f P (N-A) cycles of f P Fig. 5 Pulse Swallow Divider Timing Therefore the overall feedback divide ratio is: (P + 1) A + P (N - A ) = N P + A . Further restrictions can be derived from above equation: A < P and A < N. Simple math shows that for uniform frequency steps the following condition is necessary: (12) 3.3.2 PLL Counter Ranges In order to cover the frequency range of about 300 to 930MHz the following counter values are implemented in the receiver: PLL Counter Ranges A 0 to 31 (5bit) Therefore the minimum and maximum divider ratios of the PLL feedback divider are given by: Y R A IN IM L E R P NP + A PP. N R P 3 to 2047 (11bit) 3 to 2047 (11bit) 32 (13) N totmin = 32 32 = 1024 N totmax = 2047 32 + 31 = 65535 3.3.3 Reference Oscillator (RO) VCC IRO 30pF 30pF The reference oscillator is based on a Colpitts topology with two integrated functional capacitors as shown in figure 6. The circuitry is optimized for a load capacitance range of 10pF to 15pF. The equivalent input capacitance CRO offered by the oscillator input pin ROI is about 15pF. To ensure a fast and reliable start-up and a very stable frequency over the specified supply voltage and temperature range, the oscillator bias circuitry provides an amplitude regulation. The amplitude at pin ROI is monitored in order to regulate the current of the oscillator core IRO. In SPI-mode it is possible to adjust the typical core current with register ROCUR. There are four values available (see 4.1.7). In ABC-mode IRO = 355A is used as default current. ROI CX XTAL VEE Fig.6: RO schematic 39010 71122 Rev. 007 Page 16 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.3.4 Phase-Frequency Detector (PFD) The phase-frequency detector (in conjunction with the charge pump) generates a voltage step at the loop filter pin LF. This voltage step is proportional to the phase difference between the digital input signals fR and fFB. The implementation of the phase detector is phase-frequency type. This circuitry is very useful because it decreases the acquisition time significantly even if both frequencies differ very much. The phase-frequency detector creates Up and Down signals that control the charge pump and that are also used for the lock detection circuit. The first rising edge of one of the input signals, after a reset of Up and Down, sets either the Up or the Down signal from LOW to HIGH. The following rising edge of the other signal resets Up and Down. If the register setting PFDPOL (see 4.1.2) is HIGH, the PFD polarity is positive. This means a rising edge of the signal fR sets Up from LOW to HIGH and a rising edge of the signal fFB sets Down from LOW to HIGH. If PFDPOL is LOW, the PFD polarity is negative and the assignment of Up and Down to the signals fR and fFB is swapped. In the MLX71122 receiver the VCO frequency increases if the loop filter output voltage increases and vice versa. The PFD polarity needs to be positive to achieve the correct feedback in the PLL loop. If an external varactor diode is added to the VCO tank, the tuning characteristic may change from positive to negative depending on the particular varactor diode circuitry. Therefore the PFDPOL bit can be used to define the phase-frequency detector polarity. 3.3.5 Charge Pump (CP) The Charge Pump is controlled by the Up and Down signals of the Phase-Frequency Detector. If the Up signal is HIGH, then the charge pump current ICP is sourced from the positive supply rail to the loop filter pin LF (pin 15). If the Down signal is HIGH, then the current ICP is drained from pin LF to ground. The gain of the phase detector in conjunction with the charge pump can be expressed as: whereat ICP is the charge pump current which is set via register CPCUR (see 4.1.2). Default of ICP is 100A. The static Up and Down selections of ICP can be used for test purposes. 3.3.6 Loop Filter (LF) Since the loop filter has a strong impact on the function of the PLL, it must be chosen carefully. The suggested filter topology is shown in Fig. 7. The loop filter of the PLL is set up by an external resistor and two external capacitors. It constitutes a 2nd order passive filter. This approach allows the user to easily adapt the loop filter bandwidth to different requirements. As a rule of thumb the loop filter bandwidth of an integer-N PLL should be set 10 times smaller than the PFD frequency. This is to achieve a stable PLL with a flat VCO noise floor. The loop filter bandwidth depends on the external resistor and capacitors as well as on the VCO gain, the charge pump current and the so-called phase margin. A phase margin of 45 is commonly used for highest PLL stability. It is recommended to follow the component lists of section 6 for choosing appropriate values of the loop filter resistor and capacitors. A good source for a detailed PLL analysis is: "Gardner, F.M., PhaseLocked Loop Techniques, John Wiley & Sons, 1980." Y R A IN IM L E R P K PD = I CP , 2 VCC (14) CF1 RF CF2 LF VCO + Fig. 7: 2nd order Loop filter 39010 71122 Rev. 007 Page 17 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.3.7 Lock Detector (LD) In SPI mode a lock-detect signal LD is available at pin 23 if MFO is set to 1000 (binary) in control word R3 (see 4.1.4). The pin output is HIGH when the PLL is locked in. Alternatively the lock-detect signal is visible in bit 10 of R7 (see 4.1.8) if bit SHOWLD in R1 (see 4.1.2) is HIGH. The lock detection circuitry uses the Up and Down signals from the phase-frequency detector to check them for phase coherency. Figure 8 shows an overview of the lock signal generation. The locked state and the unlock condition will be controlled by the register settings of LDTIME and LDERR. During the start-up phase of the PLL, Up and Down signals are quite unbalanced. Therefore the Lock Detector circuit waits the time span that is programmed in divider DIV_LDTIME before a first lock can occur. The time span is dependent on the period of the reference signal fR. By default it is 16/fR (see 4.1.2). When the PLL approaches steady state, the signals Up and Down begin to overlap. The time span within which the signals are not overlapping is assessed by using a programmable delay gate. If it is shorter than programmed in LDERR (see 4.1.2) then the LD output is set to HIGH. By default the error time should be shorter than 15ns. A second option is shorter than 30ns. After LD is set to HIGH the divider is disabled and the lock state remains unchanged until the unlock signal resets the divider. If LDMODE in register R1 (see 4.1.2) is HIGH then the LD output can not be reset. It remains HIGH until the synthesizer is turned off. 2 LDTIME [ 1: 0 ] DIV_LDTIME 2 4 8 16 O LD f R >1 1 C R MUX EN Up =1 Dn 3.3.8 Voltage Controlled Oscillator (VCO) The receiver includes an LC-based voltage controlled oscillator with an external inductor connected between pins TNK1 and TNK2. Two internal varactor diodes in series combination are forming the tuneable part of the oscillator tank. The oscillation frequency is adjusted by the DC voltage at pin LF. The tuning sensitivity of the VCO is approximately 83MHz/V for 433MHz operation and 105MHz/V at 868MHz, respectively. Since the cathodes of the varactors is tied to VCC, a higher voltage at pin LF or an Up-signal of the PFD forces the capacitance to decrease and the VCO frequency to increase. With positive phase detector polarity (PFDPOL = HIGH) the edges of the signal fFB will catch up to the reference signal fR (see Fig. 3). The VCO current VCOCUR can be adjusted via the SPI in order to ensure stable oscillations over the whole frequency range. Also the bias current of the output buffer can be increased with VCOBUF to enhance its driving capability at the high frequency bands above 800MHz (see section 4.1.2). If the supply voltage is lower than 5V it is possible to adjust the tuning range of the VCO with VCORANGE (see 4.1.2). The minimum supply voltage is 3V. 39010 71122 Rev. 007 Page 18 of 44 Y R A IN IM L E R P >1 LDMODE 1 >1 R Q unlock = 15ns 30ns delay & S LDERR Fig. 8: Lock Detection Circuit External Loop Filter TNK1 LF TNK2 VCC VCCVCO 5k 5k Charge Pump Fig.9: + VCOCUR VEE VCO schematic Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.4 Receiver Front End The radio frequency (RF) front-end of the receiver is a double-superheterodyne configuration that converts the input RF signal via a first intermediate frequency (IF1) signal to a second intermediate frequency (IF2) signal. While the range of IF1 can vary between 100 and 200MHz, IF2 is fixed to 2MHz. Both signals are completely processed internally. According to the block diagram (see Fig. 1), the front-end consists of an LNA, a first mixer (MIX1), a second mixer (MIX2), an internal IF filter (IFF) and an IF limiting amplifier (IFA) with received signal strength indicator (RSSI). The local oscillator signal for mixer 1 (LO1) is directly generated in the PLL frequency synthesizer. The LO2 signal for mixer 2 is derived from the LO1 signal via a divider (see 4.1.4). There is no inherent suppression of the first mixer's image frequency. It depends on the particular application and the system's environmental conditions whether an RF front-end filter should be added or not. If image rejection and/or good blocking immunity are relevant system parameters, a band-pass filter must be placed either in front or after the LNA. This filter can be a SAW (surface acoustic wave) or LC-based filter (e.g. helical type). Because mixer 2 is an image rejection mixer, the image frequencies of the second mixing process are suppressed (see Fig. 2). The advantage of a two stage mixing receiver is the higher gain that can be achieved in the front end. 3.4.1 Low Noise Amplifier (LNA) and Mixer 1 (MIX1) The LNA is based on a cascode topology for low-noise, high gain and good reverse isolation. The open collector output has to be connected to an external resonance circuit tuned to the receive frequency. The gain of the LNA can be changed to achieve a high dynamic range. There are four gain settings selectable by the control bits LNAGAIN (see 4.1.1). Default setting is the highest gain. The gain settings are automatically set if the automatic gain control (AGC) feature is activated (see 4.1.4). The first mixer is a double-balanced mixer which converts the receive frequency to IF1. The default LO injection type for RF frequencies below 600MHz should be high side (fLO1 = fRX + fIF1). Low side injection (fLO1 = fRX - fIF1) is recommended for the higher frequency bands. Since the data polarity of an FSK modulated signal will be inverted by changing the injection side it is possible to change the data polarity at the data output (DTAO) via bit DTAPOL (see 4.1.1). Two gain settings of mixer 1 can be selected through MIX1GAIN (see 4.1.1): 14dB as a default value or 0dB optionally. Y R A IN IM L E R P VCC L3 C4 C6 C5 LNAO MIXN MIXP LNAGAIN [ 1: 0 ] 2 VCCLNA Ibias MIX1 LO1 IF1 2k LNAI LNA MIX1GAIN VEELNA Fig. 10: LNA and Mixer 1 3.4.2 Mixer 2 (MIX2) SSBSEL 0/90 IF1 LO2 The second mixer is a double-balanced image rejection mixer in Hartley architecture using a complex poly-phase filter that converts the IF1 to the IF2 signal. The default LO injection type is high side (fLO2 = fIF1 + fIF2), but also low side injection is possible (fLO2 = fIF1 - fIF2), by setting SSBSEL to LOW (see 4.1.1). As for mixer 1, the injection side determines the polarity of the output signal. Two gain settings of mixer 2 can be selected by MIX2GAIN (see 4.1.1), a setting at 9dB (default) and one at -2dB. polyphase IF2 filter CROSS SWITCH 90/0 MIX2GAIN 90 Fig. 11: Mixer 2 (Image Rejection Mixer) 39010 71122 Rev. 007 Page 19 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.4.3 IF Filter (IFF) The MLX71122 comprises an internal IF filter with a -3dB bandwidth of 230kHz and a -40dB attenuation bandwidth of 1.6MHz. The filter contains three capacitively coupled bi-quad stages that represent resonant tanks at a filter center frequency of 2MHz. Each bi-quad stage uses transconductance cells that can be tuned by changing their bias current. An auto-tuning mechanism is implemented that permanently adjusts the bias current to eliminate process, temperature and supply voltage variations. A matched master bi-quad is used in a current controlled oscillator (CCO) at 3MHz embedded in a PLL structure. The PFD-frequency of this PLL is derived from the RO signal using divider RIFF (see 4.1.6). The actual internal control word IFFVAL of the filter can be read out from register 7 (see. 4.1.8). At power on and after deactivation of the IF filter with IFFTUNE (see 4.1.7), the preset value that is stored in IFFPRES in register 6 (see 4.1.7) will be loaded into the internal control word. If the filter auto tuning is halted via IFFHLT (see 4.1.7) then the actual word remains in the internal control word but is not updated. The internal control word determines the current consumption of the filter and therefore of the whole receiver. Higher values lead to higher current consumptions. The deviation from the nominal current consumption can be about 0.75mA. Four gain settings of the IF filter are selectable via IFFGAIN in register R0 (see 4.1.1). The default value is +6dB, other options are -14dB, -6dB and 0dB. IFF IF2 IFFHLT IFFTUNE IFFPRES [ 7: 0 ] 10 IFFSTATE [ 1: 0 ] IFFVAL [ 7: 0 ] 10 tuning signal 2MHz IF 2 IFFGAIN [ 1: 0 ] f RO Y R A IN IM L E R P RIFF digital counter PFD 8 D IFFVAL A CCO 3MHz 200 Fig. 12: IF filter auto-tuning circuit 39010 71122 Rev. 007 Page 20 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.4.4 IF Amplifier (IFA) After passing the IF filter the receiving signal is amplitude limited by means of a high gain limiting amplifier. Its small signal gain is about 68dB. A received signal strength indicator (RSSI) voltage is generated in the IF amplifier. It is available at pin RSSI. The voltage at this pin is proportional to the input level of the receiver (in dB scales). By using this RSSI output signal the incoming signal strength of different transmitters can be determined. The same RSSI signal is used for receiving ASK modulated signals if MODSEL (see 4.1.6) is HIGH. The IFA generates two digital signals RSSIL and RSSIH that indicate the level range of the RSSI voltage. If the level is in the lower quarter of the RSSI voltage range then both signals are LOW. If it is in the upper quarter of the RSSI range then both signals are HIGH. In between, the RSSIL signal is HIGH and RSSIH is LOW. Both values can be read out from register R7 of the IC (see 4.1.8). These two signals are also used for the AGC feature. 3.4.5 Automatic Gain Control (AGC) The Automatic Gain Control (AGC) can be activated in SPI mode with AGCEN (see 4.1.4). By default, it is turned off. It uses the RSSIH and RSSIL signals of the IF amplifier to determine whether the gain has to be increased or decreased. The gain will be decreased beginning with the gain of the last stage. The gain increase works vice versa. The AGC circuit controls the gain of the LNA, and of mixer 1 and mixer 2. To avoid rapid gain switching, caused by short signal strength fluctuations or during ASK reception, the gain control operates with a time delay that can be programmed via AGCDEL (see 4.1.4). The time delay also depends on the PFD frequency of the IF filter auto-tuning circuit. There is no delay by default. AGCMODE (see 4.1.5), a second setting, determines whether the delay is applied for gain increase and decrease or only for gain increase. By default, a delay for increase and decrease is used. 3.4.6 FSK Demodulator FSK reception is turned on if bit MODSEL in register R5 is set to LOW (default). The demodulator is completely internally implemented, so no external, expensive discriminator device is needed. The used FSK demodulator is based on time delay elements and a mixer. The delay path provides a phase shift of 90 degrees to the original IF signal. The average of the phase shift is controlled, so that the input frequency acceptance range is wider than the IF filter bandwidth of 230kHz. The gain of the demodulator can be changed with bit DEMGAIN (see 4.1.1). It can be at low gain with about 4mV/kHz (default) or at high gain with about 15mV/kHz. High gain should only be used for small FSK/FM deviations of up to 15kHz, because the demodulator gets nonlinear at larger FM/FSK deviations. Y R A IN IM L E R P 39010 71122 Rev. 007 Page 21 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.5 Data Path The data path contains all circuitry that is used to process the baseband signal. The MLX71122 comprises a second order Sallen-Key lowpass filter, two peak detectors and an output comparator as digital signal output. 3.5.1 Data Filter (DF) The receive part of the MLX71122 contains a 2nd order Sallen-Key low-pass filter that can be configured by connecting two external capacitors C8 and C9 to the IC (see sec. 6). This data filter removes high frequency components and noise from the demodulated signal that may otherwise lower the signal to noise ratio at the comparator input. The filter bandwidth has to be adjusted to the maximum data rate. A good choice for the 3dB bandwidth is 75% of the data rate for NRZ codes and 150% for bi-phase or Manchester codes. A Butterworth characteristic is commonly used in the data filter. To compensate parasitic effects of the board and IC, we recommend calculating the filter characteristic with a slight amplitude peaking, e.g. a 0.035dB Tschebyschew filter characteristic. Since the internal resistors of the filter are both 200k and the overall gain is set to unity we obtain the following table for the capacitor values: Coding NRZ Code C8 C9 Bi-Phase Code Example: base band signal 4kbps, NRZ coding C8 = 2.2 150pF = 330pF 3.5.2 Averaging Data Slicer Mode The averaging data slicer mode is the default setting for the data path of the MLX71122. Bit SLCSEL in register R0 (see 4.1.1) is LOW if it is active and switch SW2 connects the pin SLC with DFO via a 200k resistor (see Fig. 1). With an external capacitor C10 at pin SLC, a simple low pass filter is formed that generates the threshold voltage for the output comparator. The value of C10 depends on the length of the packet preamble, the coding and the data rate. The larger the C10 value the longer the time until valid output data can be received at pin DTAO. We recommend using the averaging data slicer mode for bi-phase or Manchester encoded bit streams since the DC-content of these codes is almost zero. The RC-time constant of the slicer can be calculated using: Y R A IN IM L E R P 2.2 C9 2.2 C9 560 pF data rate / kbps 280 pF data rate / kbps C9 = 560pF = 140pF 4 [kbps] in E-series C9 = 150pF in E-series C8 = 330pF t SLC = 200k C10 We recommend that tSLC is at least 25 times as long as the bit time of the equivalent NRZ signal. Example: base band signal 4kbps, NRZ coding (15) C10 = 25 0.25ms = 31.25nF 200k in E-series C10 = 33nF 39010 71122 Rev. 007 Page 22 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.5.3 Peak Detectors (PKDET) Peak detector mode is recommended for fast acquisition of the received data and if NRZ code is used. The peak detectors can be activated by setting SLCSEL to HIGH in register R0 (see 4.1.1). This connects SLC (pin 32) with the resistive voltage divider between PDP (pin 25) and PDN (pin 26) (see Fig. 1). The peak detector at PDP is used to detect the maximum of the voltage at DFO and the peak detector at PDN detects the minimum of the voltage at DFO. Since the voltage divider is symmetric, the threshold voltage will be in the middle of the minimum and maximum voltages at DFO. The peak voltages are proportional to the charge that is stored on the peak detector capacitors at PDP (C11) and PDN (C12). All pull-up and pull-down currents are given in sec. 5.5. Because both pins are connected via a 2M resistor, both peak detector capacitors will be discharged with a time constant depending on the value of the capacitors. For equal values of both capacitors (C = C11 = C12), the time constant will be: t DIS = 2M 0.5 C (16) The minimum value of tDIS is limited by the maximum number of equally consecutive bits. A value of tDIS of at least 128 times the bit time is a good choice since this is a common data package length. Example: base band signal 4kbps, NRZ coding C11 = C12 = 128 0.25ms = 32nF 0.5 2M in E-series C11 = C12 = 33nF The maximum capacitor value may also be limited by the pull-up and pull-down currents of the peak detectors given in sec. 5.5, because C11 and C12 have to be charged during the first bits of the preamble of the data packet. 3.5.4 Output Comparator The output comparator or data slicer decides whether the incoming signal is a digital LOW or HIGH by using the reference voltage at SLC (pin 32). If the internal voltage is larger than the reference then the output is HIGH and vice versa. Nevertheless, the polarity of the output comparator can be inverted. The driving capability of the comparator output is 2mA and in standby mode the tri-state output is at high impedance. Pin DTAO must not be connected by a low impedance to a fixed voltage supply or a stronger driver output! We recommend using a series resistance of 10k to connect DTAO. 3.6 Frequency Acceptance Range The frequency acceptance range is defined as the bandwidth where the input sensitivity can be degraded by 3dB at a maximum, compared to the sensitivity at the center frequency of the channel. Typically, the frequency acceptance range of the MLX71122 is about 180kHz, see Fig.13. The frequency acceptance range is mainly depending on the frequency deviation, and slightly on the modulation frequency. The larger the frequency deviation the smaller the acceptance range. Fig. 13: Measured sensitivity characteristic -3 (BER=3*10 , 4kbps, f=20kHz) Y R A IN IM L E R P -92 -95 sensitivity / dBm -98 -101 -104 -107 -110 433.7 180kHz 433.8 433.9 434.0 frequency / MHz 434.1 39010 71122 Rev. 007 Page 23 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.7 Biasing System The biasing system needs an external 30k resistor that is connected between RBIAS (pin 10) and the PCB ground. The band-gap voltage at RBIAS causes a reference current flow of about 42A through this reference current resistor. The accuracy of the external resistor should be within 2%. To minimize the temperature dependency it is recommended to use a metal film resistor. 3.8 Operating Modes The MLX71122 has four operating modes having an impact on the receiver's current consumption. The OPMODE bits in register R0 (see 4.1.1) determine the operating mode. Selections are: * * * * 00 - Shutdown 01 - Receive 10 - RO and bias only 11 - Synthesizer only all blocks deactivated, only SPI active (default) receiving data from LNAI at selected frequency only biasing system and reference oscillator are working only biasing system, reference oscillator and PLL are working The first operating mode consumes virtually no current. The circuit is dead except of the SPI that can listen to commands. In Receive mode all necessary blocks are turned on in order to receive data at the programmed frequency. The last two operating modes can be used to accelerate the start-up time of the circuit after periods of silence. With RO and bias only, the start-up time of the reference oscillator (RO) can be circumvented. RO and biasing consume not as much current as the whole receiver. With Synthesizer only the full PLL is already working and locked. Current consuming blocks as the LNA, the IF-filter and the FSK-demodulator are turned off in this state. The last mode is useful if the receiver has to listen frequently. 3.9 Multi Functional Output The Multi Functional Output (pin 23) can be used to read out the control register settings or to make other internal signals available at this pin. The output is controlled by the bits MFO in register R3 (see 4.1.4). The most important selections are: * * * * * * * 0000 - Z-State 0001 - SPI-out 0010 - Logic-0 0011 - Logic-1 0100 - RO-out 0101 - IF-out 1000 - LD-out MFO pin is in high impedance mode MFO pin is digital serial output for data of registers MFO pin is pulled to ground MFO pin is pulled to VCC MFO pin is buffered, analogue output of RO frequency (default) MFO pin is buffered, analogue output of IF2 signal after the IF-filter MFO pin represents lock state of PLL Y R A IN IM L E R P Z-State, Logic-0 and Logic-1 can be used to provide digital control signals to other circuits on the PCB. In state RO-out a 10MHz clock frequency is available at MFO, e.g. for driving a microcontroller. At IF-out pin MFO provides the IFF output, amplified by a factor of 5 (unloaded). In this case the output resistance is about 610. The IF-out mode can be used for checking the IFF characteristics or for further signal processing, e.g. to add an external limiting amplifier and demodulator. With the LD-out setting the state of the PLL can be read out. All other selections are for test purposes 39010 71122 Rev. 007 Page 24 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.10 SPI Description 3.10.1 General Serial programming interface (SPI) mode can be activated by choosing SPISEL = 1 (e.g. at positive supply voltage VCC). In this mode, the input pins 17, 18 and 19 are used as a 3-wire unidirectional serial bus interface (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter settings, mode bits etc. In addition the MFO pin can be programmed as an output (see section 4.1.4) in order to read data from the internal latches and it can be used as an output for different test modes as well. At each rising edge of the SCLK signal, the logic value at the SDTA terminal is written into a shift register. The programming information is taken over into internal latches with the rising edge of SDEN. Additional leading bits are ignored, only the last bits are serially clocked into the shift register. A normal write operation shifts 16 bits into the SPI, a normal read operation shifts 4 bits into the SPI and reads additional 12 bits from the MFO pin. If less than 12 data bits are shifted into SDTA during the write operation then the control register may contain invalid information. In general a control word has the following format. Bit 0 is the Read/Write bit that determines whether it is a read (R/W = 1) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the corresponding data bits. MSB D11 D10 D9 D8 There are two control word formats for read and for write operation. Data bits are only needed in write mode. Read operations require only a latch address and a R/W bit. Due to the static CMOS design, the serial interface consumes virtually no current. The SPI is a fully separate building block and can therefore be programmed in every operational mode. Y R A IN IM L E R P LSB MSB LSB Control Word Format Bit 0 Data Latch Address A2 Mode R/W D7 D6 D5 D4 D3 D2 D1 D0 A2 A0 39010 71122 Rev. 007 Page 25 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 3.10.2 Read / Write Sequences Fig. 14 Typical write sequence diagram 3.10.3 Serial Programming Interface Timing SDEN t CWH Y R A IN IM L E R P Fig. 15 Typical read sequence diagram t CR tEW tEH t CWL t CF t ES t DES t DSO SCLK t CS t CH SDTA MFO Fig. 16 SPI timing diagram 39010 71122 Rev. 007 Page 26 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 4 Register Description The following tables are to describe the functionality of the registers. Sec. 4.1 provides a register overview with all the control words R0 to R7. The subsequent sections. 4.1.1 to 4.1.8 show the content of the control words in more detail. Programming the registers requires SPI mode (SPISEL = 1). Default settings are for ABC mode. 4.1 Register Overview DATA LSB 10 9 8 7 6 5 4 3 2 1 0 CONTROL WORD MSB Bit No. 11 LATCH ADDRESS MSB LSB default 1 DTAPOL 0 SLCSEL 1 SSBSEL 0 DEMGAIN 1 IFFGAIN [ 1 :0 ] 1 0 MIX2GAIN 0 MIX1GAIN 1 LNAGAIN [1 : 0 ] 1 0 0 OPMODE [1:0] 0 0 0 R0 Bit No. 11 10 default 1 SHOWLD R1 Bit No. 11 10 default 1 N [6:0] A [4:0] Y R A IN IM L E R P 9 8 7 6 5 4 3 2 1 0 MSB read/ write LSB 0 0 0 1 0 1 1 0 1 0 0 0 0 1 VCORANGE PRESCUR VCOCUR LDMODE VCOBUF PFDPOL LDTIME [ 1 :0 ] CPCUR [1:0] LDERR read/ write 9 8 7 6 5 4 3 2 1 0 MSB LSB 1 1 0 1 1 1 0 1 1 0 0 0 1 0 R2 Bit No. 11 10 9 read/ write 8 7 6 5 4 3 2 1 0 MSB LSB default 0 1 0 MFO [3:0] 0 0 AGCDEL [1:0] 0 0 AGCEN 0 LO2DIV 0 0 0 N [ 10 : 7 ] 0 0 1 1 R3 read/ write 39010 71122 Rev. 007 Page 27 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver CONTROL WORD MSB Bit No. 11 10 9 8 7 DATA LSB 6 5 4 3 2 1 0 LATCH ADDRESS MSB LSB default 0 AGCMODE 0 0 0 0 1 0 R [ 10 : 0 ] 0 1 0 1 1 1 0 0 R4 Bit No. read/ write 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB default 0 MODSEL 0 1 0 1 0 1 RIFF [ 10 : 0 ] 0 1 1 0 0 1 0 1 R5 Bit No. read/ write 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB default 1 R6 Bit No. 11 10 default RSSIH R7 Note: depends on bit 11 in R4, 0 = RSSIL, 1 = LD Y R A IN IM L E R P IFFTUNE IFFPRES [7:0] IFFHLT 9 8 7 6 5 4 3 2 1 0 MSB 1 1 0 1 0 0 0 0 1 0 1 1 1 0 ROCUR [ 1 :0 ] read/ write LSB 1 1 1 IFFSTATE [ 1 :0 ] LDRSSIL IFFVAL [7:0] readonly 39010 71122 Rev. 007 Page 28 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 4.1.1 Control Word R0 Name Bits 00 01 10 11 00 01 10 11 Description operation mode OPMODE [1:0] shutdown receive mode reference oscillator & BIAS only synthesizer only lowest gain low gain high gain highest gain LNA gain (default - 20dB) (default - 6dB) (default - 2dB) (default - 0dB) 1st Mixer gain MIX1GAIN [4] 0 1 0 1 high gain low gain high gain low gain (14dB) (0dB) 2nd Mixer gain MIX2GAIN [5] (9dB) (-2dB) #default #default LNAGAIN [3:2] #default gain values are relative to gain at default #default IFFGAIN [7:6] DEMGAIN [8] SSBSEL [9] Y R A IN IM L E R P intermediate frequency filter gain (-14dB) (-6dB) (0dB) (+6dB) 00 01 10 11 0 1 0 1 lowest gain low gain high gain highest gain low gain high gain demodulator gain (~ 4mV/kHz) (~ 15mV/kHz) single side band selection upper side band lower side band Internal IF2 = 2MHz #default #default LO2 low-side inj. (IF1 = LO2 + IF2) LO2 high-side inj. (IF1 = LO2 - IF2) slicer mode select #default SLCSEL [10] 0 1 0 averaging Data Slicer mode peak detector Data Slicer mode data output polarity OA2 inverted `1' for space at ASK or fmin at FSK, `0' for mark at ASK or fmax at FSK #default DTAPOL [11] 1 normal `0' for space at ASK or fmin at FSK, `1' for mark at ASK or fmax at FSK #default 39010 71122 Rev. 007 Page 29 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 4.1.2 Control Word R1 Name Bits 00 01 10 11 0 1 0 1 00 01 10 11 100A 400A 400A static down 400A static up PFD output polarity PFDPOL [2] negative positive lock detector time error LDERR [3] 15ns 30ns lock detection time [5:4] 2/fR 4/fR 8/fR 16/fR minimum time span before lock in fR is the reference oscillator frequency fRO divided by R, see section 4.1.5 (R4) Description charge pump current setting #default CPCUR [1:0] #default #default LDTIME #default LDMODE [6] VCORANGE [7] VCOCUR [8] VCOBUF [9] Y R A IN IM L E R P lock detector mode 0 1 0 1 check lock condition permanently check lock condition until 1st lock in VCO range 3V supply 5V supply VCO range setting for different VCCs. #default #default VCO core current 0 1 0 1 0 1 450A 520A #default VCO buffer current 900A 1040A 20A 30A #default prescaler 32/33 reference current PRESCUR [10] #default 30A may be used for fRF = 868/915MHz function of LDRSSIL bit SHOWLD [11] 0 1 RSSIL (RSSI low flag) LD (lock detection flag) select output data of LDRSSIL, see section 4.1.8 (R7) #default 39010 71122 Rev. 007 Page 30 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 4.1.3 Control Word R2 Name A Bits [4:0] 01100 value is 12 swallow counter range: 0 to 31 Description swallow counter value #default program counter value (bits 0 - 6) N [11:5] 000 0111 0111 N value is 119 N counter range: 3 to 2047 #default 4.1.4 Control Word R3 program counter range (bits 7 - 10) N [3:0] 000 0111 0111 N value is 119 N counter range: 3 to 2047 #default LO2 divider ratio LO2DIV [4] AGCEN [5] AGCDEL [7:6] MFO [11:8] Y R A IN IM L E R P AGC enable mode 0 1 disabled enabled no delay 3/fIFF 15/fIFF 31/fIFF AGC delay settings 00 01 10 11 multi functional output 0000 0001 0010 0011 0100 0101 1000 MFO is in Z state MFO is SPI read-out MFO = 0 MFO = 1 MFO is analog RO output MFO is IFF output MFO is lock detector output 0 1 divide by 4 divide by 8 #default #default #default fIFF is the reference oscillator frequency fRO divided by RIFF, see section 4.1.6 (R6) #default 39010 71122 Rev. 007 Page 31 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 4.1.5 Control Word R4 Name R Bits [10:0] 000 0100 1011 value is 75 R counter range: 3 to 2047 Description reference divider range #default AGC delay mode AGCMODE [11] 0 1 gain decrease and increase with delay gain decrease without delay, gain increase with delay #default selects AGC delay mode in combination with AGCDEL bits, see section 4.1.4 (R3) 4.1.6 Control Word R5 Name RIFF Bits [10:0] 010 1010 1100 value is 684 IFF counter range: 4 to 2047 Description reference divider value for IFF adjustment #default MODSEL [11] 4.1.7 Control Word R6 Name Bits IFFPRES [7:0] Y R A IN IM L E R P demodulation selection 0 1 FSK demodulation ASK demodulation selects modulation type when chip is controlled via SPI mode #default Description IFF preset value 1000 0101 value is 133 #default IFF DAC preset at start of automatic tuning IFF halt IFFHLT [8] 0 1 auto tuning running auto tuning halted suspends IFF automatic tuning #default IFF tuning IFFTUNE [9] 0 1 00 01 10 11 disable and load DAC with IFFPRES enable reference Oscillator core current ROCUR [11:10] 85A 170A 270A 355A #default #default 39010 71122 Rev. 007 Page 32 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 4.1.8 Control Word R7 (Read-only Register) Name IFFVAL Bits [7:0] see also IFFPRES in section 4.1.7 (R6) Description IFF adjustment value IFF automatic tuning state IFFSTATE [9:8] 00 01 10 11 0 1 filter tuned or auto-tuning disabled tuning up the filter frequency tuning down the filter frequency master oscillator of filter does not work lock detector or RSSI low flag LDRSSIL [10] PLL not locked or RSSI value in lower region PLL locked or RSSI value above lower region RSSI high flag RSSIH [11] 0 1 RSSI value below upper region RSSI value in upper region depends on SHOWLD in section 4.1.2 (R1) Y R A IN IM L E R P 39010 71122 Rev. 007 Page 33 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 5 5.1 Technical Data Absolute Maximum Ratings Parameter Symbol VCC VIN PiRF TSTG TJ RthJA Pdiss VESD1 VESD2 Condition / Note Min 0 - 0.3 @ LNA input -55 Max 7.0 Vcc+0.3 10 +125 +150 60 0.1 +1.0 +0.75 Unit V V dBm C C K/W W kV Operation beyond absolute maximum ratings may cause permanent damage of the device. Supply voltage Input voltage Input RF level Storage temperature Junction temperature Thermal Resistance Power dissipation Electrostatic discharge 1) all pins except LNAO 2) pin LNAO human body model, 1) human body model, 2) -1.0 -0.75 5.2 Normal Operating Conditions Parameter Supply voltage Operating temperature Input low voltage (CMOS) Input high voltage (CMOS) Input frequency range IF1 range IF2 range XOSC frequency VCO frequency Frequency offset of carrier Frequency deviation FSK data rate ASK data rate FM bandwidth Y R A IN IM L E R P Symbol VCC TA VIL Condition Min 3.0 -40 Max 5.5 +105 VIH ENRX, SEL pins, A/SCLK B/SDTA, C/SDEN ENRX, SEL pins, A/SCLK B/SDTA, C/SDEN 0.3 " VCC 0.7 " VCC 300 80 fRF fIF1 fIF2 fref fLO fCAR set by the crystal 400 -100 10 NRZ NRZ 930 190 2 10 750 100 f RFSK RASK fm 50 100 100 15 Unit V C V V MHz MHz MHz MHz MHz kHz kHz kbps kbps kHz 39010 71122 Rev. 007 Page 34 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 5.3 Crystal Parameters Parameter Crystal frequency Load capacitance Static capacitance Series resistance Symbol f0 CL C0 R1 Condition fundamental mode, AT 10 Min Max 10 15 7 70 Unit MHz pF pF 5.4 Serial Programming Interface (SPI) Parameter Symbol VIH VIL fSLCK tSLCK tCS tCH tCWL tCWH tES tEW I tCR tCF tDES tDSO CLMFO Condition Min VCC - 0.4 0.4 10 100 20 20 50 50 30 50 20 Max Unit V V MHz ns ns ns ns ns ns ns ns ns ns ns ns pF Input High Voltage Input Low Voltage SLCK frequency SLCK period SDTA to SCLK set up time SCLK to SDTA hold time SCLK pulse width low SCLK pulse width high SCLK to SDEN set up time SDEN pulse width SDEN to SCLK hold time Rising Edge of SLCK Falling Edge of SLCK SDEN to MFO data set-up time SCLK to MFO data set-up time MFO max. pin load capacitance Y R A IN IM L E R P 0.1 tSLCK 0.1 tSLCK 70 50 20 39010 71122 Rev. 007 Page 35 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 5.5 DC Characteristics all parameters under normal operating conditions and default settings, unless otherwise stated; typical values at TA= 23 C and VCC = 5 V all parameters based on test circuits as shown in Fig. 17 to Fig. 19 Parameter Operating Currents Shutdown current Supply current, FSK Supply current, ASK Supply current, RO only Supply current, Synthesizer only Digital Pin Characteristics Input low voltage CMOS, ENRX Input high voltage CMOS, ENRX Pull down current ENRX pin Low level input current ENRX pin Input low voltage CMOS ISBY IFSK IASK IRO ISYN OPMODE=00 and ENRX=0 OPMODE=01 or ENRX=1 OPMODE=01 or ENRX=1 OPMODE=10 and ENRX=0 OPMODE=11 and ENRX=0 ENRX pin 50 10 9.5 0.4 3 12 11.5 0.8 4 500 15 14.5 1.2 5 nA mA mA mA mA Symbol Condition Min Typ Max Unit Input high voltage CMOS Low level input leakage current Y R A IN IM L E R P VIHEN IPDEN ENRX pin 0.7 " VCC 3.5 VCC+0.3 7 ENRX=1 ENRX=0 5 IINLEN VIL 0.05 VIH IIL IHL Pins MODSEL, SPISEL, A/SCLK, B/SDTA, C/SDEN Pins MODSEL, SPISEL, A/SCLK, B/SDTA, C/SDEN Pins MODSEL, SPISEL, A/SCLK, B/SDTA, C/SDEN Pins MODSEL, SPISEL, A/SCLK, B/SDTA, C/SDEN OA1 OA2 OA2 (DTAO pin) OA2 (DTAO pin) PDP PDN -0.3 0.3 " Vcc 0.7 " VCC VCC+0.3 -2 2 VOFFOA1 VOFFOA2 IOA2SINK IOA2SRC IPDPPU IPDNPD -50 -50 50 50 2 2 235 270 VILEN -0.3 0.3 " Vcc V V A A V V A High level input leakage current Analog Pin Characteristics OA1 input offset voltage OA2 input offset voltage OA2 current sinking capability OA2 current sourcing capability Peak detector P pull-up current Peak detector N pull-down current A mV mV mA mA A A 39010 71122 Rev. 007 Page 36 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 5.6 AC System Characteristics all parameters under normal operating conditions and default settings, unless otherwise stated; typical values at TA = 23 C and VCC = 5 V, RF at 433.92 MHz all parameters based on test circuits as shown in Fig. 17 to Fig. 19 Parameter Receive Characteristics Input sensitivity - FSK (standard) Input sensitivity - FSK (with carrier offset) Pmin, FSK f = 20kHz, 4kbps NRZ, BER 310-3 f = 20kHz, 4kbps NRZ, 90kHz carrier offset BER 310-3 100% on-off ratio 4kbps NRZ, BER 310-3 BER 310-3 -3 Symbol Condition Min Typ -107 Max Unit dBm Pmin, FSK, offs -104 dBm Input sensitivity - ASK Pmin, ASK -112 dBm Maximum input signal - FSK/FM Maximum input signal - ASK Spurious emission Image rejection of MIX2 IF Filter Parameters Center frequency 3dB bandwidth 40dB bandwidth Low voltage High voltage RSSI dynamic range RSSI slope FSK Demodulator Pmax, FSK 0 -10 -54 35 dBm dBm dBm dB MHz kHz MHz V V dB mV/dB mV/ kHz kbps kHz ms TXTL + 200k " C10 RSSI Characteristics Demodulator gain, low Y R A IN IM L E R P Pimag fIF B3dB B40dB 2 230 1.6 VLRSSI VHRSSI DRRSSI SRSSI 1 2.65 maximum 50 40 4 DGLOW f > 15kHz DGHIGH BDEM BWDEMOD f = 20kHz TXTL TRX f < 15kHz NRZ 230 0.9 15 100 ENRX from 0 to 1 ENRX from 0 to 1, depends on data slicer time constant, valid data at output max for VCORANGE=0 max for VCORANGE=0 depends on CPCUR Pmax, ASK BER 310 Pspur Demodulator gain, high Maximum data rate Frequency acceptance range Start-up Parameters Crystal start-up time Receiver start-up time PLL Parameters VCO gain @ 433MHz VCO gain @ 868MHz Charge pump current KVCO KVCO ICP 83 105 100 100 126 400 MHz/V MHz/V A 39010 71122 Rev. 007 Page 37 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 6 6.1 6.1.1 Test Circuits Standard FSK & ASK Reception in 8-Channel Preconfigured (ABC) Mode Averaging Data Slicer Configured for Bi-Phase Codes RB0 CB3 FSK/ASK output XTAL CX MFO 23 ROI 24 A B C VCCDIG 21 VEEDIG 20 A/SCLK 19 B/SDTA 18 C/SDEN 17 3-bit frequency selection DTAO 22 25 PDP 26 PDN 27 DFO 28 DF1 29 DF2 ENRX 16 LF 15 RX enable CF2 CF1 CB2 C8 C9 VCCVCO 14 RF L0 Y R A IN IM L E R P L1 30 VEEANA 31 LNAI MLX71122 32L QFN 5x5 TNK2 13 TNK1 12 VEEVCO 11 C3 RBS VEELNA VCCANA RBIAS 10 RSSI 9 SPISEL LNAO VEEIF MIXN 50 C1 C2 32 SLC MIXP MODSEL FSK/ASK C10 1 2 3 4 5 6 7 8 RSSI CB0 L3 C5 C6 C7 CB1 C4 VCC Fig. 17: Test circuit for FSK & ASK reception 39010 71122 Rev. 007 Page 38 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 6.2 6.2.1 Standard FSK & ASK Reception in SPI Mode Averaging Data Slicer Configured for Bi-Phase Codes RB0 CB3 FSK/ASK output XTAL CX MFO 23 ROI 24 CLK SDTA SDEN VCCDIG 21 VEEDIG 20 A/SCLK 19 B/SDTA 18 C/SDEN 17 3-wire bus SPI DTAO 22 25 PDP 26 PDN 27 DFO 28 DF1 29 DF2 ENRX 16 LF 15 CF2 RF L0 CF1 CB2 C8 C9 VCCVCO 14 Y R A IN IM L E R P L1 30 VEEANA 31 LNAI MLX71122 32L QFN 5x5 TNK2 13 TNK1 12 VEEVCO 11 C3 RBS VEELNA VCCANA RBIAS 10 RSSI 9 SPISEL 7 LNAO VEEIF MIXN 50 C1 C2 32 SLC MIXP MODSEL C10 1 2 3 4 5 6 8 RSSI CB0 L3 C5 C6 C7 CB1 C4 VCC Fig. 18: Test circuit for FSK & ASK reception 39010 71122 Rev. 007 Page 39 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 6.2.2 Peak Detector Data Slicer Configured for NRZ Codes RB0 CB3 FSK/ASK output XTAL CX MFO 23 ROI 24 CLK SDTA SDEN VCCDIG 21 VEEDIG 20 A/SCLK 19 B/SDTA 18 C/SDEN 17 3-wire bus SPI C11 C12 C8 C9 DTAO 22 25 PDP 26 PDN 27 DFO 28 DF1 29 DF2 ENRX 16 LF 15 CF2 RF L0 RBS CF1 CB2 VCCVCO 14 MLX71122 32L QFN 5x5 TNK2 13 TNK1 12 Y R A IN IM L E R P L1 30 VEEANA 31 LNAI VEEVCO 11 C3 VEELNA VCCANA RBIAS 10 RSSI 9 SPISEL 7 VEEIF LNAO MIXN 50 C1 C2 32 SLC MIXP MODSEL 1 2 3 4 5 6 8 RSSI CB0 L3 C5 C6 C7 CB1 C4 VCC Fig. 19: Test circuit for FSK & ASK reception 39010 71122 Rev. 007 Page 40 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 6.3 Test Circuit Component List Below table is for all test circuits shown in Figures 17 to 19. Part C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 CB0 CB1 CB2 CB3 CF1 CF2 CX RB0 RF RBS L0 L1 L3 XTAL Size 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 1210 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SMD 5x3.2 Value @ 315 MHz 3.9 pF 1.5 pF 100 pF 4.7 pF 100 pF 100 pF 1 nF 330 pF 150 pF 33 nF Value @ Value @ 433.92 MHz 868.3 MHz 4.7 pF 1.5 pF 100 pF 3.3 pF 100 pF 100 pF 1 nF 330 pF 150 pF 3.3 pF 1.5 pF 100 pF 2.7 pF 100 pF 100 pF 1 nF 330 pF 150 pF Value @ 915 MHz 1.5 pF 1.5 pF 100 pF 2.2 pF 100 pF 100 pF 1 nF 330 pF 150 pF Tol. 5% 5% 5% 5% 5% Description matching capacitor matching capacitor LNA input filtering capacitor LNA output tank capacitor MIX1 negative input matching capacitor MIX1 negative input matching 5% capacitor RSSI output low pass capacitor, 10% for data rate of 4 kbps NRZ data low-pass filter capacitor, 10% for data rate of 4 kbps NRZ data low-pass filter capacitor, 10% for data rate of 4 kbps NRZ 10% data slicer capacitor, for data rate of 4 kbps NRZ 33 nF 33 nF 33 nF not required in Figure 19 33 nF 33 nF 33 nF 33 nF not required in Figures. 17 and 18 33 nF 33 nF 33 nF 33 nF not required in Figures 17 and 18 10 F 10 F 10 F 470 pF 33 nF 33 nF 2.2 nF 27 pF 10 220 pF Y R A IN IM L E R P 10% 10 F decoupling capacitor, 10% low-noise power supply recommended 10% decoupling capacitor 10% decoupling capacitor 10% decoupling capacitor 5% 5% loop filter capacitor loop filter capacitor protection resistor 470 pF 33 nF 33 nF 470 pF 33 nF 33 nF 470 pF 33 nF 33 nF 2.2 nF 27 pF 10 2.2 nF 27 pF 10 2.2 nF 27 pF 10 220 pF 220 pF 220 pF 5% crystal series capacitor loop filter resistor reference bias resistor VCO tank inductor matching inductor LNA output tank inductor fundamental-mode crystal 5% 27 k 30 k 15 nH 47 nH 22 nH 47 k 30 k 8.2 nH 22 nH 5.6 nH 47 k 30 k 8.2 nH 15 nH 5.6 nH 5% 2% 5% 5% 5% 10.00000 MHz 20ppm cal., 30ppm temp. PKDET positive filtering capacitor, for data rate of 4 kbps NRZ PKDET negative filtering capacitor, 10% for data rate of 4 kbps NRZ 27 k 30 k 33 nH 68 nH 33 nH 39010 71122 Rev. 007 Page 41 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 7 Package Description The device MLX71122 is RoHS compliant. D 24 25 17 16 A3 E 32 1 e 8 b 9 A1 A Y R A IN IM L E R P exp osed pad E2 L D2 The "exposed pad" is not connected to internal ground, it should not be connected to the PCB. Fig. 20: 32L QFN 5x5 Quad all Dimension in mm D min max min max 4.75 5.25 0.187 0.207 E 4.75 5.25 0.187 0.207 D2 3.00 3.25 0.118 0.128 E2 3.00 3.25 0.118 0.128 A 0.80 1.00 0.0315 0.0393 A1 0 0.05 0 0.002 A3 0.20 L 0.3 0.5 0.0118 0.0197 e 0.50 b 0.18 0.30 0.0071 0.0118 all Dimension in inch 0.0079 0.0197 7.1 Soldering Information * The device MLX71122 is qualified for MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD-20 Page 42 of 44 Data Sheet Oct/07 39010 71122 Rev. 007 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 8 Reliability Information This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: Reflow Soldering SMD's (Surface Mount Devices) * * IPC/JEDEC J-STD-020 "Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)" EIA/JEDEC JESD22-A113 "Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2)" Wave Soldering SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * * EN60749-20 "Resistance of plastic- encapsulated SMD's to combined effect of moisture and soldering heat" EIA/JEDEC JESD22-B106 and EN60749-15 "Resistance to soldering temperature for through-hole mounted devices" Iron Soldering THD's (Through Hole Devices) * EN60749-15 "Resistance to soldering temperature for through-hole mounted devices" Solderability SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * EIA/JEDEC JESD22-B102 and EN60749-21 "Solderability" For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD's is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the Use of Certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality_leadfree.aspx Y R A IN IM L E R P 9 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 39010 71122 Rev. 007 Page 43 of 44 Data Sheet Oct/07 MLX71122 300 to 930MHz FSK/FM/ASK Receiver 10 Disclaimer 1) The information included in this documentation is subject to Melexis intellectual and other property rights. Reproduction of information is permissible only if the information will not be altered and is accompanied by all associated conditions, limitations and notices. 2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such altered documentation. 3) The information furnished by Melexis in this documentation is provided 'as is'. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation. 4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. Melexis disclaims any responsibility in connection herewith. 5) Melexis reserves the right to change the documentation, the specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. 6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the information in this documentation. 7) The product described in this documentation is intended for use in normal commercial applications. Applications requiring operation beyond ranges specified in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. 8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on www.melexis.com. (c) Melexis NV. All rights reserved. Y R A IN IM L E R P For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe, Africa: Phone: +32 1367 0495 E-mail: sales_europe@melexis.com Americas: Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com Asia: Phone: +32 1367 0495 E-mail: sales_asia@melexis.com ISO/TS 16949 and ISO14001 Certified 39010 71122 Rev. 007 Page 44 of 44 Data Sheet Oct/07 |
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