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| FQD1P50 / FQU1P50 December 2000 QFET FQD1P50 / FQU1P50 500V P-Channel MOSFET General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and commutation modes. These devices are well suited for electronic lamp ballasts based on the complementary half bridge topology. TM Features * * * * * * -1.2A, -500V, RDS(on) = 10.5 @VGS = -10 V Low gate charge ( typical 11 nC) Low Crss ( typical 6.0 pF) Fast switching 100% avalanche tested Improved dv/dt capability S D G! ! G S D-PAK FQD Series I-PAK GDS FQU Series ! D Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25C) Drain Current - Continuous (TC = 100C) Drain Current - Pulsed (Note 1) FQD1P50 / FQU1P50 -500 -1.2 -0.76 -4.8 30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W W/C C C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25C) * Power Dissipation (TC = 25C) 110 -1.2 3.8 -4.5 2.5 38 0.3 -55 to +150 300 TJ, TSTG TL - Derate above 25C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RJC RJA RJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient * Thermal Resistance, Junction-to-Ambient Typ ---Max 3.29 50 110 Units C/W C/W C/W * When mounted on the minimum pad size recommended (PCB Mount) (c)2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD1P50 / FQU1P50 Elerical Characteristics Symbol Parameter TC = 25C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS BVDSS / TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = -250 A ID = -250 A, Referenced to 25C VDS = -500 V, VGS = 0 V VDS = -400 V, TC = 125C VGS = -30 V, VDS = 0 V VGS = 30 V, VDS = 0 V -400 -------------1 -10 -100 100 V V/C A A nA nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = -250 A VGS = -10 V, ID = -0.6 A VDS = -50 V, ID = -0.6 A (Note 4) -3.0 --- -8.0 1.12 -5.0 10.5 -- V S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = -25 V, VGS = 0 V, f = 1.0 MHz ---270 40 6.0 350 50 8.0 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = -250 V, ID = -1.5 A, RG = 25 (Note 4, 5) -------- 9.0 25 27 30 11 2.0 5.6 30 60 65 70 14 --- ns ns ns ns nC nC nC VDS = -400 V, ID = -1.5 A, VGS = -10 V (Note 4, 5) Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = -1.2 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = -1.5 A, dIF / dt = 100 A/s (Note 4) ------ ---200 0.7 -1.2 -4.8 -5.0 --- A A V ns C Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 138mH, IAS = -1.2A, VDD = -50V, RG = 25 , Starting TJ = 25C 3. ISD -1.5A, di/dt 200A/s, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature (c)2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD1P50 / FQU1P50 Typical Characteristics 10 0 -I D , Drain Current [A] -I D, Drain Current [A] VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -6.0 V Bottom : -5.5 V Top : 10 0 150 10 -1 25 -55 -1 Notes : 1. 250 Pulse Test s 2. TC = 25 Notes : 1. VDS = -50V 2. 250 Pulse Test s 10 -2 10 -1 10 0 10 1 10 2 4 6 8 10 -VDS, Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 16 RDS(on) [], Drain-Source On-Resistance 14 12 VGS = - 20V -I DR , Reverse Drain Current [A] VGS = - 10V 10 0 10 8 Note : TJ = 25 150 25 Notes : 1. VGS = 0V 2. 250 Pulse Test s 6 0 1 2 3 4 10 -1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -ID , Drain Current [A] -VSD , Source-Drain Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 600 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 500 10 VDS = -100V VDS = -250V 400 -V GS , Gate-Source Voltage [V] Capacitance [pF] Ciss 8 VDS = -400V 300 6 Coss 200 Notes : 1. VGS = 0 V 2. f = 1 MHz 4 Crss 100 2 Note : ID = -1.5 A 0 -1 10 10 0 10 1 0 0 2 4 6 8 10 12 -VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics (c)2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD1P50 / FQU1P50 Typical Characteristics (Continued) 1.2 2.5 -BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.0 RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 1.5 1.0 1.0 0.9 Notes : 1. VGS = 0 V 2. ID = -250 A 0.5 Notes : 1. VGS = -10 V 2. ID = -0.75 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 1.2 1 10 Operation in This Area is Limited by R DS(on) 1.0 -I D, Drain Current [A] 100 s 1 ms 10 0 10 ms DC -I D, Drain Current [A] 3 0.8 0.6 0.4 10 -1 Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse o o 0.2 10 -2 10 0 10 1 10 2 10 0.0 25 50 75 100 125 150 -VDS, Drain-Source Voltage [V] TC, Case Temperature [] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature ( t) , T h e r m a l R e s p o n s e D = 0 .5 10 0 0 .2 0 .1 0 .0 5 10 -1 N o te s : 1 . Z J C( t) = 3 .2 9 /W M a x . 2 . D u ty F a c to r , D = t1 /t2 3 . T JM - T C = P D M * Z J C( t) 0 .0 2 0 .0 1 s in g le p u ls e PDM t1 t2 Z JC 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] Figure 11. Transient Thermal Response Curve (c)2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD1P50 / FQU1P50 Gate Charge Test Circuit & Waveform 50K 12V 200nF 300nF Same Type as DUT VDS VGS Qg -10V Qgs Qgd VGS DUT -3mA Charge Resistive Switching Test Circuit & Waveforms VDS VGS RG RL VDD td(on) t on tr td(off) t off tf VGS 10% -10V DUT VDS 90% Unclamped Inductive Switching Test Circuit & Waveforms L VDS ID RG DUT tp BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD tp Time VDS (t) VDD VDD ID (t) IAS BVDSS -10V (c)2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD1P50 / FQU1P50 Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT _ I SD L Driver RG Compliment of DUT (N-Channel) VDD VGS * dv/dt controlled by RG * ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V I SD ( DUT ) Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop Body Diode Recovery dv/dt VDD (c)2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD1P50 / FQU1P50 Package Dimensions DPAK 6.60 0.20 5.34 0.30 (0.50) (4.34) (0.50) 0.70 0.20 2.30 0.10 0.50 0.10 0.60 0.20 6.10 0.20 2.70 0.20 9.50 0.30 0.91 0.10 0.80 0.20 MAX0.96 2.30TYP [2.300.20] 0.76 0.10 2.30TYP [2.300.20] 0.89 0.10 0.50 0.10 1.02 0.20 2.30 0.20 (0.70) (0.90) (0.10) (3.05) 6.10 0.20 9.50 0.30 2.70 0.20 (2XR0.25) 0.76 0.10 (c)2000 Fairchild Semiconductor International (1.00) Rev. A2, December 2000 6.60 0.20 (5.34) (5.04) (1.50) MIN0.55 FQD1P50 / FQU1P50 Package Dimensions (Continued) IPAK 6.60 0.20 5.34 0.20 (0.50) (4.34) (0.50) 0.50 0.10 2.30 0.20 0.60 0.20 0.70 0.20 0.80 0.10 6.10 0.20 1.80 0.20 MAX0.96 0.76 0.10 9.30 0.30 2.30TYP [2.300.20] 2.30TYP [2.300.20] 0.50 0.10 (c)2000 Fairchild Semiconductor International 16.10 0.30 Rev. A2, December 2000 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM ISOPLANARTM MICROWIRETM POPTM PowerTrench(R) QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production (c)2000 Fairchild Semiconductor International Rev. A, January 2000 |
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