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| Design Idea DI-52 DPA-SwitchTM 60 W DC-DC Converter Application Telecom Device DPA426R Power Output 60 W Input Voltage 36-75 VDC Output Voltage 12 V Topology (R) Forward Sync. Rect. Design Highlights * Low component count * High efficiency: 91.5% at 36 VDC using synchronous rectification * Capacitor coupled synchronous rectification allows higher output voltages without overstressing MOSFET gates * No current sense resistor or current transformer required * Output overload, open loop and thermal protection * 300 kHz switching frequency to allow sufficient transformer reset time * 3.55 x 2.1 x 0.6 inch (approx. 13.4 W/cubic inch) Resistor R1 programs the under/over voltages and linearly reduces the maximum duty cycle with input voltage to prevent core saturation during load transients. Components D1, D2, C9, and L2 implement a resonant clamp circuit to catch and re-circulate the transformer leakage energy during normal operation, with Zener VR1 providing absolute clamping for transient conditions. Capacitor C21 charges the gate of Q2, the forward synchronous rectifier MOSFET. Resistor R21 limits gate oscillation and R22 provides gate pull down. Zener diode VR20 limits the Q2 gate voltage during conduction and also reverse charges (resets) C21 during the Q2 off time. A similar drive technique is used for the catch synchronous rectifier MOSFET Q1 (with C22, R23, R24, and VR21). MOSFET Q1 is driven by the transformer (T1) reset voltage and operates only when Q2 is off. Diode D20 provides a Operation DPA-Switch greatly simplifies the design compared to a discrete implementation. The capacitor coupled synchronous rectifier drive used in this design is useful for higher voltage outputs, still allowing passive MOSFET drive without gate overvoltage, which would result from direct resistor drive. C7 1 nF 1.5 kV T1 6,7 R14 10 C20 C21 1 nF 2.2 nF VR20 15 V L4 40 H 10,9 4,5 C23 C24 100 F 100 F 16 V 16 V C25 1 F 50 V 12 V, 5 A + VIN 36-75 VDC L1 1 H 2.5 A D1 ESD1 R1 619 k 1% 1 R21 R22 R20 10 10 k 0.5 1W 9,8 Q2 Si4486 VR21 R23 15 V 10 D20 12 CWQ 10 FN RTN Q1 Si4486 R24 10 k C1-C4 0.22 F 100 V C9 150 pF 200 V 4 5 2 C22 1 nF D3 BAV19WS L3 2.2 mH 40 mA R7 U2 10 k R10 38 k 1% D4 BAV19WS C8 1 F L2 220 H D L U1 DPA426R DPA-Switch C U2 PC357 NT D3 BAV19WS R6 150 C15 10 F 10 V CONTROL C13 100 nF R12 5.1 C17 1 F D2 ESD1 S VR1 SMBJ 150 A X F R4 1.0 C5 0.22 F C6 68 F 10 V R9 220 -VIN R3 11 k 1% U3 LMV431 AIM5X R11 10 k 1% PI-3550-062403 Figure 1. DPA426R - 60 W, 12 V, 5 A, DC-DC Converter. . DI-52 www.powerint.com July 2003 DI-52 conduction path for the output inductor (L4) current when the transformer reset is complete. TRANSFORMER PARAMETERS Core Material Bobbin Ferroxcube P/N: EFD25, ungapped 10-pin EFD25 surface mount bobbin Primary 5T + 5T, 4 x 26 AWG Bias 5T, 1 x 30 AWG 12 V 6T, 4 x 26 AWG Bias (2-5), Primary-1 (4-NC), 12 V (9,10-6,7), Primary-2 (NC-1) Pin (1-4): 190 H 25% @ 300 kHz 3.8 MHz (minimum) 1 H (maximum) Key Design Points * Transformer core reset is critical in this design. MOSFET gate loading will affect the transformer-reset waveform. Capacitors C20, C22 and CQ1GS will all load transformer reset. Choose values to ensure sufficient reset at low line and safe maximum drain voltage at high line. Also use 300 kHz operation for longest reset time. * Capacitors C20 and C22 will capacitively drive MOSFET gate capacitances CQ2GS and CQ1GS, respectively. C20 and C22 should be chosen to ensure that gate drive voltage attains turn-on threshold of MOSFET (VgTH) at worst case conditions (low line for forward MOSFET). * Reduce transformer leakage inductance by filling each winding layer across the entire width of the bobbin. PI-3551-060503 Winding Details Winding Order and Pin Numbers Primary Inductance Primary Resonant Frequency Leakage Inductance Table 1. Transformer Construction Information. 100 INDUCTOR PARAMETERS Core Material Ferroxcube P/N: EFD20-3F3 gap for inductance required 10-pin EFD20 surface mount bobbin Main 18T, 3 x 24 AWG Main (4,5-9,10) Pin (4,5-9,10): 40 H 10% @ 300 kHz 90 Efficiency (%) 80 Bobbin Winding Details 70 60 36 VDC 48 VDC 72 VDC Winding Order and Pin Numbers Inductance 50 0 1 2 3 4 5 Table 2. L4 Output Inductor Design Parameters. Pout (W) Figure 2. Efficiency vs. Output Power. A 7/03 www.powerint.com |
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